mbox series

[v3-a,00/27] target/arm: Scalable Vector Extension

Message ID 20180516223007.10256-1-richard.henderson@linaro.org
Headers show
Series target/arm: Scalable Vector Extension | expand

Message

Richard Henderson May 16, 2018, 10:29 p.m. UTC 
This is the first third, more or less, of my current patch set.
I'm sending only this portion now, rather than another monster
set all at once.

The major change is to move the call to sve_access_check inside
any final decode reject that might be required.  There are other
minor cleanups to patch integrity and comments.

The changes are mostly trivial from the February v2 patch set,
so if an R-b was given, I have retained it.

That leaves 4, 7, 8, and 26 (new) as unreviewed.

The patch that enables SVE for aarch64-linux-user is not present.


r~


Richard Henderson (27):
  target/arm: Introduce translate-a64.h
  target/arm: Add SVE decode skeleton
  target/arm: Implement SVE Bitwise Logical - Unpredicated Group
  target/arm: Implement SVE load vector/predicate
  target/arm: Implement SVE predicate test
  target/arm: Implement SVE Predicate Logical Operations Group
  target/arm: Implement SVE Predicate Misc Group
  target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group
  target/arm: Implement SVE Integer Reduction Group
  target/arm: Implement SVE bitwise shift by immediate (predicated)
  target/arm: Implement SVE bitwise shift by vector (predicated)
  target/arm: Implement SVE bitwise shift by wide elements (predicated)
  target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group
  target/arm: Implement SVE Integer Multiply-Add Group
  target/arm: Implement SVE Integer Arithmetic - Unpredicated Group
  target/arm: Implement SVE Index Generation Group
  target/arm: Implement SVE Stack Allocation Group
  target/arm: Implement SVE Bitwise Shift - Unpredicated Group
  target/arm: Implement SVE Compute Vector Address Group
  target/arm: Implement SVE floating-point exponential accelerator
  target/arm: Implement SVE floating-point trig select coefficient
  target/arm: Implement SVE Element Count Group
  target/arm: Implement SVE Bitwise Immediate Group
  target/arm: Implement SVE Integer Wide Immediate - Predicated Group
  target/arm: Implement SVE Permute - Extract Group
  target/arm: Extend vec_reg_offset to larger sizes
  target/arm: Implement SVE Permute - Unpredicated Group

 target/arm/cpu.h           |    8 +-
 target/arm/helper-sve.h    |  450 ++++++++
 target/arm/helper.h        |    1 +
 target/arm/translate-a64.h |  118 ++
 target/arm/sve_helper.c    | 1676 +++++++++++++++++++++++++++
 target/arm/translate-a64.c |  119 +-
 target/arm/translate-sve.c | 2203 ++++++++++++++++++++++++++++++++++++
 .gitignore                 |    1 +
 target/arm/Makefile.objs   |   10 +
 target/arm/sve.decode      |  446 ++++++++
 10 files changed, 4933 insertions(+), 99 deletions(-)
 create mode 100644 target/arm/helper-sve.h
 create mode 100644 target/arm/translate-a64.h
 create mode 100644 target/arm/sve_helper.c
 create mode 100644 target/arm/translate-sve.c
 create mode 100644 target/arm/sve.decode

-- 
2.17.0

Comments

no-reply@patchew.org May 16, 2018, 11:01 p.m. UTC | #1 
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180516223007.10256-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v3-a 00/27] target/arm: Scalable Vector Extension

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]               patchew/20180516223007.10256-1-richard.henderson@linaro.org -> patchew/20180516223007.10256-1-richard.henderson@linaro.org
Switched to a new branch 'test'
d5d6c8f1c1 target/arm: Implement SVE Permute - Unpredicated Group
3e81d585ea target/arm: Extend vec_reg_offset to larger sizes
b1fd0b35ed target/arm: Implement SVE Permute - Extract Group
7440d418b4 target/arm: Implement SVE Integer Wide Immediate - Predicated Group
c35230538c target/arm: Implement SVE Bitwise Immediate Group
b74492415e target/arm: Implement SVE Element Count Group
4c4d56ab60 target/arm: Implement SVE floating-point trig select coefficient
9037d7db89 target/arm: Implement SVE floating-point exponential accelerator
4dcb0e1e0d target/arm: Implement SVE Compute Vector Address Group
6ebd038b3f target/arm: Implement SVE Bitwise Shift - Unpredicated Group
6f313170d7 target/arm: Implement SVE Stack Allocation Group
3ac441769e target/arm: Implement SVE Index Generation Group
55bb3f6e0f target/arm: Implement SVE Integer Arithmetic - Unpredicated Group
a903947c6e target/arm: Implement SVE Integer Multiply-Add Group
61ca1958eb target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group
10ebd0fdb6 target/arm: Implement SVE bitwise shift by wide elements (predicated)
2bc70c192a target/arm: Implement SVE bitwise shift by vector (predicated)
df68c49188 target/arm: Implement SVE bitwise shift by immediate (predicated)
f7ff94163d target/arm: Implement SVE Integer Reduction Group
b1496deb00 target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group
c5f223b5fb target/arm: Implement SVE Predicate Misc Group
a437ba8c21 target/arm: Implement SVE Predicate Logical Operations Group
c2eb96dd2f target/arm: Implement SVE predicate test
d8c66d6568 target/arm: Implement SVE load vector/predicate
356c9c883c target/arm: Implement SVE Bitwise Logical - Unpredicated Group
932a4173aa target/arm: Add SVE decode skeleton
313294c78c target/arm: Introduce translate-a64.h

=== OUTPUT BEGIN ===
Checking PATCH 1/27: target/arm: Introduce translate-a64.h...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#256: 
new file mode 100644

total: 0 errors, 1 warnings, 337 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 2/27: target/arm: Add SVE decode skeleton...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

total: 0 errors, 1 warnings, 140 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/27: target/arm: Implement SVE Bitwise Logical - Unpredicated Group...
Checking PATCH 4/27: target/arm: Implement SVE load vector/predicate...
Checking PATCH 5/27: target/arm: Implement SVE predicate test...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#21: 
new file mode 100644

total: 0 errors, 1 warnings, 197 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/27: target/arm: Implement SVE Predicate Logical Operations Group...
Checking PATCH 7/27: target/arm: Implement SVE Predicate Misc Group...
Checking PATCH 8/27: target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group...
Checking PATCH 9/27: target/arm: Implement SVE Integer Reduction Group...
Checking PATCH 10/27: target/arm: Implement SVE bitwise shift by immediate (predicated)...
Checking PATCH 11/27: target/arm: Implement SVE bitwise shift by vector (predicated)...
Checking PATCH 12/27: target/arm: Implement SVE bitwise shift by wide elements (predicated)...
ERROR: spaces required around that '*' (ctx:WxV)
#118: FILE: target/arm/translate-sve.c:505:
+static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a,         \
                                                               ^

total: 1 errors, 0 warnings, 110 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 13/27: target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group...
ERROR: spaces required around that '-' (ctx:VxV)
#185: FILE: target/arm/sve_helper.c:564:
+#define DO_FABS(N)    (N & ((__typeof(N))-1 >> 1))
                                          ^

ERROR: spaces required around that '-' (ctx:VxV)
#191: FILE: target/arm/sve_helper.c:570:
+#define DO_FNEG(N)    (N ^ ~((__typeof(N))-1 >> 1))
                                           ^

total: 2 errors, 0 warnings, 347 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 14/27: target/arm: Implement SVE Integer Multiply-Add Group...
Checking PATCH 15/27: target/arm: Implement SVE Integer Arithmetic - Unpredicated Group...
Checking PATCH 16/27: target/arm: Implement SVE Index Generation Group...
Checking PATCH 17/27: target/arm: Implement SVE Stack Allocation Group...
Checking PATCH 18/27: target/arm: Implement SVE Bitwise Shift - Unpredicated Group...
Checking PATCH 19/27: target/arm: Implement SVE Compute Vector Address Group...
Checking PATCH 20/27: target/arm: Implement SVE floating-point exponential accelerator...
Checking PATCH 21/27: target/arm: Implement SVE floating-point trig select coefficient...
Checking PATCH 22/27: target/arm: Implement SVE Element Count Group...
Checking PATCH 23/27: target/arm: Implement SVE Bitwise Immediate Group...
Checking PATCH 24/27: target/arm: Implement SVE Integer Wide Immediate - Predicated Group...
Checking PATCH 25/27: target/arm: Implement SVE Permute - Extract Group...
Checking PATCH 26/27: target/arm: Extend vec_reg_offset to larger sizes...
Checking PATCH 27/27: target/arm: Implement SVE Permute - Unpredicated Group...
ERROR: space prohibited before that close parenthesis ')'
#116: FILE: target/arm/sve_helper.c:1575:
+DO_INSR(sve_insr_d, uint64_t, )

ERROR: space prohibited before that close parenthesis ')'
#190: FILE: target/arm/sve_helper.c:1649:
+DO_TBL(sve_tbl_d, uint64_t, )

total: 2 errors, 0 warnings, 330 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


---
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Please send your feedback to patchew-devel@redhat.com
Peter Maydell May 18, 2018, 12:16 p.m. UTC | #2 
On 16 May 2018 at 23:29, Richard Henderson <richard.henderson@linaro.org> wrote:
> This is the first third, more or less, of my current patch set.

> I'm sending only this portion now, rather than another monster

> set all at once.

>

> The major change is to move the call to sve_access_check inside

> any final decode reject that might be required.  There are other

> minor cleanups to patch integrity and comments.

>

> The changes are mostly trivial from the February v2 patch set,

> so if an R-b was given, I have retained it.

>

> That leaves 4, 7, 8, and 26 (new) as unreviewed.

>

> The patch that enables SVE for aarch64-linux-user is not present.


I've applied 1-25 to target-arm.next.

thanks
-- PMM