| Message ID | 20180514221219.7091-13-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | softfloat patch roundup | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > This is now handled properly by the generic softfloat code. > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/helper-a64.c | 1 - > target/arm/helper.c | 12 ++---------- > 2 files changed, 2 insertions(+), 11 deletions(-) > > diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c > index 6f0eb83661..f92bdea732 100644 > --- a/target/arm/helper-a64.c > +++ b/target/arm/helper-a64.c > @@ -466,7 +466,6 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) > set_float_rounding_mode(float_round_to_zero, &tstat); > set_float_exception_flags(0, &tstat); > r = float64_to_float32(a, &tstat); > - r = float32_maybe_silence_nan(r, &tstat); > exflags = get_float_exception_flags(&tstat); > if (exflags & float_flag_inexact) { > r = make_float32(float32_val(r) | 1); > diff --git a/target/arm/helper.c b/target/arm/helper.c > index e05c7230d4..db8bbe52a6 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -11348,20 +11348,12 @@ FLOAT_CONVS(ui, d, 64, u) > /* floating point conversion */ > float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) > { > - float64 r = float32_to_float64(x, &env->vfp.fp_status); > - /* ARM requires that S<->D conversion of any kind of NaN generates > - * a quiet NaN by forcing the most significant frac bit to 1. > - */ > - return float64_maybe_silence_nan(r, &env->vfp.fp_status); > + return float32_to_float64(x, &env->vfp.fp_status); > } > > float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) > { > - float32 r = float64_to_float32(x, &env->vfp.fp_status); > - /* ARM requires that S<->D conversion of any kind of NaN generates > - * a quiet NaN by forcing the most significant frac bit to 1. > - */ > - return float32_maybe_silence_nan(r, &env->vfp.fp_status); > + return float64_to_float32(x, &env->vfp.fp_status); > } > > /* VFP3 fixed point conversion. */ -- Alex Bennée
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 6f0eb83661..f92bdea732 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -466,7 +466,6 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) set_float_rounding_mode(float_round_to_zero, &tstat); set_float_exception_flags(0, &tstat); r = float64_to_float32(a, &tstat); - r = float32_maybe_silence_nan(r, &tstat); exflags = get_float_exception_flags(&tstat); if (exflags & float_flag_inexact) { r = make_float32(float32_val(r) | 1); diff --git a/target/arm/helper.c b/target/arm/helper.c index e05c7230d4..db8bbe52a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11348,20 +11348,12 @@ FLOAT_CONVS(ui, d, 64, u) /* floating point conversion */ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) { - float64 r = float32_to_float64(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float64_maybe_silence_nan(r, &env->vfp.fp_status); + return float32_to_float64(x, &env->vfp.fp_status); } float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) { - float32 r = float64_to_float32(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float32_maybe_silence_nan(r, &env->vfp.fp_status); + return float64_to_float32(x, &env->vfp.fp_status); } /* VFP3 fixed point conversion. */