[Xen-devel,5/7] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

This driver follows an approach similar to smmu driver. The intent here
is to reuse as much Linux code as possible.
- Glue code has been introduced to bridge the API calls.
- Called Linux functions from the Xen IOMMU function calls.
- Xen modifications are preceded by /*Xen: comment */
- xen/linux_compat: Add a Linux compat header
  For porting files directly from Linux it is useful to have a function mapping
  definitions from Linux to Xen. This file adds common API functions and
  other defines that are needed for porting arm SMMU drivers.

Signed-off-by: Sameer Goel <sameer.goel@linaro.org>
---
 xen/arch/arm/p2m.c                    |   1 +
 xen/drivers/Kconfig                   |   2 +
 xen/drivers/passthrough/arm/Kconfig   |   8 +
 xen/drivers/passthrough/arm/Makefile  |   1 +
 xen/drivers/passthrough/arm/smmu-v3.c | 892 ++++++++++++++++++++++++++++++++--
 xen/include/xen/linux_compat.h        |  84 ++++
 6 files changed, 959 insertions(+), 29 deletions(-)
 create mode 100644 xen/drivers/passthrough/arm/Kconfig
 create mode 100644 xen/include/xen/linux_compat.h

Hi,

On 09/02/18 03:10, Sameer Goel wrote:
> This driver follows an approach similar to smmu driver. The intent here
> is to reuse as much Linux code as possible.
> - Glue code has been introduced to bridge the API calls.
> - Called Linux functions from the Xen IOMMU function calls.
> - Xen modifications are preceded by /*Xen: comment */
> - xen/linux_compat: Add a Linux compat header
>    For porting files directly from Linux it is useful to have a function mapping
>    definitions from Linux to Xen. This file adds common API functions and
>    other defines that are needed for porting arm SMMU drivers.

I understand Roger asked for it, but that was not a really wise choice 
given the size of this patch. Anyway, let's keep it like that.

> 
> Signed-off-by: Sameer Goel <sameer.goel@linaro.org>
> ---
>   xen/arch/arm/p2m.c                    |   1 +
>   xen/drivers/Kconfig                   |   2 +
>   xen/drivers/passthrough/arm/Kconfig   |   8 +
>   xen/drivers/passthrough/arm/Makefile  |   1 +
>   xen/drivers/passthrough/arm/smmu-v3.c | 892 ++++++++++++++++++++++++++++++++--
>   xen/include/xen/linux_compat.h        |  84 ++++

You need to CC the REST maintainers for that.

>   6 files changed, 959 insertions(+), 29 deletions(-)
>   create mode 100644 xen/drivers/passthrough/arm/Kconfig
>   create mode 100644 xen/include/xen/linux_compat.h
> 
> diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
> index 65e8b9c6ea..fef7605fd6 100644
> --- a/xen/arch/arm/p2m.c
> +++ b/xen/arch/arm/p2m.c
> @@ -1460,6 +1460,7 @@ err:
>   static void __init setup_virt_paging_one(void *data)
>   {
>       unsigned long val = (unsigned long)data;
> +    /* SMMUv3 S2 cfg vtcr reuses the following value */
>       WRITE_SYSREG32(val, VTCR_EL2);
>       isb();
>   }
> diff --git a/xen/drivers/Kconfig b/xen/drivers/Kconfig
> index bc3a54f0ea..612655386d 100644
> --- a/xen/drivers/Kconfig
> +++ b/xen/drivers/Kconfig
> @@ -12,4 +12,6 @@ source "drivers/pci/Kconfig"
>   
>   source "drivers/video/Kconfig"
>   
> +source "drivers/passthrough/arm/Kconfig"
> +
>   endmenu
> diff --git a/xen/drivers/passthrough/arm/Kconfig b/xen/drivers/passthrough/arm/Kconfig
> new file mode 100644
> index 0000000000..cda899f608
> --- /dev/null
> +++ b/xen/drivers/passthrough/arm/Kconfig
> @@ -0,0 +1,8 @@
> +
> +config ARM_SMMU_v3
> +	bool "ARM SMMUv3 Support"
> +	depends on ARM_64

Why the dependency on Arm64 here?

> +	help
> +	 Support for implementations of the ARM System MMU architecture
> +	 version 3.
> +
> diff --git a/xen/drivers/passthrough/arm/Makefile b/xen/drivers/passthrough/arm/Makefile
> index f4cd26e15d..e14732b55c 100644
> --- a/xen/drivers/passthrough/arm/Makefile
> +++ b/xen/drivers/passthrough/arm/Makefile
> @@ -1,2 +1,3 @@
>   obj-y += iommu.o
>   obj-y += smmu.o
> +obj-$(CONFIG_ARM_SMMU_v3) += smmu-v3.o
> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c
> index e67ba6c40f..f43485fe6e 100644
> --- a/xen/drivers/passthrough/arm/smmu-v3.c
> +++ b/xen/drivers/passthrough/arm/smmu-v3.c
> @@ -18,28 +18,414 @@
>    * Author: Will Deacon <will.deacon@arm.com>
>    *
>    * This driver is powered by bad coffee and bombay mix.
> + *
> + *
> + * Based on Linux drivers/iommu/arm-smmu-v3.c
> + * => commit 7aa8619a66aea52b145e04cbab4f8d6a4e5f3f3b
> + *
> + * Xen modifications:
> + * Sameer Goel <sameer.goel@linaro.org>
> + * Copyright (C) 2017, The Linux Foundation, All rights reserved.
> + *
> + */

[...]

> +static void *dmam_alloc_coherent(struct device *dev, size_t size,
> +			   dma_addr_t *dma_handle, gfp_t gfp)
> +{
> +	void *vaddr;
> +	unsigned long alignment = size;
> +
> +	/*
> +	 * _xzalloc requires that the (align & (align -1)) = 0. Most of the
> +	 * allocations in SMMU code should send the right value for size. In
> +	 * case this is not true print a warning and align to the size of a
> +	 * (void *)
> +	 */
> +	if (size & (size - 1)) {
> +		dev_warn(dev, "Fixing alignment for the DMA buffer\n");
> +		alignment = sizeof(void *);
> +	}
> +
> +	vaddr = _xzalloc(size, alignment);
> +	if (!vaddr) {
> +		dev_err(dev, "DMA allocation failed\n");
> +		return NULL;
> +	}
> +
> +	*dma_handle = virt_to_maddr(vaddr);
> +
> +	return vaddr;
> +}
> +
> +

One newline should be enough.

> +static void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
> +			dma_addr_t dma_handle)
> +{
> +	xfree(vaddr);
> +}
> +
> +/* Xen: Stub out DMA domain related functions */
> +#define iommu_get_dma_cookie(dom) 0
> +#define iommu_put_dma_cookie(dom)
> +
> +/* Xen: Stub out module param related function */
> +#define module_param_named(a, b, c, d)
> +#define MODULE_PARM_DESC(a, b)
> +
> +#define dma_set_mask_and_coherent(d, b) 0
> +
> +#define of_dma_is_coherent(n) 0
> +
> +#define MODULE_DEVICE_TABLE(type, name)
> +
> +static void __iomem *devm_ioremap_resource(struct device *dev,
> +					   struct resource *res)
> +{
> +	void __iomem *ptr;
> +
> +	if (!res || res->type != IORESOURCE_MEM) {
> +		dev_err(dev, "Invalid resource\n");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	ptr = ioremap_nocache(res->addr, res->size);
> +	if (!ptr) {
> +		dev_err(dev,
> +			"ioremap failed (addr 0x%"PRIx64" size 0x%"PRIx64")\n",
> +			res->addr, res->size);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	return ptr;
> +}
> +
> +/* Xen: Compatibility define for iommu_domain_geometry.*/
> +struct iommu_domain_geometry {
> +	dma_addr_t aperture_start; /* First address that can be mapped    */
> +	dma_addr_t aperture_end;   /* Last address that can be mapped     */
> +	bool force_aperture;       /* DMA only allowed in mappable range? */
> +};
> +
> +

Same here.

[...]

> +
> +/*
> + * Xen: The pgtable_ops are used by the S1 translations, so return the dummy
> + * address.
> + */
> +#define alloc_io_pgtable_ops(f, c, o) ((struct io_pgtable_ops *)0x0)

I am slightly confused, on a previous e-mail you suggested that 0x0 is 
not possible to use. The comment in arm_smmu-domain_finalise seems to 
confirm that. So why the 0x0 here?

> +#define free_io_pgtable_ops(o)

Please use do { } while (0)

[...]

> @@ -1232,7 +1634,7 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)
>   
>   	dev_info(smmu->dev, "unexpected PRI request received:\n");
>   	dev_info(smmu->dev,
> -		 "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n",
> +		 "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova %#" PRIx64 "\n",
>   		 sid, ssid, grpid, last ? "L" : "",
>   		 evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",
>   		 evt[0] & PRIQ_0_PERM_READ ? "R" : "",
> @@ -1346,6 +1748,8 @@ static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev)
>   {
>   	arm_smmu_gerror_handler(irq, dev);
>   	arm_smmu_cmdq_sync_handler(irq, dev);
> +	/*Xen: No threaded irq. So call the required function from here */

NIT: /* Xen: ... */

> +	arm_smmu_combined_irq_thread(irq, dev);
>   	return IRQ_WAKE_THREAD;
>   }
>   

[...]

> @@ -1783,7 +2239,14 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
>   	return sid < limit;
>   }
>   
> +/* Xen: Unused */
> +#if 0
>   static struct iommu_ops arm_smmu_ops;
> +#endif
> +
> +/* Xen: Redefine arm_smmu_ops to what fwspec should evaluate */
> +static const struct iommu_ops arm_smmu_iommu_ops;
> +#define arm_smmu_ops arm_smmu_iommu_ops

Hmmmmm. Why is that necessary? arm_smmu_iommu_ops is added in this 
patch. So can't you just name the structure arm_smmu_ops?

Furthermore, I would be ok to leave to remove the const as Linux does 
not do it.

>   
>   static int arm_smmu_add_device(struct device *dev)
>   {
> @@ -1791,8 +2254,11 @@ static int arm_smmu_add_device(struct device *dev)
>   	struct arm_smmu_device *smmu;
>   	struct arm_smmu_master_data *master;
>   	struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> +#if 0 /*Xen: iommu_group is not needed */
>   	struct iommu_group *group;
> +#endif
>   
> +	/* Xen: fwspec->ops are not needed */

You don't change this code. So why this comment?

>   	if (!fwspec || fwspec->ops != &arm_smmu_ops)
>   		return -ENODEV;
>   	/*
> @@ -1830,6 +2296,11 @@ static int arm_smmu_add_device(struct device *dev)
>   		}
>   	}
>   
> +/*
> + * Xen: Do not need an iommu group as the stream data is carried by the SMMU

NIT: "We don't need...".

> + * master device object

NIT: Missing full stop.

> + */
> +#if 0
>   	group = iommu_group_get_for_dev(dev);
>   	if (!IS_ERR(group)) {
>   		iommu_group_put(group);

[...]

> @@ -2316,9 +2800,13 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
>   		 * Cavium ThunderX2 implementation doesn't not support unique
>   		 * irq lines. Use single irq line for all the SMMUv3 interrupts.
>   		 */
> -		ret = devm_request_threaded_irq(smmu->dev, irq,
> +		/*
> +		 * Xen: Does not support threaded irqs, so serialise the setup.
> +		 * This is the same for pris and event interrupt lines on other
> +		 * systems
> +		 */
> +		ret = devm_request_irq(smmu->dev, irq,
>   					arm_smmu_combined_irq_handler,
> -					arm_smmu_combined_irq_thread,
>   					IRQF_ONESHOT,
>   					"arm-smmu-v3-combined-irq", smmu);

On "RFC v4", I asked a question which was left unanswered. Here the 
conversation:

Me: Above you did implemented a dummy implementation of
     devm_request_threaded_irq(...). So why did you replace the code here?

You: The replacement worked well for other functions, where the handler 
was not defined. So, the wrapper function calls devm_request_irq with 
the argument passed in as thread. In this case really the handler hits 
first and it calls the thread in response. I can modify the code to make 
this fit into the api but in that case I will need to swap around the 
functions so number of line changes will stay the same. Tell me your 
preference.

Me: I don't understand what you mean here. Would it be possible to give 
a concrete example?

>   		if (ret < 0)

[...]

> @@ -2703,7 +3200,7 @@ static inline int arm_smmu_device_acpi_probe(struct platform_device *pdev,
>   static int arm_smmu_device_dt_probe(struct platform_device *pdev,
>   				    struct arm_smmu_device *smmu)
>   {
> -	struct device *dev = &pdev->dev;
> +	struct device *dev = pdev;
>   	u32 cells;
>   	int ret = -EINVAL;
>   
> @@ -2716,6 +3213,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev,
>   
>   	parse_driver_options(smmu);
>   
> +	/* Xen: of_dma_is_coherent is a stub till dt support is introduced */
>   	if (of_dma_is_coherent(dev->of_node))

On RFC v4, I requested to move the message on top of of_dma_is_coherent 
stub and add a WARN/WARN_ON(). Please address it.

>   		smmu->features |= ARM_SMMU_FEAT_COHERENCY;
>   

[...]

> @@ -2844,9 +3351,20 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>   		if (ret)
>   			return ret;
>   	}
> +#endif
> +	/*
> +	 * Xen: Keep a list of all probed devices. This will be used to query
> +	 * the smmu devices based on the fwnode.
> +	 */
> +	INIT_LIST_HEAD(&smmu->devices);
> +	spin_lock(&arm_smmu_devices_lock);
> +	list_add(&smmu->devices, &arm_smmu_devices);
> +	spin_unlock(&arm_smmu_devices_lock);
>   	return 0;
>   }
>   
> +/* Xen: Unused function */
> +#if 0
>   static int arm_smmu_device_remove(struct platform_device *pdev)
>   {
>   	struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
> @@ -2860,6 +3378,8 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev)
>   {
>   	arm_smmu_device_remove(pdev);
>   }
> +#endif
> +

Newline not necessary.

>    >   static const struct of_device_id arm_smmu_of_match[] = {
>   	{ .compatible = "arm,smmu-v3", },

[...]

> diff --git a/xen/include/xen/linux_compat.h b/xen/include/xen/linux_compat.h
> new file mode 100644
> index 0000000000..8037be0a3e
> --- /dev/null
> +++ b/xen/include/xen/linux_compat.h
> @@ -0,0 +1,84 @@
> +/******************************************************************************
> + * include/xen/linux_compat.h
> + *
> + * Compatibility defines for porting code from Linux to Xen
> + *
> + * Copyright (c) 2017 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef __XEN_LINUX_COMPAT_H__
> +#define __XEN_LINUX_COMPAT_H__
> +
> +#include <asm/types.h>
> +
> +typedef paddr_t phys_addr_t;
> +typedef paddr_t dma_addr_t;
> +
> +typedef unsigned int gfp_t;
> +#define GFP_KERNEL 0
> +#define __GFP_ZERO 0x01U

No need to the hexa here. 1U is much clearer.

> +
> +/* Helpers for IRQ functions */
> +#define free_irq release_irq
> +
> +enum irqreturn {
> +    IRQ_NONE,
> +    IRQ_HANDLED,
> +    IRQ_WAKE_THREAD,
> +};
> +
> +typedef enum irqreturn irqreturn_t;
> +
> +/* Device logger functions */
> +#define dev_dbg(dev, fmt, ...) printk(XENLOG_DEBUG fmt, ## __VA_ARGS__)
> +#define dev_notice(dev, fmt, ...) printk(XENLOG_INFO fmt, ## __VA_ARGS__)
> +#define dev_warn(dev, fmt, ...) printk(XENLOG_WARNING fmt, ## __VA_ARGS__)
> +#define dev_err(dev, fmt, ...) printk(XENLOG_ERR fmt, ## __VA_ARGS__)
> +#define dev_info(dev, fmt, ...) printk(XENLOG_INFO fmt, ## __VA_ARGS__)
> +
> +#define dev_err_ratelimited(dev, fmt, ...)                  \
> +     printk(XENLOG_ERR fmt, ## __VA_ARGS__)
> +
> +#define dev_name(dev) dt_node_full_name(dev_to_dt(dev))
> +
> +/* Alias to Xen allocation helpers */
> +#define kfree xfree
> +#define kmalloc(size, flags) ({\
> +	void *__ret_alloc = NULL; \
> +	if (flags & __GFP_ZERO) \
> +		__ret_alloc = _xzalloc(size, sizeof(void *)); \

That's Xen code, so please avoid using hard tabs.

> +	else \
> +		__ret_alloc = _xmalloc(size, sizeof(void *)); \
> +	__ret_alloc; \
> +})

Could we make at least kmalloc and kmalloc_array static inline? This 
will add safety and make easier to read (the \ are not indented at all).

> +#define kzalloc(size, flags)        _xzalloc(size, sizeof(void *))
> +#define devm_kzalloc(dev, size, flags)  _xzalloc(size, sizeof(void *))
> +#define kmalloc_array(size, n, flags) ({\
> +	void *__ret_alloc = NULL; \
> +	if (flags & __GFP_ZERO) \
> +		__ret_alloc = _xzalloc_array(size, sizeof(void *), n); \
> +	else \
> +		__ret_alloc = _xmalloc_array(size, sizeof(void *), n); \
> +	__ret_alloc; \
> +})
> +
> +/* Alias to Xen time functions */
> +#define ktime_t s_time_t
> +#define ktime_get()             (NOW())
> +#define ktime_add_us(t,i)       (t + MICROSECS(i))
> +#define ktime_compare(t,i)      (t > (i))
> +
> +#endif /* __XEN_LINUX_COMPAT_H__ */
> 

Cheers,

>>> On 01.03.18 at 15:07, <julien.grall@arm.com> wrote:
> On 09/02/18 03:10, Sameer Goel wrote:
>> This driver follows an approach similar to smmu driver. The intent here
>> is to reuse as much Linux code as possible.
>> - Glue code has been introduced to bridge the API calls.
>> - Called Linux functions from the Xen IOMMU function calls.
>> - Xen modifications are preceded by /*Xen: comment */
>> - xen/linux_compat: Add a Linux compat header
>>    For porting files directly from Linux it is useful to have a function mapping
>>    definitions from Linux to Xen. This file adds common API functions and
>>    other defines that are needed for porting arm SMMU drivers.
> 
> I understand Roger asked for it, but that was not a really wise choice 
> given the size of this patch. Anyway, let's keep it like that.
> 
>> 
>> Signed-off-by: Sameer Goel <sameer.goel@linaro.org>
>> ---
>>   xen/arch/arm/p2m.c                    |   1 +
>>   xen/drivers/Kconfig                   |   2 +
>>   xen/drivers/passthrough/arm/Kconfig   |   8 +
>>   xen/drivers/passthrough/arm/Makefile  |   1 +
>>   xen/drivers/passthrough/arm/smmu-v3.c | 892 ++++++++++++++++++++++++++++++++--
>>   xen/include/xen/linux_compat.h        |  84 ++++
> 
> You need to CC the REST maintainers for that.

And to be honest, I find adding such disgusting. We've imported
_lots_ of stuff from Linux, yet never needed things like gfp
definitions. I'm far from convinced that converting the new file
in at least some basic aspects to "Xen wording" would complicate
maintaining that file significantly. Headers included at the top
obviously can't use linux/ anyway, so it's never going to be a
verbatim copy.

Jan

Hi Jan,

On 01/03/18 14:21, Jan Beulich wrote:
>>>> On 01.03.18 at 15:07, <julien.grall@arm.com> wrote:
>> On 09/02/18 03:10, Sameer Goel wrote:
>>> This driver follows an approach similar to smmu driver. The intent here
>>> is to reuse as much Linux code as possible.
>>> - Glue code has been introduced to bridge the API calls.
>>> - Called Linux functions from the Xen IOMMU function calls.
>>> - Xen modifications are preceded by /*Xen: comment */
>>> - xen/linux_compat: Add a Linux compat header
>>>     For porting files directly from Linux it is useful to have a function mapping
>>>     definitions from Linux to Xen. This file adds common API functions and
>>>     other defines that are needed for porting arm SMMU drivers.
>>
>> I understand Roger asked for it, but that was not a really wise choice
>> given the size of this patch. Anyway, let's keep it like that.
>>
>>>
>>> Signed-off-by: Sameer Goel <sameer.goel@linaro.org>
>>> ---
>>>    xen/arch/arm/p2m.c                    |   1 +
>>>    xen/drivers/Kconfig                   |   2 +
>>>    xen/drivers/passthrough/arm/Kconfig   |   8 +
>>>    xen/drivers/passthrough/arm/Makefile  |   1 +
>>>    xen/drivers/passthrough/arm/smmu-v3.c | 892 ++++++++++++++++++++++++++++++++--
>>>    xen/include/xen/linux_compat.h        |  84 ++++
>>
>> You need to CC the REST maintainers for that.
> 
> And to be honest, I find adding such disgusting. We've imported
> _lots_ of stuff from Linux, yet never needed things like gfp
> definitions. I'm far from convinced that converting the new file
> in at least some basic aspects to "Xen wording" would complicate
> maintaining that file significantly. Headers included at the top
> obviously can't use linux/ anyway, so it's never going to be a
> verbatim copy.

What Sameer has been doing for SMMUv3 is following the word we did on 
the ARM SMMUv2 driver. The header is a suggestion for consolidating the 
macros over the files here.

Overall I think it makes sense to keep "Linux wording" as much as 
possible because those files are using Linux philosophy. But I would be 
open to suggestion here. So would you mind giving a list of things you 
consider "basic aspects to 'Xen wording'"?

Cheers,

>>> On 01.03.18 at 15:33, <julien.grall@arm.com> wrote:
> What Sameer has been doing for SMMUv3 is following the word we did on 
> the ARM SMMUv2 driver. The header is a suggestion for consolidating the 
> macros over the files here.

In which case - why isn't the patch introducing this compat header
removing the equivalent stuff from that other file. Instead it goes
and introduces the new smmu-v3.c right here. If it was more visible
what code is merely moved, it might be easier to agree to the
introduction.

Otoh this is still all very ARM IOMMU specific - perhaps the header
would then better be local to xen/drivers/passthrough/arm/ (and
you won't see me complain about all this random stuff anymore)?

> Overall I think it makes sense to keep "Linux wording" as much as 
> possible because those files are using Linux philosophy. But I would be 
> open to suggestion here. So would you mind giving a list of things you 
> consider "basic aspects to 'Xen wording'"?

- as already said, anything gfp-ish
- enum irqreturn, and in particular IRQ_WAKE_THREAD, the
  semantics of which surely aren't matched in Xen

Otoh I'm having less of a problem with e.g. dev_printk() and friends
or ktime_t et al, even if I would prefer them to not appear.

Hi Sameer,


On 02/09/2018 08:40 AM, Sameer Goel wrote:
> This driver follows an approach similar to smmu driver. The intent here
> is to reuse as much Linux code as possible.
> - Glue code has been introduced to bridge the API calls.
> - Called Linux functions from the Xen IOMMU function calls.
> - Xen modifications are preceded by /*Xen: comment */
> - xen/linux_compat: Add a Linux compat header
>    For porting files directly from Linux it is useful to have a function mapping
>    definitions from Linux to Xen. This file adds common API functions and
>    other defines that are needed for porting arm SMMU drivers.
>
> Signed-off-by: Sameer Goel <sameer.goel@linaro.org>
> ---
>   xen/arch/arm/p2m.c                    |   1 +
>   xen/drivers/Kconfig                   |   2 +
>   xen/drivers/passthrough/arm/Kconfig   |   8 +
>   xen/drivers/passthrough/arm/Makefile  |   1 +
>   xen/drivers/passthrough/arm/smmu-v3.c | 892 ++++++++++++++++++++++++++++++++--
>   xen/include/xen/linux_compat.h        |  84 ++++
>   6 files changed, 959 insertions(+), 29 deletions(-)
>   create mode 100644 xen/drivers/passthrough/arm/Kconfig
>   create mode 100644 xen/include/xen/linux_compat.h
>
> diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
> index 65e8b9c6ea..fef7605fd6 100644
> --- a/xen/arch/arm/p2m.c
> +++ b/xen/arch/arm/p2m.c
> @@ -1460,6 +1460,7 @@ err:
>   static void __init setup_virt_paging_one(void *data)
>   {
>       unsigned long val = (unsigned long)data;
> +    /* SMMUv3 S2 cfg vtcr reuses the following value */
>       WRITE_SYSREG32(val, VTCR_EL2);
>       isb();
>   }
> diff --git a/xen/drivers/Kconfig b/xen/drivers/Kconfig
> index bc3a54f0ea..612655386d 100644
> --- a/xen/drivers/Kconfig
> +++ b/xen/drivers/Kconfig
> @@ -12,4 +12,6 @@ source "drivers/pci/Kconfig"
>   
>   source "drivers/video/Kconfig"
>   
> +source "drivers/passthrough/arm/Kconfig"
> +
>   endmenu
> diff --git a/xen/drivers/passthrough/arm/Kconfig b/xen/drivers/passthrough/arm/Kconfig
> new file mode 100644
> index 0000000000..cda899f608
> --- /dev/null
> +++ b/xen/drivers/passthrough/arm/Kconfig
> @@ -0,0 +1,8 @@
> +
> +config ARM_SMMU_v3
> +	bool "ARM SMMUv3 Support"
> +	depends on ARM_64
> +	help
> +	 Support for implementations of the ARM System MMU architecture
> +	 version 3.
> +
> diff --git a/xen/drivers/passthrough/arm/Makefile b/xen/drivers/passthrough/arm/Makefile
> index f4cd26e15d..e14732b55c 100644
> --- a/xen/drivers/passthrough/arm/Makefile
> +++ b/xen/drivers/passthrough/arm/Makefile
> @@ -1,2 +1,3 @@
>   obj-y += iommu.o
>   obj-y += smmu.o
> +obj-$(CONFIG_ARM_SMMU_v3) += smmu-v3.o
> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c
> index e67ba6c40f..f43485fe6e 100644
> --- a/xen/drivers/passthrough/arm/smmu-v3.c
> +++ b/xen/drivers/passthrough/arm/smmu-v3.c
> @@ -18,28 +18,414 @@
>    * Author: Will Deacon <will.deacon@arm.com>
>    *
>    * This driver is powered by bad coffee and bombay mix.
> + *
> + *
> + * Based on Linux drivers/iommu/arm-smmu-v3.c
> + * => commit 7aa8619a66aea52b145e04cbab4f8d6a4e5f3f3b
> + *
> + * Xen modifications:
> + * Sameer Goel <sameer.goel@linaro.org>
> + * Copyright (C) 2017, The Linux Foundation, All rights reserved.
> + *
> + */
> +
> +#include <xen/acpi.h>
> +#include <xen/config.h>
> +#include <xen/delay.h>
> +#include <xen/errno.h>
> +#include <xen/err.h>
> +#include <xen/irq.h>
> +#include <xen/lib.h>
> +#include <xen/linux_compat.h>
> +#include <xen/list.h>
> +#include <xen/mm.h>
> +#include <xen/rbtree.h>
> +#include <xen/sched.h>
> +#include <xen/sizes.h>
> +#include <xen/vmap.h>
> +#include <acpi/acpi_iort.h>
> +#include <asm/atomic.h>
> +#include <asm/device.h>
> +#include <asm/io.h>
> +#include <asm/platform.h>
> +
> +/* Alias to Xen device tree helpers */
> +#define device_node dt_device_node
> +#define of_phandle_args dt_phandle_args
> +#define of_device_id dt_device_match
> +#define of_match_node dt_match_node
> +#define of_property_read_u32(np, pname, out) (!dt_property_read_u32(np, pname, out))
> +#define of_property_read_bool dt_property_read_bool
> +#define of_parse_phandle_with_args dt_parse_phandle_with_args
> +
> +/* Xen: Helpers to get device MMIO and IRQs */
> +struct resource {
> +	u64 addr;
> +	u64 size;
> +	unsigned int type;
> +};
> +
> +#define resource_size(res) ((res)->size)
> +
> +#define platform_device device
> +
> +#define IORESOURCE_MEM 0
> +#define IORESOURCE_IRQ 1
> +
> +static struct resource *platform_get_resource(struct platform_device *pdev,
> +					      unsigned int type,
> +					      unsigned int num)
> +{
> +	/*
> +	 * The resource is only used between 2 calls of platform_get_resource.
> +	 * It's quite ugly but it's avoid to add too much code in the part
> +	 * imported from Linux
> +	 */
> +	static struct resource res;
> +	struct acpi_iort_node *iort_node;
> +	struct acpi_iort_smmu_v3 *node_smmu_data;
> +	int ret = 0;
> +
> +	res.type = type;
> +
> +	switch (type) {
> +	case IORESOURCE_MEM:
> +		if (pdev->type == DEV_ACPI) {
> +			ret = 1;
> +			iort_node = pdev->acpi_node;
> +			node_smmu_data =
> +				(struct acpi_iort_smmu_v3 *)iort_node->node_data;
> +
> +			if (node_smmu_data != NULL) {
> +				res.addr = node_smmu_data->base_address;
> +				res.size = SZ_128K;
> +				ret = 0;
> +			}
> +		} else {
> +			ret = dt_device_get_address(dev_to_dt(pdev), num,
> +						    &res.addr, &res.size);
> +		}
> +
> +		return ((ret) ? NULL : &res);
> +
> +	case IORESOURCE_IRQ:
> +		/* ACPI case not implemented as there is no use case for it */
> +		ret = platform_get_irq(dev_to_dt(pdev), num);
> +
> +		if (ret < 0)
> +			return NULL;
> +
> +		res.addr = ret;
> +		res.size = 1;
> +
> +		return &res;
> +
> +	default:
> +		return NULL;
> +	}
> +}
> +
> +static int platform_get_irq_byname(struct platform_device *pdev, const char *name)
> +{
> +	const struct dt_property *dtprop;
> +	struct acpi_iort_node *iort_node;
> +	struct acpi_iort_smmu_v3 *node_smmu_data;
> +	int ret = 0;
> +
> +	if (pdev->type == DEV_ACPI) {
> +		iort_node = pdev->acpi_node;
> +		node_smmu_data = (struct acpi_iort_smmu_v3 *)iort_node->node_data;
> +
> +		if (node_smmu_data != NULL) {
> +			if (!strcmp(name, "eventq"))
> +				ret = node_smmu_data->event_gsiv;
> +			else if (!strcmp(name, "priq"))
> +				ret = node_smmu_data->pri_gsiv;
> +			else if (!strcmp(name, "cmdq-sync"))
> +				ret = node_smmu_data->sync_gsiv;
> +			else if (!strcmp(name, "gerror"))
> +				ret = node_smmu_data->gerr_gsiv;
> +			else
> +				ret = -EINVAL;
> +		}
> +	} else {
> +		dtprop = dt_find_property(dev_to_dt(pdev), "interrupt-names", NULL);
> +		if (!dtprop)
> +			return -EINVAL;
> +
> +		if (!dtprop->value)
> +			return -ENODATA;
> +	}
> +
> +	return ret;
> +}
> +
> +/*
> + * Xen: Helpers for DMA allocation. Just the function name is reused for
> + * porting code these allocation are not managed allocations
>    */
>   
> -#include <linux/acpi.h>
> -#include <linux/acpi_iort.h>
> -#include <linux/delay.h>
> -#include <linux/dma-iommu.h>
> -#include <linux/err.h>
> -#include <linux/interrupt.h>
> -#include <linux/iommu.h>
> -#include <linux/iopoll.h>
> -#include <linux/module.h>
> -#include <linux/msi.h>
> -#include <linux/of.h>
> -#include <linux/of_address.h>
> -#include <linux/of_iommu.h>
> -#include <linux/of_platform.h>
> -#include <linux/pci.h>
> -#include <linux/platform_device.h>
> -
> -#include <linux/amba/bus.h>
> -
> -#include "io-pgtable.h"
> +static void *dmam_alloc_coherent(struct device *dev, size_t size,
> +			   dma_addr_t *dma_handle, gfp_t gfp)
> +{
> +	void *vaddr;
> +	unsigned long alignment = size;
> +
> +	/*
> +	 * _xzalloc requires that the (align & (align -1)) = 0. Most of the
> +	 * allocations in SMMU code should send the right value for size. In
> +	 * case this is not true print a warning and align to the size of a
> +	 * (void *)
> +	 */
> +	if (size & (size - 1)) {
> +		dev_warn(dev, "Fixing alignment for the DMA buffer\n");
> +		alignment = sizeof(void *);
> +	}
> +
> +	vaddr = _xzalloc(size, alignment);
> +	if (!vaddr) {
> +		dev_err(dev, "DMA allocation failed\n");
> +		return NULL;
> +	}
> +
> +	*dma_handle = virt_to_maddr(vaddr);
> +
> +	return vaddr;
> +}
> +
> +
> +static void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
> +			dma_addr_t dma_handle)
> +{
> +	xfree(vaddr);
> +}
> +
> +/* Xen: Stub out DMA domain related functions */
> +#define iommu_get_dma_cookie(dom) 0
> +#define iommu_put_dma_cookie(dom)
> +
> +/* Xen: Stub out module param related function */
> +#define module_param_named(a, b, c, d)
> +#define MODULE_PARM_DESC(a, b)
> +
> +#define dma_set_mask_and_coherent(d, b) 0
> +
> +#define of_dma_is_coherent(n) 0
> +
> +#define MODULE_DEVICE_TABLE(type, name)
> +
> +static void __iomem *devm_ioremap_resource(struct device *dev,
> +					   struct resource *res)
> +{
> +	void __iomem *ptr;
> +
> +	if (!res || res->type != IORESOURCE_MEM) {
> +		dev_err(dev, "Invalid resource\n");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	ptr = ioremap_nocache(res->addr, res->size);
> +	if (!ptr) {
> +		dev_err(dev,
> +			"ioremap failed (addr 0x%"PRIx64" size 0x%"PRIx64")\n",
> +			res->addr, res->size);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	return ptr;
> +}
> +
> +/* Xen: Compatibility define for iommu_domain_geometry.*/
> +struct iommu_domain_geometry {
> +	dma_addr_t aperture_start; /* First address that can be mapped    */
> +	dma_addr_t aperture_end;   /* Last address that can be mapped     */
> +	bool force_aperture;       /* DMA only allowed in mappable range? */
> +};
> +
> +
> +/* Xen: Type definitions for iommu_domain */
> +#define IOMMU_DOMAIN_UNMANAGED 0
> +#define IOMMU_DOMAIN_DMA 1
> +#define IOMMU_DOMAIN_IDENTITY 2
> +
> +/* Xen: Dummy iommu_domain */
> +struct iommu_domain {
> +	/* Runtime SMMU configuration for this iommu_domain */
> +	struct arm_smmu_domain		*priv;
> +	unsigned int type;
> +
> +	/* Dummy compatibility defines */
> +	unsigned long pgsize_bitmap;
> +	struct iommu_domain_geometry geometry;
> +
> +	atomic_t ref;
> +	/*
> +	 * Used to link iommu_domain contexts for a same domain.
> +	 * There is at least one per-SMMU to used by the domain.
> +	 */
> +	struct list_head		list;
> +};
> +
> +/* Xen: Describes information required for a Xen domain */
> +struct arm_smmu_xen_domain {
> +	spinlock_t			lock;
> +	/* List of iommu domains associated to this domain */
> +	struct list_head		contexts;
> +};
> +
> +/*
> + * Xen: Information about each device stored in dev->archdata.iommu
> + *
> + * The dev->archdata.iommu stores the iommu_domain (runtime configuration of
> + * the SMMU).
> + */
> +struct arm_smmu_xen_device {
> +	struct iommu_domain *domain;
> +};
> +
> +/*
> + * Xen: io_pgtable compatibility defines.
> + * Most of these are to port in the S1 translation code as is.
> + */
> +struct io_pgtable_ops {
> +};
> +
> +struct iommu_gather_ops {
> +	void (*tlb_flush_all)(void *cookie);
> +	void (*tlb_add_flush)(unsigned long iova, size_t size, size_t granule,
> +			      bool leaf, void *cookie);
> +	void (*tlb_sync)(void *cookie);
> +};
> +
> +struct io_pgtable_cfg {
> +	/*
> +	 * IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE bits in
> +	 *	stage 1 PTEs, for hardware which insists on validating them
> +	 *	even in	non-secure state where they should normally be ignored.
> +	 *
> +	 * IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE and
> +	 *	IOMMU_NOEXEC flags and map everything with full access, for
> +	 *	hardware which does not implement the permissions of a given
> +	 *	format, and/or requires some format-specific default value.
> +	 *
> +	 * IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching invalid
> +	 *	(unmapped) entries but the hardware might do so anyway, perform
> +	 *	TLB maintenance when mapping as well as when unmapping.
> +	 *
> +	 * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> +	 *	PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> +	 *	when the SoC is in "4GB mode" and they can only access the high
> +	 *	remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> +	 *
> +	 * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
> +	 *	be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
> +	 *	software-emulated IOMMU), such that pagetable updates need not
> +	 *	be treated as explicit DMA data.
> +	 */
> +	#define IO_PGTABLE_QUIRK_ARM_NS		BIT(0)
> +	#define IO_PGTABLE_QUIRK_NO_PERMS	BIT(1)
> +	#define IO_PGTABLE_QUIRK_TLBI_ON_MAP	BIT(2)
> +	#define IO_PGTABLE_QUIRK_ARM_MTK_4GB	BIT(3)
> +	#define IO_PGTABLE_QUIRK_NO_DMA		BIT(4)
> +	unsigned long			quirks;
> +	unsigned long			pgsize_bitmap;
> +	unsigned int			ias;
> +	unsigned int			oas;
> +	const struct iommu_gather_ops	*tlb;
> +	struct device			*iommu_dev;
> +
> +	/* Low-level data specific to the table format */
> +	union {
> +		struct {
> +			u64	ttbr[2];
> +			u64	tcr;
> +			u64	mair[2];
> +		} arm_lpae_s1_cfg;
> +
> +		struct {
> +			u64	vttbr;
> +			u64	vtcr;
> +		} arm_lpae_s2_cfg;
> +
> +		struct {
> +			u32	ttbr[2];
> +			u32	tcr;
> +			u32	nmrr;
> +			u32	prrr;
> +		} arm_v7s_cfg;
> +	};
> +};
> +
> +enum io_pgtable_fmt {
> +	ARM_32_LPAE_S1,
> +	ARM_32_LPAE_S2,
> +	ARM_64_LPAE_S1,
> +	ARM_64_LPAE_S2,
> +	ARM_V7S,
> +	IO_PGTABLE_NUM_FMTS,
> +};
> +
> +/*
> + * Xen: The pgtable_ops are used by the S1 translations, so return the dummy
> + * address.
> + */
> +#define alloc_io_pgtable_ops(f, c, o) ((struct io_pgtable_ops *)0x0)
Is this correct? it will make the caller null check fail
> +#define free_io_pgtable_ops(o)
> +
> +/* Xen: Define wrapper for requesting IRQs */
> +#define IRQF_ONESHOT 0
> +
> +typedef void (*irq_handler_t)(int, void *, struct cpu_user_regs *);
> +
> +static inline int devm_request_irq(struct device *dev, unsigned int irq,
> +				   irq_handler_t handler, unsigned long irqflags,
> +				   const char *devname, void *dev_id)
> +{
> +	/*
> +	 * SMMUv3 implementation can support wired interrupt outputs that are
> +	 * edge-triggered. Set the irq type as per the spec.
> +	 */
> +	irq_set_type(irq, IRQ_TYPE_EDGE_BOTH);
> +	return request_irq(irq, irqflags, handler, devname, dev_id);
> +}
> +
> +/*
> + * Xen does not have a concept of threaded irq, but eventually we can use
> + * tasklets to optimize the following function.
> + */
> +int devm_request_threaded_irq(struct device *dev, unsigned int irq, irq_handler_t handler,
> +			      irq_handler_t thread_fn, unsigned long irqflags,
> +			      const char *devname, void *dev_id)
> +{
> +	return devm_request_irq(dev, irq, thread_fn, irqflags, devname, dev_id);
> +}
> +
> +/* Xen: The mutex is used only during initialization so the typecast is safe */
> +#define mutex spinlock
> +#define mutex_init spin_lock_init
> +#define mutex_lock spin_lock
> +#define mutex_unlock spin_unlock
> +
> +#define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \
> +({ \
> +	s_time_t deadline = NOW() + MICROSECS(timeout_us); \
> +	for (;;) { \
> +		(val) = op(addr); \
> +		if (cond) \
> +			break; \
> +		if (NOW() > deadline) { \
> +			(val) = op(addr); \
> +			break; \
> +		} \
> +	udelay(sleep_us); \
> +	} \
> +	(cond) ? 0 : -ETIMEDOUT; \
> +})
> +
> +#define readl_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \
> +	readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, timeout_us)
> +
> +#define VA_BITS 0 /* Only needed for S1 translations */
>   
>   /* MMIO registers */
>   #define ARM_SMMU_IDR0			0x0
> @@ -433,6 +819,7 @@ enum pri_resp {
>   	PRI_RESP_SUCC,
>   };
>   
> +#if 0 /* Xen: No MSI support in this iteration */
>   enum arm_smmu_msi_index {
>   	EVTQ_MSI_INDEX,
>   	GERROR_MSI_INDEX,
> @@ -457,6 +844,7 @@ static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
>   		ARM_SMMU_PRIQ_IRQ_CFG2,
>   	},
>   };
> +#endif
>   
>   struct arm_smmu_cmdq_ent {
>   	/* Common fields */
> @@ -561,6 +949,8 @@ struct arm_smmu_s2_cfg {
>   	u16				vmid;
>   	u64				vttbr;
>   	u64				vtcr;
> +	/* Xen: Domain associated to this configuration */
> +	struct domain			*domain;
>   };
>   
>   struct arm_smmu_strtab_ent {
> @@ -635,9 +1025,21 @@ struct arm_smmu_device {
>   	struct arm_smmu_strtab_cfg	strtab_cfg;
>   
>   	/* IOMMU core code handle */
> +#if 0 /*Xen: Generic iommu_device ref not needed here */
>   	struct iommu_device		iommu;
> +#endif
> +	/* Xen: Need to keep a list of SMMU devices */
> +	struct list_head                devices;
>   };
>   
> +/* Xen: Keep a list of devices associated with this driver */
> +static DEFINE_SPINLOCK(arm_smmu_devices_lock);
> +static LIST_HEAD(arm_smmu_devices);
> +/* Xen: Helper for finding a device using fwnode */
> +static
> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode);
> +
> +
>   /* SMMU private data for each master */
>   struct arm_smmu_master_data {
>   	struct arm_smmu_device		*smmu;
> @@ -1232,7 +1634,7 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)
>   
>   	dev_info(smmu->dev, "unexpected PRI request received:\n");
>   	dev_info(smmu->dev,
> -		 "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n",
> +		 "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova %#" PRIx64 "\n",
>   		 sid, ssid, grpid, last ? "L" : "",
>   		 evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",
>   		 evt[0] & PRIQ_0_PERM_READ ? "R" : "",
> @@ -1346,6 +1748,8 @@ static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev)
>   {
>   	arm_smmu_gerror_handler(irq, dev);
>   	arm_smmu_cmdq_sync_handler(irq, dev);
> +	/*Xen: No threaded irq. So call the required function from here */
> +	arm_smmu_combined_irq_thread(irq, dev);
>   	return IRQ_WAKE_THREAD;
>   }
>   
> @@ -1358,6 +1762,46 @@ static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
>   	arm_smmu_cmdq_issue_cmd(smmu, &cmd);
>   }
>   
> +/*
> + * Xen: Define the IRQ handlers for xen. The linux functions would be
> + * modified to use the functions defined in the following code.
> + */
> +static void arm_smmu_evtq_thread_xen(int irq, void *dev,
> +				       struct cpu_user_regs *regs)
> +{
> +	arm_smmu_evtq_thread(irq, dev);
> +}
> +
> +static void arm_smmu_priq_thread_xen(int irq, void *dev,
> +				       struct cpu_user_regs *regs)
> +{
> +	arm_smmu_priq_thread(irq, dev);
> +}
> +
> +static void arm_smmu_cmdq_sync_handler_xen(int irq, void *dev,
> +				       struct cpu_user_regs *regs)
> +{
> +	arm_smmu_cmdq_sync_handler(irq, dev);
> +}
> +
> +static void arm_smmu_gerror_handler_xen(int irq, void *dev,
> +				       struct cpu_user_regs *regs)
> +{
> +	arm_smmu_gerror_handler(irq, dev);
> +}
> +
> +static void arm_smmu_combined_irq_handler_xen(int irq, void *dev,
> +				       struct cpu_user_regs *regs)
> +{
> +	arm_smmu_combined_irq_handler(irq, dev);
> +}
> +
> +#define arm_smmu_evtq_thread arm_smmu_evtq_thread_xen
> +#define arm_smmu_priq_thread arm_smmu_priq_thread_xen
> +#define arm_smmu_cmdq_sync_handler arm_smmu_cmdq_sync_handler_xen
> +#define arm_smmu_gerror_handler arm_smmu_gerror_handler_xen
> +#define arm_smmu_combined_irq_handler arm_smmu_combined_irq_handler_xen
> +
>   static void arm_smmu_tlb_sync(void *cookie)
>   {
>   	struct arm_smmu_domain *smmu_domain = cookie;
> @@ -1415,6 +1859,7 @@ static const struct iommu_gather_ops arm_smmu_gather_ops = {
>   	.tlb_sync	= arm_smmu_tlb_sync,
>   };
>   
> +#if 0 /*Xen: Unused functionality */
>   /* IOMMU API */
>   static bool arm_smmu_capable(enum iommu_cap cap)
>   {
> @@ -1427,6 +1872,7 @@ static bool arm_smmu_capable(enum iommu_cap cap)
>   		return false;
>   	}
>   }
> +#endif
>   
>   static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
>   {
> @@ -1546,9 +1992,16 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain,
>   	if (vmid < 0)
>   		return vmid;
>   
> -	cfg->vmid	= (u16)vmid;
> -	cfg->vttbr	= pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
> -	cfg->vtcr	= pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
> +	/*
> +	 * Xen: Get the ttbr and vtcr values
> +	 * vttbr: This is a shared value with the domain page table
> +	 * vtcr: The TCR settings are the same as CPU since the page
> +	 * tables are shared
> +	 */
> +
> +	cfg->vmid	= vmid;
> +	cfg->vttbr	= page_to_maddr(cfg->domain->arch.p2m.root);
> +	cfg->vtcr	= READ_SYSREG32(VTCR_EL2) & STRTAB_STE_2_VTCR_MASK;
>   	return 0;
>   }
>   
> @@ -1604,6 +2057,7 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain)
>   	if (smmu->features & ARM_SMMU_FEAT_COHERENCY)
>   		pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_NO_DMA;
>   
> +	/* Xen: pgtbl_ops gets an invalid address */
>   	pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
>   	if (!pgtbl_ops)
>   		return -ENOMEM;
Will this not fail ?
> @@ -1721,6 +2175,7 @@ out_unlock:
>   	return ret;
>   }
>   
> +#if 0 /* Xen: Unused functionality */
>   static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
>   			phys_addr_t paddr, size_t size, int prot)
>   {
> @@ -1772,6 +2227,7 @@ struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
>   	put_device(dev);
>   	return dev ? dev_get_drvdata(dev) : NULL;
>   }
> +#endif
>   
>   static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
>   {
> @@ -1783,7 +2239,14 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
>   	return sid < limit;
>   }
>   
> +/* Xen: Unused */
> +#if 0
>   static struct iommu_ops arm_smmu_ops;
> +#endif
> +
> +/* Xen: Redefine arm_smmu_ops to what fwspec should evaluate */
> +static const struct iommu_ops arm_smmu_iommu_ops;
> +#define arm_smmu_ops arm_smmu_iommu_ops
>   
>   static int arm_smmu_add_device(struct device *dev)
>   {
> @@ -1791,8 +2254,11 @@ static int arm_smmu_add_device(struct device *dev)
>   	struct arm_smmu_device *smmu;
>   	struct arm_smmu_master_data *master;
>   	struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> +#if 0 /*Xen: iommu_group is not needed */
>   	struct iommu_group *group;
> +#endif
>   
> +	/* Xen: fwspec->ops are not needed */
>   	if (!fwspec || fwspec->ops != &arm_smmu_ops)
>   		return -ENODEV;
>   	/*
> @@ -1830,6 +2296,11 @@ static int arm_smmu_add_device(struct device *dev)
>   		}
>   	}
>   
> +/*
> + * Xen: Do not need an iommu group as the stream data is carried by the SMMU
> + * master device object
> + */
> +#if 0
>   	group = iommu_group_get_for_dev(dev);
>   	if (!IS_ERR(group)) {
>   		iommu_group_put(group);
> @@ -1837,8 +2308,16 @@ static int arm_smmu_add_device(struct device *dev)
>   	}
>   
>   	return PTR_ERR_OR_ZERO(group);
> +#endif
> +	return 0;
>   }
>   
> +/*
> + * Xen: We can potentially support this function and destroy a device. This
> + * will be relevant for PCI hotplug. So, will be implemented as needed after
> + * passthrough support is available.
> + */
> +#if 0
>   static void arm_smmu_remove_device(struct device *dev)
>   {
>   	struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> @@ -1974,6 +2453,7 @@ static struct iommu_ops arm_smmu_ops = {
>   	.put_resv_regions	= arm_smmu_put_resv_regions,
>   	.pgsize_bitmap		= -1UL, /* Restricted during device attach */
>   };
> +#endif
>   
>   /* Probing and initialisation functions */
>   static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
> @@ -2182,6 +2662,7 @@ static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr)
>   					  1, ARM_SMMU_POLL_TIMEOUT_US);
>   }
>   
> +#if 0 /* Xen: There is no MSI support as yet */
>   static void arm_smmu_free_msis(void *data)
>   {
>   	struct device *dev = data;
> @@ -2247,12 +2728,15 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
>   	/* Add callback to free MSIs on teardown */
>   	devm_add_action(dev, arm_smmu_free_msis, dev);
>   }
> +#endif
>   
>   static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
>   {
>   	int irq, ret;
>   
> +#if 0 /*Xen: Cannot setup msis for now */
>   	arm_smmu_setup_msis(smmu);
> +#endif
>   
>   	/* Request interrupt lines */
>   	irq = smmu->evtq.q.irq;
> @@ -2316,9 +2800,13 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
>   		 * Cavium ThunderX2 implementation doesn't not support unique
>   		 * irq lines. Use single irq line for all the SMMUv3 interrupts.
>   		 */
> -		ret = devm_request_threaded_irq(smmu->dev, irq,
> +		/*
> +		 * Xen: Does not support threaded irqs, so serialise the setup.
> +		 * This is the same for pris and event interrupt lines on other
> +		 * systems
> +		 */
> +		ret = devm_request_irq(smmu->dev, irq,
>   					arm_smmu_combined_irq_handler,
> -					arm_smmu_combined_irq_thread,
>   					IRQF_ONESHOT,
>   					"arm-smmu-v3-combined-irq", smmu);
>   		if (ret < 0)
> @@ -2542,8 +3030,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
>   		smmu->features |= ARM_SMMU_FEAT_STALLS;
>   	}
>   
> +/*
> + * Xen: Block stage 1 translations. By doing this here we do not need to set the
> + * domain->stage explicitly.
> + */
> +#if 0
>   	if (reg & IDR0_S1P)
>   		smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
> +#endif
>   
>   	if (reg & IDR0_S2P)
>   		smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
> @@ -2616,10 +3110,12 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
>   	if (reg & IDR5_GRAN4K)
>   		smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
>   
> +#if 0 /* Xen: SMMU ops do not have a pgsize_bitmap member for Xen */
>   	if (arm_smmu_ops.pgsize_bitmap == -1UL)
>   		arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
>   	else
>   		arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
> +#endif
>   
>   	/* Output address size */
>   	switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) {
> @@ -2680,7 +3176,8 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
>   	struct device *dev = smmu->dev;
>   	struct acpi_iort_node *node;
>   
> -	node = *(struct acpi_iort_node **)dev_get_platdata(dev);
> +	/* Xen: Modification to get iort_node */
> +	node = (struct acpi_iort_node *)dev->acpi_node;
>   
>   	/* Retrieve SMMUv3 specific data */
>   	iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
> @@ -2703,7 +3200,7 @@ static inline int arm_smmu_device_acpi_probe(struct platform_device *pdev,
>   static int arm_smmu_device_dt_probe(struct platform_device *pdev,
>   				    struct arm_smmu_device *smmu)
>   {
> -	struct device *dev = &pdev->dev;
> +	struct device *dev = pdev;
>   	u32 cells;
>   	int ret = -EINVAL;
>   
> @@ -2716,6 +3213,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev,
>   
>   	parse_driver_options(smmu);
>   
> +	/* Xen: of_dma_is_coherent is a stub till dt support is introduced */
>   	if (of_dma_is_coherent(dev->of_node))
>   		smmu->features |= ARM_SMMU_FEAT_COHERENCY;
>   
> @@ -2734,9 +3232,11 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>   {
>   	int irq, ret;
>   	struct resource *res;
> +#if 0 /*Xen: Do not need to setup sysfs */
>   	resource_size_t ioaddr;
> +#endif
>   	struct arm_smmu_device *smmu;
> -	struct device *dev = &pdev->dev;
> +	struct device *dev = pdev;/* Xen: dev is ignored */
>   	bool bypass;
>   
>   	smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
> @@ -2763,7 +3263,9 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>   		dev_err(dev, "MMIO region too small (%pr)\n", res);
>   		return -EINVAL;
>   	}
> +#if 0 /*Xen: Do not need to setup sysfs */
>   	ioaddr = res->start;
> +#endif
>   
>   	smmu->base = devm_ioremap_resource(dev, res);
>   	if (IS_ERR(smmu->base))
> @@ -2802,13 +3304,18 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>   		return ret;
>   
>   	/* Record our private device structure */
> +	/* Xen: SMMU is not treated a a platform device*/
> +#if 0
>   	platform_set_drvdata(pdev, smmu);
> +#endif
>   
>   	/* Reset the device */
>   	ret = arm_smmu_device_reset(smmu, bypass);
>   	if (ret)
>   		return ret;
>   
> +/* Xen: Not creating an IOMMU device list for Xen */
> +#if 0
>   	/* And we're up. Go go go! */
>   	ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL,
>   				     "smmu3.%pa", &ioaddr);
> @@ -2844,9 +3351,20 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>   		if (ret)
>   			return ret;
>   	}
> +#endif
> +	/*
> +	 * Xen: Keep a list of all probed devices. This will be used to query
> +	 * the smmu devices based on the fwnode.
> +	 */
> +	INIT_LIST_HEAD(&smmu->devices);
> +	spin_lock(&arm_smmu_devices_lock);
> +	list_add(&smmu->devices, &arm_smmu_devices);
> +	spin_unlock(&arm_smmu_devices_lock);
>   	return 0;
>   }
>   
> +/* Xen: Unused function */
> +#if 0
>   static int arm_smmu_device_remove(struct platform_device *pdev)
>   {
>   	struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
> @@ -2860,6 +3378,8 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev)
>   {
>   	arm_smmu_device_remove(pdev);
>   }
> +#endif
> +
>   
>   static const struct of_device_id arm_smmu_of_match[] = {
>   	{ .compatible = "arm,smmu-v3", },
> @@ -2867,6 +3387,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
>   };
>   MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
>   
> +#if 0
>   static struct platform_driver arm_smmu_driver = {
>   	.driver	= {
>   		.name		= "arm-smmu-v3",
> @@ -2883,3 +3404,316 @@ IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3", NULL);
>   MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
>   MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
>   MODULE_LICENSE("GPL v2");
> +#endif
> +
> +/***** Start of Xen specific code *****/
> +
> +static int __must_check arm_smmu_iotlb_flush_all(struct domain *d)
> +{
> +	struct arm_smmu_xen_domain *smmu_domain = dom_iommu(d)->arch.priv;
> +	struct iommu_domain *cfg;
> +
> +	spin_lock(&smmu_domain->lock);
> +	list_for_each_entry(cfg, &smmu_domain->contexts, list) {
> +		/*
> +		 * Only invalidate the context when SMMU is present.
> +		 * This is because the context initialization is delayed
> +		 * until a master has been added.
> +		 */
> +		if (unlikely(!ACCESS_ONCE(cfg->priv->smmu)))
> +			continue;
> +		arm_smmu_tlb_inv_context(cfg->priv);
> +	}
> +	spin_unlock(&smmu_domain->lock);
> +	return 0;
> +}
> +
> +static int __must_check arm_smmu_iotlb_flush(struct domain *d,
> +					     unsigned long gfn,
> +					     unsigned int page_count)
> +{
> +	return arm_smmu_iotlb_flush_all(d);
> +}
> +
> +static struct iommu_domain *arm_smmu_get_domain(struct domain *d,
> +						struct device *dev)
> +{
> +	struct iommu_domain *domain;
> +	struct arm_smmu_xen_domain *xen_domain;
> +	struct arm_smmu_device *smmu;
> +	struct arm_smmu_domain *smmu_domain;
> +
> +	xen_domain = dom_iommu(d)->arch.priv;
> +
> +	smmu = arm_smmu_get_by_fwnode(dev->iommu_fwspec->iommu_fwnode);
> +	if (!smmu)
> +		return NULL;
> +
> +	/*
> +	 * Loop through the &xen_domain->contexts to locate a context
> +	 * assigned to this SMMU
> +	 */
> +	list_for_each_entry(domain, &xen_domain->contexts, list) {
> +		smmu_domain = to_smmu_domain(domain);
> +		if (smmu_domain->smmu == smmu)
> +			return domain;
> +	}
> +
> +	return NULL;
> +}
> +
> +static void arm_smmu_destroy_iommu_domain(struct iommu_domain *domain)
> +{
> +	list_del(&domain->list);
> +	arm_smmu_domain_free(domain);
> +}
> +
> +static int arm_smmu_assign_dev(struct domain *d, u8 devfn,
> +			       struct device *dev, u32 flag)
> +{
> +	int ret = 0;
> +	struct iommu_domain *domain;
> +	struct arm_smmu_xen_domain *xen_domain;
> +	struct arm_smmu_domain *arm_smmu;
> +
> +	xen_domain = dom_iommu(d)->arch.priv;
> +
> +	if (!dev->archdata.iommu) {
> +		dev->archdata.iommu = xzalloc(struct arm_smmu_xen_device);
> +		if (!dev->archdata.iommu)
> +			return -ENOMEM;
> +	}
> +
> +	ret = arm_smmu_add_device(dev);
> +	if (ret)
> +		return ret;
> +
> +	spin_lock(&xen_domain->lock);
> +
> +	/*
> +	 * Check to see if an iommu_domain already exists for this xen domain
> +	 * under the same SMMU
> +	 */
> +	domain = arm_smmu_get_domain(d, dev);
> +	if (!domain) {
> +
> +		domain = arm_smmu_domain_alloc(IOMMU_DOMAIN_DMA);
> +		if (!domain) {
> +			ret = -ENOMEM;
> +			goto out;
> +		}
> +
> +		arm_smmu = to_smmu_domain(domain);
> +		arm_smmu->s2_cfg.domain = d;
> +
> +		/* Chain the new context to the domain */
> +		list_add(&domain->list, &xen_domain->contexts);
> +
> +	}
> +
> +	ret = arm_smmu_attach_dev(domain, dev);
> +	if (ret) {
> +		if (domain->ref.counter == 0)
> +			arm_smmu_destroy_iommu_domain(domain);
> +	} else {
> +		atomic_inc(&domain->ref);
> +	}
> +
> +out:
> +	spin_unlock(&xen_domain->lock);
> +	return ret;
> +}
> +
> +static int arm_smmu_deassign_dev(struct domain *d, struct device *dev)
> +{
> +	struct iommu_domain *domain = arm_smmu_get_domain(d, dev);
> +	struct arm_smmu_xen_domain *xen_domain;
> +	struct arm_smmu_domain *arm_smmu = to_smmu_domain(domain);
> +
> +	xen_domain = dom_iommu(d)->arch.priv;
> +
> +	if (!arm_smmu || arm_smmu->s2_cfg.domain != d) {
> +		dev_err(dev, " not attached to domain %d\n", d->domain_id);
> +		return -ESRCH;
> +	}
> +
> +	spin_lock(&xen_domain->lock);
> +
> +	arm_smmu_detach_dev(dev);
> +	atomic_dec(&domain->ref);
> +
> +	if (domain->ref.counter == 0)
> +		arm_smmu_destroy_iommu_domain(domain);
> +
> +	spin_unlock(&xen_domain->lock);
> +
> +	return 0;
> +}
> +
> +static int arm_smmu_reassign_dev(struct domain *s, struct domain *t,
> +				 u8 devfn,  struct device *dev)
> +{
> +	int ret = 0;
> +
> +	/* Don't allow remapping on other domain than hwdom */
> +	if (t && t != hardware_domain)
> +		return -EPERM;
> +
> +	if (t == s)
> +		return 0;
> +
> +	ret = arm_smmu_deassign_dev(s, dev);
> +	if (ret)
> +		return ret;
> +
> +	if (t) {
> +		/* No flags are defined for ARM. */
> +		ret = arm_smmu_assign_dev(t, devfn, dev, 0);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int arm_smmu_iommu_domain_init(struct domain *d)
> +{
> +	struct arm_smmu_xen_domain *xen_domain;
> +
> +	xen_domain = xzalloc(struct arm_smmu_xen_domain);
> +	if (!xen_domain)
> +		return -ENOMEM;
> +
> +	spin_lock_init(&xen_domain->lock);
> +	INIT_LIST_HEAD(&xen_domain->contexts);
> +
> +	dom_iommu(d)->arch.priv = xen_domain;
> +
> +	return 0;
> +}
> +
> +static void __hwdom_init arm_smmu_iommu_hwdom_init(struct domain *d)
> +{
> +}
> +
> +static void arm_smmu_iommu_domain_teardown(struct domain *d)
> +{
> +	struct arm_smmu_xen_domain *xen_domain = dom_iommu(d)->arch.priv;
> +
> +	ASSERT(list_empty(&xen_domain->contexts));
> +	xfree(xen_domain);
> +}
> +
> +static int __must_check arm_smmu_map_page(struct domain *d, unsigned long gfn,
> +			unsigned long mfn, unsigned int flags)
> +{
> +	p2m_type_t t;
> +
> +	/*
> +	 * Grant mappings can be used for DMA requests. The dev_bus_addr
> +	 * returned by the hypercall is the MFN (not the IPA). For device
> +	 * protected by an IOMMU, Xen needs to add a 1:1 mapping in the domain
> +	 * p2m to allow DMA request to work.
> +	 * This is only valid when the domain is directed mapped. Hence this
> +	 * function should only be used by gnttab code with gfn == mfn.
> +	 */
> +	BUG_ON(!is_domain_direct_mapped(d));
> +	BUG_ON(mfn != gfn);
> +
> +	/* We only support readable and writable flags */
> +	if (!(flags & (IOMMUF_readable | IOMMUF_writable)))
> +		return -EINVAL;
> +
> +	t = (flags & IOMMUF_writable) ? p2m_iommu_map_rw : p2m_iommu_map_ro;
> +
> +	/*
> +	 * The function guest_physmap_add_entry replaces the current mapping
> +	 * if there is already one...
> +	 */
> +	return guest_physmap_add_entry(d, _gfn(gfn), _mfn(mfn), 0, t);
> +}
> +
> +static int __must_check arm_smmu_unmap_page(struct domain *d, unsigned long gfn)
> +{
> +	/*
> +	 * This function should only be used by gnttab code when the domain
> +	 * is direct mapped
> +	 */
> +	if (!is_domain_direct_mapped(d))
> +		return -EINVAL;
> +
> +	return guest_physmap_remove_page(d, _gfn(gfn), _mfn(gfn), 0);
> +}
> +
> +static const struct iommu_ops arm_smmu_iommu_ops = {
> +	.init = arm_smmu_iommu_domain_init,
> +	.hwdom_init = arm_smmu_iommu_hwdom_init,
> +	.teardown = arm_smmu_iommu_domain_teardown,
> +	.iotlb_flush = arm_smmu_iotlb_flush,
> +	.iotlb_flush_all = arm_smmu_iotlb_flush_all,
> +	.assign_device = arm_smmu_assign_dev,
> +	.reassign_device = arm_smmu_reassign_dev,
> +	.map_page = arm_smmu_map_page,
> +	.unmap_page = arm_smmu_unmap_page,
> +};
> +
> +static
> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
> +{
> +	struct arm_smmu_device *smmu = NULL;
> +
> +	spin_lock(&arm_smmu_devices_lock);
> +	list_for_each_entry(smmu, &arm_smmu_devices, devices) {
> +		if (smmu->dev->fwnode == fwnode)
> +			break;
> +	}
> +	spin_unlock(&arm_smmu_devices_lock);
> +
> +	return smmu;
> +}
> +
> +static __init int arm_smmu_dt_init(struct dt_device_node *dev,
> +				   const void *data)
> +{
> +	int rc;
> +
> +	/*
> +	 * Even if the device can't be initialized, we don't want to
> +	 * give the SMMU device to dom0.
> +	 */
> +	dt_device_set_used_by(dev, DOMID_XEN);
> +
> +	rc = arm_smmu_device_probe(dt_to_dev(dev));
> +	if (rc)
> +		return rc;
> +
> +	iommu_set_ops(&arm_smmu_iommu_ops);
> +
> +	return 0;
> +}
> +
> +DT_DEVICE_START(smmuv3, "ARM SMMU V3", DEVICE_IOMMU)
> +	.dt_match = arm_smmu_of_match,
> +	.init = arm_smmu_dt_init,
> +DT_DEVICE_END
> +
> +#ifdef CONFIG_ACPI
> +/* Set up the IOMMU */
> +static int __init arm_smmu_acpi_init(const void *data)
> +{
> +	int rc;
> +
> +	rc = arm_smmu_device_probe((struct device *)data);
> +	if (rc)
> +		return rc;
> +
> +	iommu_set_ops(&arm_smmu_iommu_ops);
> +	return 0;
> +}
> +
> +ACPI_DEVICE_START(asmmuv3, "ARM SMMU V3", DEVICE_IOMMU)
> +	.class_type = ACPI_IORT_NODE_SMMU_V3,
> +	.init = arm_smmu_acpi_init,
> +ACPI_DEVICE_END
> +
> +#endif
> diff --git a/xen/include/xen/linux_compat.h b/xen/include/xen/linux_compat.h
> new file mode 100644
> index 0000000000..8037be0a3e
> --- /dev/null
> +++ b/xen/include/xen/linux_compat.h
> @@ -0,0 +1,84 @@
> +/******************************************************************************
> + * include/xen/linux_compat.h
> + *
> + * Compatibility defines for porting code from Linux to Xen
> + *
> + * Copyright (c) 2017 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef __XEN_LINUX_COMPAT_H__
> +#define __XEN_LINUX_COMPAT_H__
> +
> +#include <asm/types.h>
> +
> +typedef paddr_t phys_addr_t;
> +typedef paddr_t dma_addr_t;
> +
> +typedef unsigned int gfp_t;
> +#define GFP_KERNEL 0
> +#define __GFP_ZERO 0x01U
> +
> +/* Helpers for IRQ functions */
> +#define free_irq release_irq
> +
> +enum irqreturn {
> +    IRQ_NONE,
> +    IRQ_HANDLED,
> +    IRQ_WAKE_THREAD,
> +};
> +
> +typedef enum irqreturn irqreturn_t;
> +
> +/* Device logger functions */
> +#define dev_dbg(dev, fmt, ...) printk(XENLOG_DEBUG fmt, ## __VA_ARGS__)
> +#define dev_notice(dev, fmt, ...) printk(XENLOG_INFO fmt, ## __VA_ARGS__)
> +#define dev_warn(dev, fmt, ...) printk(XENLOG_WARNING fmt, ## __VA_ARGS__)
> +#define dev_err(dev, fmt, ...) printk(XENLOG_ERR fmt, ## __VA_ARGS__)
> +#define dev_info(dev, fmt, ...) printk(XENLOG_INFO fmt, ## __VA_ARGS__)
> +
> +#define dev_err_ratelimited(dev, fmt, ...)                  \
> +     printk(XENLOG_ERR fmt, ## __VA_ARGS__)
> +
> +#define dev_name(dev) dt_node_full_name(dev_to_dt(dev))
> +
> +/* Alias to Xen allocation helpers */
> +#define kfree xfree
> +#define kmalloc(size, flags) ({\
> +	void *__ret_alloc = NULL; \
> +	if (flags & __GFP_ZERO) \
> +		__ret_alloc = _xzalloc(size, sizeof(void *)); \
> +	else \
> +		__ret_alloc = _xmalloc(size, sizeof(void *)); \
> +	__ret_alloc; \
> +})
> +#define kzalloc(size, flags)        _xzalloc(size, sizeof(void *))
> +#define devm_kzalloc(dev, size, flags)  _xzalloc(size, sizeof(void *))
> +#define kmalloc_array(size, n, flags) ({\
> +	void *__ret_alloc = NULL; \
> +	if (flags & __GFP_ZERO) \
> +		__ret_alloc = _xzalloc_array(size, sizeof(void *), n); \
> +	else \
> +		__ret_alloc = _xmalloc_array(size, sizeof(void *), n); \
> +	__ret_alloc; \
> +})
> +
> +/* Alias to Xen time functions */
> +#define ktime_t s_time_t
> +#define ktime_get()             (NOW())
> +#define ktime_add_us(t,i)       (t + MICROSECS(i))
> +#define ktime_compare(t,i)      (t > (i))
> +
> +#endif /* __XEN_LINUX_COMPAT_H__ */

On 10 March 2018 at 23:23, Manish Jaggi <mjaggi@caviumnetworks.com> wrote:
> Hi Sameer,

>

>

>

> On 02/09/2018 08:40 AM, Sameer Goel wrote:

>>

>> This driver follows an approach similar to smmu driver. The intent here

>> is to reuse as much Linux code as possible.

>> - Glue code has been introduced to bridge the API calls.

>> - Called Linux functions from the Xen IOMMU function calls.

>> - Xen modifications are preceded by /*Xen: comment */

>> - xen/linux_compat: Add a Linux compat header

>>    For porting files directly from Linux it is useful to have a function

>> mapping

>>    definitions from Linux to Xen. This file adds common API functions and

>>    other defines that are needed for porting arm SMMU drivers.

>>

>> Signed-off-by: Sameer Goel <sameer.goel@linaro.org>

>> ---

>>   xen/arch/arm/p2m.c                    |   1 +

>>   xen/drivers/Kconfig                   |   2 +

>>   xen/drivers/passthrough/arm/Kconfig   |   8 +

>>   xen/drivers/passthrough/arm/Makefile  |   1 +

>>   xen/drivers/passthrough/arm/smmu-v3.c | 892

>> ++++++++++++++++++++++++++++++++--

>>   xen/include/xen/linux_compat.h        |  84 ++++

>>   6 files changed, 959 insertions(+), 29 deletions(-)

>>   create mode 100644 xen/drivers/passthrough/arm/Kconfig

>>   create mode 100644 xen/include/xen/linux_compat.h

>>

>> diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c

>> index 65e8b9c6ea..fef7605fd6 100644

>> --- a/xen/arch/arm/p2m.c

>> +++ b/xen/arch/arm/p2m.c

>> @@ -1460,6 +1460,7 @@ err:

>>   static void __init setup_virt_paging_one(void *data)

>>   {

>>       unsigned long val = (unsigned long)data;

>> +    /* SMMUv3 S2 cfg vtcr reuses the following value */

>>       WRITE_SYSREG32(val, VTCR_EL2);

>>       isb();

>>   }

>> diff --git a/xen/drivers/Kconfig b/xen/drivers/Kconfig

>> index bc3a54f0ea..612655386d 100644

>> --- a/xen/drivers/Kconfig

>> +++ b/xen/drivers/Kconfig

>> @@ -12,4 +12,6 @@ source "drivers/pci/Kconfig"

>>     source "drivers/video/Kconfig"

>>   +source "drivers/passthrough/arm/Kconfig"

>> +

>>   endmenu

>> diff --git a/xen/drivers/passthrough/arm/Kconfig

>> b/xen/drivers/passthrough/arm/Kconfig

>> new file mode 100644

>> index 0000000000..cda899f608

>> --- /dev/null

>> +++ b/xen/drivers/passthrough/arm/Kconfig

>> @@ -0,0 +1,8 @@

>> +

>> +config ARM_SMMU_v3

>> +       bool "ARM SMMUv3 Support"

>> +       depends on ARM_64

>> +       help

>> +        Support for implementations of the ARM System MMU architecture

>> +        version 3.

>> +

>> diff --git a/xen/drivers/passthrough/arm/Makefile

>> b/xen/drivers/passthrough/arm/Makefile

>> index f4cd26e15d..e14732b55c 100644

>> --- a/xen/drivers/passthrough/arm/Makefile

>> +++ b/xen/drivers/passthrough/arm/Makefile

>> @@ -1,2 +1,3 @@

>>   obj-y += iommu.o

>>   obj-y += smmu.o

>> +obj-$(CONFIG_ARM_SMMU_v3) += smmu-v3.o

>> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c

>> b/xen/drivers/passthrough/arm/smmu-v3.c

>> index e67ba6c40f..f43485fe6e 100644

>> --- a/xen/drivers/passthrough/arm/smmu-v3.c

>> +++ b/xen/drivers/passthrough/arm/smmu-v3.c

>> @@ -18,28 +18,414 @@

>>    * Author: Will Deacon <will.deacon@arm.com>

>>    *

>>    * This driver is powered by bad coffee and bombay mix.

>> + *

>> + *

>> + * Based on Linux drivers/iommu/arm-smmu-v3.c

>> + * => commit 7aa8619a66aea52b145e04cbab4f8d6a4e5f3f3b

>> + *

>> + * Xen modifications:

>> + * Sameer Goel <sameer.goel@linaro.org>

>> + * Copyright (C) 2017, The Linux Foundation, All rights reserved.

>> + *

>> + */

>> +

>> +#include <xen/acpi.h>

>> +#include <xen/config.h>

>> +#include <xen/delay.h>

>> +#include <xen/errno.h>

>> +#include <xen/err.h>

>> +#include <xen/irq.h>

>> +#include <xen/lib.h>

>> +#include <xen/linux_compat.h>

>> +#include <xen/list.h>

>> +#include <xen/mm.h>

>> +#include <xen/rbtree.h>

>> +#include <xen/sched.h>

>> +#include <xen/sizes.h>

>> +#include <xen/vmap.h>

>> +#include <acpi/acpi_iort.h>

>> +#include <asm/atomic.h>

>> +#include <asm/device.h>

>> +#include <asm/io.h>

>> +#include <asm/platform.h>

>> +

>> +/* Alias to Xen device tree helpers */

>> +#define device_node dt_device_node

>> +#define of_phandle_args dt_phandle_args

>> +#define of_device_id dt_device_match

>> +#define of_match_node dt_match_node

>> +#define of_property_read_u32(np, pname, out) (!dt_property_read_u32(np,

>> pname, out))

>> +#define of_property_read_bool dt_property_read_bool

>> +#define of_parse_phandle_with_args dt_parse_phandle_with_args

>> +

>> +/* Xen: Helpers to get device MMIO and IRQs */

>> +struct resource {

>> +       u64 addr;

>> +       u64 size;

>> +       unsigned int type;

>> +};

>> +

>> +#define resource_size(res) ((res)->size)

>> +

>> +#define platform_device device

>> +

>> +#define IORESOURCE_MEM 0

>> +#define IORESOURCE_IRQ 1

>> +

>> +static struct resource *platform_get_resource(struct platform_device

>> *pdev,

>> +                                             unsigned int type,

>> +                                             unsigned int num)

>> +{

>> +       /*

>> +        * The resource is only used between 2 calls of

>> platform_get_resource.

>> +        * It's quite ugly but it's avoid to add too much code in the

part
>> +        * imported from Linux

>> +        */

>> +       static struct resource res;

>> +       struct acpi_iort_node *iort_node;

>> +       struct acpi_iort_smmu_v3 *node_smmu_data;

>> +       int ret = 0;

>> +

>> +       res.type = type;

>> +

>> +       switch (type) {

>> +       case IORESOURCE_MEM:

>> +               if (pdev->type == DEV_ACPI) {

>> +                       ret = 1;

>> +                       iort_node = pdev->acpi_node;

>> +                       node_smmu_data =

>> +                               (struct acpi_iort_smmu_v3

>> *)iort_node->node_data;

>> +

>> +                       if (node_smmu_data != NULL) {

>> +                               res.addr = node_smmu_data->base_address;

>> +                               res.size = SZ_128K;

>> +                               ret = 0;

>> +                       }

>> +               } else {

>> +                       ret = dt_device_get_address(dev_to_dt(pdev), num,

>> +                                                   &res.addr,

&res.size);
>> +               }

>> +

>> +               return ((ret) ? NULL : &res);

>> +

>> +       case IORESOURCE_IRQ:

>> +               /* ACPI case not implemented as there is no use case for

>> it */

>> +               ret = platform_get_irq(dev_to_dt(pdev), num);

>> +

>> +               if (ret < 0)

>> +                       return NULL;

>> +

>> +               res.addr = ret;

>> +               res.size = 1;

>> +

>> +               return &res;

>> +

>> +       default:

>> +               return NULL;

>> +       }

>> +}

>> +

>> +static int platform_get_irq_byname(struct platform_device *pdev, const

>> char *name)

>> +{

>> +       const struct dt_property *dtprop;

>> +       struct acpi_iort_node *iort_node;

>> +       struct acpi_iort_smmu_v3 *node_smmu_data;

>> +       int ret = 0;

>> +

>> +       if (pdev->type == DEV_ACPI) {

>> +               iort_node = pdev->acpi_node;

>> +               node_smmu_data = (struct acpi_iort_smmu_v3

>> *)iort_node->node_data;

>> +

>> +               if (node_smmu_data != NULL) {

>> +                       if (!strcmp(name, "eventq"))

>> +                               ret = node_smmu_data->event_gsiv;

>> +                       else if (!strcmp(name, "priq"))

>> +                               ret = node_smmu_data->pri_gsiv;

>> +                       else if (!strcmp(name, "cmdq-sync"))

>> +                               ret = node_smmu_data->sync_gsiv;

>> +                       else if (!strcmp(name, "gerror"))

>> +                               ret = node_smmu_data->gerr_gsiv;

>> +                       else

>> +                               ret = -EINVAL;

>> +               }

>> +       } else {

>> +               dtprop = dt_find_property(dev_to_dt(pdev),

>> "interrupt-names", NULL);

>> +               if (!dtprop)

>> +                       return -EINVAL;

>> +

>> +               if (!dtprop->value)

>> +                       return -ENODATA;

>> +       }

>> +

>> +       return ret;

>> +}

>> +

>> +/*

>> + * Xen: Helpers for DMA allocation. Just the function name is reused for

>> + * porting code these allocation are not managed allocations

>>    */

>>   -#include <linux/acpi.h>

>> -#include <linux/acpi_iort.h>

>> -#include <linux/delay.h>

>> -#include <linux/dma-iommu.h>

>> -#include <linux/err.h>

>> -#include <linux/interrupt.h>

>> -#include <linux/iommu.h>

>> -#include <linux/iopoll.h>

>> -#include <linux/module.h>

>> -#include <linux/msi.h>

>> -#include <linux/of.h>

>> -#include <linux/of_address.h>

>> -#include <linux/of_iommu.h>

>> -#include <linux/of_platform.h>

>> -#include <linux/pci.h>

>> -#include <linux/platform_device.h>

>> -

>> -#include <linux/amba/bus.h>

>> -

>> -#include "io-pgtable.h"

>> +static void *dmam_alloc_coherent(struct device *dev, size_t size,

>> +                          dma_addr_t *dma_handle, gfp_t gfp)

>> +{

>> +       void *vaddr;

>> +       unsigned long alignment = size;

>> +

>> +       /*

>> +        * _xzalloc requires that the (align & (align -1)) = 0. Most of

>> the

>> +        * allocations in SMMU code should send the right value for size.

>> In

>> +        * case this is not true print a warning and align to the size of

>> a

>> +        * (void *)

>> +        */

>> +       if (size & (size - 1)) {

>> +               dev_warn(dev, "Fixing alignment for the DMA buffer\n");

>> +               alignment = sizeof(void *);

>> +       }

>> +

>> +       vaddr = _xzalloc(size, alignment);

>> +       if (!vaddr) {

>> +               dev_err(dev, "DMA allocation failed\n");

>> +               return NULL;

>> +       }

>> +

>> +       *dma_handle = virt_to_maddr(vaddr);

>> +

>> +       return vaddr;

>> +}

>> +

>> +

>> +static void dmam_free_coherent(struct device *dev, size_t size, void

>> *vaddr,

>> +                       dma_addr_t dma_handle)

>> +{

>> +       xfree(vaddr);

>> +}

>> +

>> +/* Xen: Stub out DMA domain related functions */

>> +#define iommu_get_dma_cookie(dom) 0

>> +#define iommu_put_dma_cookie(dom)

>> +

>> +/* Xen: Stub out module param related function */

>> +#define module_param_named(a, b, c, d)

>> +#define MODULE_PARM_DESC(a, b)

>> +

>> +#define dma_set_mask_and_coherent(d, b) 0

>> +

>> +#define of_dma_is_coherent(n) 0

>> +

>> +#define MODULE_DEVICE_TABLE(type, name)

>> +

>> +static void __iomem *devm_ioremap_resource(struct device *dev,

>> +                                          struct resource *res)

>> +{

>> +       void __iomem *ptr;

>> +

>> +       if (!res || res->type != IORESOURCE_MEM) {

>> +               dev_err(dev, "Invalid resource\n");

>> +               return ERR_PTR(-EINVAL);

>> +       }

>> +

>> +       ptr = ioremap_nocache(res->addr, res->size);

>> +       if (!ptr) {

>> +               dev_err(dev,

>> +                       "ioremap failed (addr 0x%"PRIx64" size

>> 0x%"PRIx64")\n",

>> +                       res->addr, res->size);

>> +               return ERR_PTR(-ENOMEM);

>> +       }

>> +

>> +       return ptr;

>> +}

>> +

>> +/* Xen: Compatibility define for iommu_domain_geometry.*/

>> +struct iommu_domain_geometry {

>> +       dma_addr_t aperture_start; /* First address that can be mapped

>> */

>> +       dma_addr_t aperture_end;   /* Last address that can be mapped

>> */

>> +       bool force_aperture;       /* DMA only allowed in mappable range?

>> */

>> +};

>> +

>> +

>> +/* Xen: Type definitions for iommu_domain */

>> +#define IOMMU_DOMAIN_UNMANAGED 0

>> +#define IOMMU_DOMAIN_DMA 1

>> +#define IOMMU_DOMAIN_IDENTITY 2

>> +

>> +/* Xen: Dummy iommu_domain */

>> +struct iommu_domain {

>> +       /* Runtime SMMU configuration for this iommu_domain */

>> +       struct arm_smmu_domain          *priv;

>> +       unsigned int type;

>> +

>> +       /* Dummy compatibility defines */

>> +       unsigned long pgsize_bitmap;

>> +       struct iommu_domain_geometry geometry;

>> +

>> +       atomic_t ref;

>> +       /*

>> +        * Used to link iommu_domain contexts for a same domain.

>> +        * There is at least one per-SMMU to used by the domain.

>> +        */

>> +       struct list_head                list;

>> +};

>> +

>> +/* Xen: Describes information required for a Xen domain */

>> +struct arm_smmu_xen_domain {

>> +       spinlock_t                      lock;

>> +       /* List of iommu domains associated to this domain */

>> +       struct list_head                contexts;

>> +};

>> +

>> +/*

>> + * Xen: Information about each device stored in dev->archdata.iommu

>> + *

>> + * The dev->archdata.iommu stores the iommu_domain (runtime

configuration
>> of

>> + * the SMMU).

>> + */

>> +struct arm_smmu_xen_device {

>> +       struct iommu_domain *domain;

>> +};

>> +

>> +/*

>> + * Xen: io_pgtable compatibility defines.

>> + * Most of these are to port in the S1 translation code as is.

>> + */

>> +struct io_pgtable_ops {

>> +};

>> +

>> +struct iommu_gather_ops {

>> +       void (*tlb_flush_all)(void *cookie);

>> +       void (*tlb_add_flush)(unsigned long iova, size_t size, size_t

>> granule,

>> +                             bool leaf, void *cookie);

>> +       void (*tlb_sync)(void *cookie);

>> +};

>> +

>> +struct io_pgtable_cfg {

>> +       /*

>> +        * IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE bits

>> in

>> +        *      stage 1 PTEs, for hardware which insists on validating

>> them

>> +        *      even in non-secure state where they should normally be

>> ignored.

>> +        *

>> +        * IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE

>> and

>> +        *      IOMMU_NOEXEC flags and map everything with full access,

>> for

>> +        *      hardware which does not implement the permissions of a

>> given

>> +        *      format, and/or requires some format-specific default

>> value.

>> +        *

>> +        * IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching

>> invalid

>> +        *      (unmapped) entries but the hardware might do so anyway,

>> perform

>> +        *      TLB maintenance when mapping as well as when unmapping.

>> +        *

>> +        * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in

all
>> +        *      PTEs, for Mediatek IOMMUs which treat it as a 33rd

address
>> bit

>> +        *      when the SoC is in "4GB mode" and they can only access

the
>> high

>> +        *      remap of DRAM (0x1_00000000 to 0x1_ffffffff).

>> +        *

>> +        * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only

>> ever

>> +        *      be accessed by a fully cache-coherent IOMMU or CPU (e.g.

>> for a

>> +        *      software-emulated IOMMU), such that pagetable updates

need
>> not

>> +        *      be treated as explicit DMA data.

>> +        */

>> +       #define IO_PGTABLE_QUIRK_ARM_NS         BIT(0)

>> +       #define IO_PGTABLE_QUIRK_NO_PERMS       BIT(1)

>> +       #define IO_PGTABLE_QUIRK_TLBI_ON_MAP    BIT(2)

>> +       #define IO_PGTABLE_QUIRK_ARM_MTK_4GB    BIT(3)

>> +       #define IO_PGTABLE_QUIRK_NO_DMA         BIT(4)

>> +       unsigned long                   quirks;

>> +       unsigned long                   pgsize_bitmap;

>> +       unsigned int                    ias;

>> +       unsigned int                    oas;

>> +       const struct iommu_gather_ops   *tlb;

>> +       struct device                   *iommu_dev;

>> +

>> +       /* Low-level data specific to the table format */

>> +       union {

>> +               struct {

>> +                       u64     ttbr[2];

>> +                       u64     tcr;

>> +                       u64     mair[2];

>> +               } arm_lpae_s1_cfg;

>> +

>> +               struct {

>> +                       u64     vttbr;

>> +                       u64     vtcr;

>> +               } arm_lpae_s2_cfg;

>> +

>> +               struct {

>> +                       u32     ttbr[2];

>> +                       u32     tcr;

>> +                       u32     nmrr;

>> +                       u32     prrr;

>> +               } arm_v7s_cfg;

>> +       };

>> +};

>> +

>> +enum io_pgtable_fmt {

>> +       ARM_32_LPAE_S1,

>> +       ARM_32_LPAE_S2,

>> +       ARM_64_LPAE_S1,

>> +       ARM_64_LPAE_S2,

>> +       ARM_V7S,

>> +       IO_PGTABLE_NUM_FMTS,

>> +};

>> +

>> +/*

>> + * Xen: The pgtable_ops are used by the S1 translations, so return the

>> dummy

>> + * address.

>> + */

>> +#define alloc_io_pgtable_ops(f, c, o) ((struct io_pgtable_ops *)0x0)

>

> Is this correct? it will make the caller null check fail

In your earlier patch it was

#define alloc_io_pgtable_ops(f, c, o) ((struct io_pgtable_ops *)0xDEADBEEF)

>

>> +#define free_io_pgtable_ops(o)

>> +

>> +/* Xen: Define wrapper for requesting IRQs */

>> +#define IRQF_ONESHOT 0

>> +

>> +typedef void (*irq_handler_t)(int, void *, struct cpu_user_regs *);

>> +

>> +static inline int devm_request_irq(struct device *dev, unsigned int irq,

>> +                                  irq_handler_t handler, unsigned long

>> irqflags,

>> +                                  const char *devname, void *dev_id)

>> +{

>> +       /*

>> +        * SMMUv3 implementation can support wired interrupt outputs that

>> are

>> +        * edge-triggered. Set the irq type as per the spec.

>> +        */

>> +       irq_set_type(irq, IRQ_TYPE_EDGE_BOTH);

>> +       return request_irq(irq, irqflags, handler, devname, dev_id);

>> +}

>> +

>> +/*

>> + * Xen does not have a concept of threaded irq, but eventually we can

use
>> + * tasklets to optimize the following function.

>> + */

>> +int devm_request_threaded_irq(struct device *dev, unsigned int irq,

>> irq_handler_t handler,

>> +                             irq_handler_t thread_fn, unsigned long

>> irqflags,

>> +                             const char *devname, void *dev_id)

>> +{

>> +       return devm_request_irq(dev, irq, thread_fn, irqflags, devname,

>> dev_id);

>> +}

>> +

>> +/* Xen: The mutex is used only during initialization so the typecast is

>> safe */

>> +#define mutex spinlock

>> +#define mutex_init spin_lock_init

>> +#define mutex_lock spin_lock

>> +#define mutex_unlock spin_unlock

>> +

>> +#define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \

>> +({ \

>> +       s_time_t deadline = NOW() + MICROSECS(timeout_us); \

>> +       for (;;) { \

>> +               (val) = op(addr); \

>> +               if (cond) \

>> +                       break; \

>> +               if (NOW() > deadline) { \

>> +                       (val) = op(addr); \

>> +                       break; \

>> +               } \

>> +       udelay(sleep_us); \

>> +       } \

>> +       (cond) ? 0 : -ETIMEDOUT; \

>> +})

>> +

>> +#define readl_relaxed_poll_timeout(addr, val, cond, delay_us,

timeout_us)
>> \

>> +       readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us,

>> timeout_us)

>> +

>> +#define VA_BITS 0 /* Only needed for S1 translations */

>>     /* MMIO registers */

>>   #define ARM_SMMU_IDR0                 0x0

>> @@ -433,6 +819,7 @@ enum pri_resp {

>>         PRI_RESP_SUCC,

>>   };

>>   +#if 0 /* Xen: No MSI support in this iteration */

>>   enum arm_smmu_msi_index {

>>         EVTQ_MSI_INDEX,

>>         GERROR_MSI_INDEX,

>> @@ -457,6 +844,7 @@ static phys_addr_t

>> arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {

>>                 ARM_SMMU_PRIQ_IRQ_CFG2,

>>         },

>>   };

>> +#endif

>>     struct arm_smmu_cmdq_ent {

>>         /* Common fields */

>> @@ -561,6 +949,8 @@ struct arm_smmu_s2_cfg {

>>         u16                             vmid;

>>         u64                             vttbr;

>>         u64                             vtcr;

>> +       /* Xen: Domain associated to this configuration */

>> +       struct domain                   *domain;

>>   };

>>     struct arm_smmu_strtab_ent {

>> @@ -635,9 +1025,21 @@ struct arm_smmu_device {

>>         struct arm_smmu_strtab_cfg      strtab_cfg;

>>         /* IOMMU core code handle */

>> +#if 0 /*Xen: Generic iommu_device ref not needed here */

>>         struct iommu_device             iommu;

>> +#endif

>> +       /* Xen: Need to keep a list of SMMU devices */

>> +       struct list_head                devices;

>>   };

>>   +/* Xen: Keep a list of devices associated with this driver */

>> +static DEFINE_SPINLOCK(arm_smmu_devices_lock);

>> +static LIST_HEAD(arm_smmu_devices);

>> +/* Xen: Helper for finding a device using fwnode */

>> +static

>> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle

>> *fwnode);

>> +

>> +

>>   /* SMMU private data for each master */

>>   struct arm_smmu_master_data {

>>         struct arm_smmu_device          *smmu;

>> @@ -1232,7 +1634,7 @@ static void arm_smmu_handle_ppr(struct

>> arm_smmu_device *smmu, u64 *evt)

>>         dev_info(smmu->dev, "unexpected PRI request received:\n");

>>         dev_info(smmu->dev,

>> -                "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access

>> at iova 0x%016llx\n",

>> +                "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access

>> at iova %#" PRIx64 "\n",

>>                  sid, ssid, grpid, last ? "L" : "",

>>                  evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",

>>                  evt[0] & PRIQ_0_PERM_READ ? "R" : "",

>> @@ -1346,6 +1748,8 @@ static irqreturn_t

arm_smmu_combined_irq_handler(int
>> irq, void *dev)

>>   {

>>         arm_smmu_gerror_handler(irq, dev);

>>         arm_smmu_cmdq_sync_handler(irq, dev);

>> +       /*Xen: No threaded irq. So call the required function from here

*/
>> +       arm_smmu_combined_irq_thread(irq, dev);

>>         return IRQ_WAKE_THREAD;

>>   }

>>   @@ -1358,6 +1762,46 @@ static void __arm_smmu_tlb_sync(struct

>> arm_smmu_device *smmu)

>>         arm_smmu_cmdq_issue_cmd(smmu, &cmd);

>>   }

>>   +/*

>> + * Xen: Define the IRQ handlers for xen. The linux functions would be

>> + * modified to use the functions defined in the following code.

>> + */

>> +static void arm_smmu_evtq_thread_xen(int irq, void *dev,

>> +                                      struct cpu_user_regs *regs)

>> +{

>> +       arm_smmu_evtq_thread(irq, dev);

>> +}

>> +

>> +static void arm_smmu_priq_thread_xen(int irq, void *dev,

>> +                                      struct cpu_user_regs *regs)

>> +{

>> +       arm_smmu_priq_thread(irq, dev);

>> +}

>> +

>> +static void arm_smmu_cmdq_sync_handler_xen(int irq, void *dev,

>> +                                      struct cpu_user_regs *regs)

>> +{

>> +       arm_smmu_cmdq_sync_handler(irq, dev);

>> +}

>> +

>> +static void arm_smmu_gerror_handler_xen(int irq, void *dev,

>> +                                      struct cpu_user_regs *regs)

>> +{

>> +       arm_smmu_gerror_handler(irq, dev);

>> +}

>> +

>> +static void arm_smmu_combined_irq_handler_xen(int irq, void *dev,

>> +                                      struct cpu_user_regs *regs)

>> +{

>> +       arm_smmu_combined_irq_handler(irq, dev);

>> +}

>> +

>> +#define arm_smmu_evtq_thread arm_smmu_evtq_thread_xen

>> +#define arm_smmu_priq_thread arm_smmu_priq_thread_xen

>> +#define arm_smmu_cmdq_sync_handler arm_smmu_cmdq_sync_handler_xen

>> +#define arm_smmu_gerror_handler arm_smmu_gerror_handler_xen

>> +#define arm_smmu_combined_irq_handler arm_smmu_combined_irq_handler_xen

>> +

>>   static void arm_smmu_tlb_sync(void *cookie)

>>   {

>>         struct arm_smmu_domain *smmu_domain = cookie;

>> @@ -1415,6 +1859,7 @@ static const struct iommu_gather_ops

>> arm_smmu_gather_ops = {

>>         .tlb_sync       = arm_smmu_tlb_sync,

>>   };

>>   +#if 0 /*Xen: Unused functionality */

>>   /* IOMMU API */

>>   static bool arm_smmu_capable(enum iommu_cap cap)

>>   {

>> @@ -1427,6 +1872,7 @@ static bool arm_smmu_capable(enum iommu_cap cap)

>>                 return false;

>>         }

>>   }

>> +#endif

>>     static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)

>>   {

>> @@ -1546,9 +1992,16 @@ static int arm_smmu_domain_finalise_s2(struct

>> arm_smmu_domain *smmu_domain,

>>         if (vmid < 0)

>>                 return vmid;

>>   -     cfg->vmid       = (u16)vmid;

>> -       cfg->vttbr      = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;

>> -       cfg->vtcr       = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;

>> +       /*

>> +        * Xen: Get the ttbr and vtcr values

>> +        * vttbr: This is a shared value with the domain page table

>> +        * vtcr: The TCR settings are the same as CPU since the page

>> +        * tables are shared

>> +        */

>> +

>> +       cfg->vmid       = vmid;

>> +       cfg->vttbr      = page_to_maddr(cfg->domain->arch.p2m.root);

>> +       cfg->vtcr       = READ_SYSREG32(VTCR_EL2) &

>> STRTAB_STE_2_VTCR_MASK;

>>         return 0;

>>   }

>>   @@ -1604,6 +2057,7 @@ static int arm_smmu_domain_finalise(struct

>> iommu_domain *domain)

>>         if (smmu->features & ARM_SMMU_FEAT_COHERENCY)

>>                 pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_NO_DMA;

>>   +     /* Xen: pgtbl_ops gets an invalid address */

>>         pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);

>>         if (!pgtbl_ops)

>>                 return -ENOMEM;

>

> Will this not fail ?

>

>> @@ -1721,6 +2175,7 @@ out_unlock:

>>         return ret;

>>   }

>>   +#if 0 /* Xen: Unused functionality */

>>   static int arm_smmu_map(struct iommu_domain *domain, unsigned long

iova,
>>                         phys_addr_t paddr, size_t size, int prot)

>>   {

>> @@ -1772,6 +2227,7 @@ struct arm_smmu_device

>> *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)

>>         put_device(dev);

>>         return dev ? dev_get_drvdata(dev) : NULL;

>>   }

>> +#endif

>>     static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32

>> sid)

>>   {

>> @@ -1783,7 +2239,14 @@ static bool arm_smmu_sid_in_range(struct

>> arm_smmu_device *smmu, u32 sid)

>>         return sid < limit;

>>   }

>>   +/* Xen: Unused */

>> +#if 0

>>   static struct iommu_ops arm_smmu_ops;

>> +#endif

>> +

>> +/* Xen: Redefine arm_smmu_ops to what fwspec should evaluate */

>> +static const struct iommu_ops arm_smmu_iommu_ops;

>> +#define arm_smmu_ops arm_smmu_iommu_ops

>>     static int arm_smmu_add_device(struct device *dev)

>>   {

>> @@ -1791,8 +2254,11 @@ static int arm_smmu_add_device(struct device *dev)

>>         struct arm_smmu_device *smmu;

>>         struct arm_smmu_master_data *master;

>>         struct iommu_fwspec *fwspec = dev->iommu_fwspec;

>> +#if 0 /*Xen: iommu_group is not needed */

>>         struct iommu_group *group;

>> +#endif

>>   +     /* Xen: fwspec->ops are not needed */

>>         if (!fwspec || fwspec->ops != &arm_smmu_ops)

>>                 return -ENODEV;

>>         /*

>> @@ -1830,6 +2296,11 @@ static int arm_smmu_add_device(struct device *dev)

>>                 }

>>         }

>>   +/*

>> + * Xen: Do not need an iommu group as the stream data is carried by the

>> SMMU

>> + * master device object

>> + */

>> +#if 0

>>         group = iommu_group_get_for_dev(dev);

>>         if (!IS_ERR(group)) {

>>                 iommu_group_put(group);

>> @@ -1837,8 +2308,16 @@ static int arm_smmu_add_device(struct device *dev)

>>         }

>>         return PTR_ERR_OR_ZERO(group);

>> +#endif

>> +       return 0;

>>   }

>>   +/*

>> + * Xen: We can potentially support this function and destroy a device.

>> This

>> + * will be relevant for PCI hotplug. So, will be implemented as needed

>> after

>> + * passthrough support is available.

>> + */

>> +#if 0

>>   static void arm_smmu_remove_device(struct device *dev)

>>   {

>>         struct iommu_fwspec *fwspec = dev->iommu_fwspec;

>> @@ -1974,6 +2453,7 @@ static struct iommu_ops arm_smmu_ops = {

>>         .put_resv_regions       = arm_smmu_put_resv_regions,

>>         .pgsize_bitmap          = -1UL, /* Restricted during device

attach
>> */

>>   };

>> +#endif

>>     /* Probing and initialisation functions */

>>   static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,

>> @@ -2182,6 +2662,7 @@ static int arm_smmu_update_gbpa(struct

>> arm_smmu_device *smmu, u32 set, u32 clr)

>>                                           1, ARM_SMMU_POLL_TIMEOUT_US);

>>   }

>>   +#if 0 /* Xen: There is no MSI support as yet */

>>   static void arm_smmu_free_msis(void *data)

>>   {

>>         struct device *dev = data;

>> @@ -2247,12 +2728,15 @@ static void arm_smmu_setup_msis(struct

>> arm_smmu_device *smmu)

>>         /* Add callback to free MSIs on teardown */

>>         devm_add_action(dev, arm_smmu_free_msis, dev);

>>   }

>> +#endif

>>     static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)

>>   {

>>         int irq, ret;

>>   +#if 0 /*Xen: Cannot setup msis for now */

>>         arm_smmu_setup_msis(smmu);

>> +#endif

>>         /* Request interrupt lines */

>>         irq = smmu->evtq.q.irq;

>> @@ -2316,9 +2800,13 @@ static int arm_smmu_setup_irqs(struct

>> arm_smmu_device *smmu)

>>                  * Cavium ThunderX2 implementation doesn't not support

>> unique

>>                  * irq lines. Use single irq line for all the SMMUv3

>> interrupts.

>>                  */

>> -               ret = devm_request_threaded_irq(smmu->dev, irq,

>> +               /*

>> +                * Xen: Does not support threaded irqs, so serialise the

>> setup.

>> +                * This is the same for pris and event interrupt lines on

>> other

>> +                * systems

>> +                */

>> +               ret = devm_request_irq(smmu->dev, irq,

>>                                         arm_smmu_combined_irq_handler,

>> -                                       arm_smmu_combined_irq_thread,

>>                                         IRQF_ONESHOT,

>>                                         "arm-smmu-v3-combined-irq",

smmu);
>>                 if (ret < 0)

>> @@ -2542,8 +3030,14 @@ static int arm_smmu_device_hw_probe(struct

>> arm_smmu_device *smmu)

>>                 smmu->features |= ARM_SMMU_FEAT_STALLS;

>>         }

>>   +/*

>> + * Xen: Block stage 1 translations. By doing this here we do not need to

>> set the

>> + * domain->stage explicitly.

>> + */

>> +#if 0

>>         if (reg & IDR0_S1P)

>>                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;

>> +#endif

>>         if (reg & IDR0_S2P)

>>                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;

>> @@ -2616,10 +3110,12 @@ static int arm_smmu_device_hw_probe(struct

>> arm_smmu_device *smmu)

>>         if (reg & IDR5_GRAN4K)

>>                 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;

>>   +#if 0 /* Xen: SMMU ops do not have a pgsize_bitmap member for Xen */

>>         if (arm_smmu_ops.pgsize_bitmap == -1UL)

>>                 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;

>>         else

>>                 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;

>> +#endif

>>         /* Output address size */

>>         switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) {

>> @@ -2680,7 +3176,8 @@ static int arm_smmu_device_acpi_probe(struct

>> platform_device *pdev,

>>         struct device *dev = smmu->dev;

>>         struct acpi_iort_node *node;

>>   -     node = *(struct acpi_iort_node **)dev_get_platdata(dev);

>> +       /* Xen: Modification to get iort_node */

>> +       node = (struct acpi_iort_node *)dev->acpi_node;

>>         /* Retrieve SMMUv3 specific data */

>>         iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data;

>> @@ -2703,7 +3200,7 @@ static inline int arm_smmu_device_acpi_probe(struct

>> platform_device *pdev,

>>   static int arm_smmu_device_dt_probe(struct platform_device *pdev,

>>                                     struct arm_smmu_device *smmu)

>>   {

>> -       struct device *dev = &pdev->dev;

>> +       struct device *dev = pdev;

>>         u32 cells;

>>         int ret = -EINVAL;

>>   @@ -2716,6 +3213,7 @@ static int arm_smmu_device_dt_probe(struct

>> platform_device *pdev,

>>         parse_driver_options(smmu);

>>   +     /* Xen: of_dma_is_coherent is a stub till dt support is

introduced
>> */

>>         if (of_dma_is_coherent(dev->of_node))

>>                 smmu->features |= ARM_SMMU_FEAT_COHERENCY;

>>   @@ -2734,9 +3232,11 @@ static int arm_smmu_device_probe(struct

>> platform_device *pdev)

>>   {

>>         int irq, ret;

>>         struct resource *res;

>> +#if 0 /*Xen: Do not need to setup sysfs */

>>         resource_size_t ioaddr;

>> +#endif

>>         struct arm_smmu_device *smmu;

>> -       struct device *dev = &pdev->dev;

>> +       struct device *dev = pdev;/* Xen: dev is ignored */

>>         bool bypass;

>>         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);

>> @@ -2763,7 +3263,9 @@ static int arm_smmu_device_probe(struct

>> platform_device *pdev)

>>                 dev_err(dev, "MMIO region too small (%pr)\n", res);

>>                 return -EINVAL;

>>         }

>> +#if 0 /*Xen: Do not need to setup sysfs */

>>         ioaddr = res->start;

>> +#endif

>>         smmu->base = devm_ioremap_resource(dev, res);

>>         if (IS_ERR(smmu->base))

>> @@ -2802,13 +3304,18 @@ static int arm_smmu_device_probe(struct

>> platform_device *pdev)

>>                 return ret;

>>         /* Record our private device structure */

>> +       /* Xen: SMMU is not treated a a platform device*/

>> +#if 0

>>         platform_set_drvdata(pdev, smmu);

>> +#endif

>>         /* Reset the device */

>>         ret = arm_smmu_device_reset(smmu, bypass);

>>         if (ret)

>>                 return ret;

>>   +/* Xen: Not creating an IOMMU device list for Xen */

>> +#if 0

>>         /* And we're up. Go go go! */

>>         ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL,

>>                                      "smmu3.%pa", &ioaddr);

>> @@ -2844,9 +3351,20 @@ static int arm_smmu_device_probe(struct

>> platform_device *pdev)

>>                 if (ret)

>>                         return ret;

>>         }

>> +#endif

>> +       /*

>> +        * Xen: Keep a list of all probed devices. This will be used to

>> query

>> +        * the smmu devices based on the fwnode.

>> +        */

>> +       INIT_LIST_HEAD(&smmu->devices);

>> +       spin_lock(&arm_smmu_devices_lock);

>> +       list_add(&smmu->devices, &arm_smmu_devices);

>> +       spin_unlock(&arm_smmu_devices_lock);

>>         return 0;

>>   }

>>   +/* Xen: Unused function */

>> +#if 0

>>   static int arm_smmu_device_remove(struct platform_device *pdev)

>>   {

>>         struct arm_smmu_device *smmu = platform_get_drvdata(pdev);

>> @@ -2860,6 +3378,8 @@ static void arm_smmu_device_shutdown(struct

>> platform_device *pdev)

>>   {

>>         arm_smmu_device_remove(pdev);

>>   }

>> +#endif

>> +

>>     static const struct of_device_id arm_smmu_of_match[] = {

>>         { .compatible = "arm,smmu-v3", },

>> @@ -2867,6 +3387,7 @@ static const struct of_device_id

arm_smmu_of_match[]
>> = {

>>   };

>>   MODULE_DEVICE_TABLE(of, arm_smmu_of_match);

>>   +#if 0

>>   static struct platform_driver arm_smmu_driver = {

>>         .driver = {

>>                 .name           = "arm-smmu-v3",

>> @@ -2883,3 +3404,316 @@ IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3",

NULL);
>>   MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3

>> implementations");

>>   MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");

>>   MODULE_LICENSE("GPL v2");

>> +#endif

>> +

>> +/***** Start of Xen specific code *****/

>> +

>> +static int __must_check arm_smmu_iotlb_flush_all(struct domain *d)

>> +{

>> +       struct arm_smmu_xen_domain *smmu_domain =

dom_iommu(d)->arch.priv;
>> +       struct iommu_domain *cfg;

>> +

>> +       spin_lock(&smmu_domain->lock);

>> +       list_for_each_entry(cfg, &smmu_domain->contexts, list) {

>> +               /*

>> +                * Only invalidate the context when SMMU is present.

>> +                * This is because the context initialization is delayed

>> +                * until a master has been added.

>> +                */

>> +               if (unlikely(!ACCESS_ONCE(cfg->priv->smmu)))

>> +                       continue;

>> +               arm_smmu_tlb_inv_context(cfg->priv);

>> +       }

>> +       spin_unlock(&smmu_domain->lock);

>> +       return 0;

>> +}

>> +

>> +static int __must_check arm_smmu_iotlb_flush(struct domain *d,

>> +                                            unsigned long gfn,

>> +                                            unsigned int page_count)

>> +{

>> +       return arm_smmu_iotlb_flush_all(d);

>> +}

>> +

>> +static struct iommu_domain *arm_smmu_get_domain(struct domain *d,

>> +                                               struct device *dev)

>> +{

>> +       struct iommu_domain *domain;

>> +       struct arm_smmu_xen_domain *xen_domain;

>> +       struct arm_smmu_device *smmu;

>> +       struct arm_smmu_domain *smmu_domain;

>> +

>> +       xen_domain = dom_iommu(d)->arch.priv;

>> +

>> +       smmu = arm_smmu_get_by_fwnode(dev->iommu_fwspec->iommu_fwnode);

>> +       if (!smmu)

>> +               return NULL;

>> +

>> +       /*

>> +        * Loop through the &xen_domain->contexts to locate a context

>> +        * assigned to this SMMU

>> +        */

>> +       list_for_each_entry(domain, &xen_domain->contexts, list) {

>> +               smmu_domain = to_smmu_domain(domain);

>> +               if (smmu_domain->smmu == smmu)

>> +                       return domain;

>> +       }

>> +

>> +       return NULL;

>> +}

>> +

>> +static void arm_smmu_destroy_iommu_domain(struct iommu_domain *domain)

>> +{

>> +       list_del(&domain->list);

>> +       arm_smmu_domain_free(domain);

>> +}

>> +

>> +static int arm_smmu_assign_dev(struct domain *d, u8 devfn,

>> +                              struct device *dev, u32 flag)

>> +{

>> +       int ret = 0;

>> +       struct iommu_domain *domain;

>> +       struct arm_smmu_xen_domain *xen_domain;

>> +       struct arm_smmu_domain *arm_smmu;

>> +

>> +       xen_domain = dom_iommu(d)->arch.priv;

>> +

>> +       if (!dev->archdata.iommu) {

>> +               dev->archdata.iommu = xzalloc(struct

arm_smmu_xen_device);
>> +               if (!dev->archdata.iommu)

>> +                       return -ENOMEM;

>> +       }

>> +

>> +       ret = arm_smmu_add_device(dev);

>> +       if (ret)

>> +               return ret;

>> +

>> +       spin_lock(&xen_domain->lock);

>> +

>> +       /*

>> +        * Check to see if an iommu_domain already exists for this xen

>> domain

>> +        * under the same SMMU

>> +        */

>> +       domain = arm_smmu_get_domain(d, dev);

>> +       if (!domain) {

>> +

>> +               domain = arm_smmu_domain_alloc(IOMMU_DOMAIN_DMA);

>> +               if (!domain) {

>> +                       ret = -ENOMEM;

>> +                       goto out;

>> +               }

>> +

>> +               arm_smmu = to_smmu_domain(domain);

>> +               arm_smmu->s2_cfg.domain = d;

>> +

>> +               /* Chain the new context to the domain */

>> +               list_add(&domain->list, &xen_domain->contexts);

>> +

>> +       }

>> +

>> +       ret = arm_smmu_attach_dev(domain, dev);

>> +       if (ret) {

>> +               if (domain->ref.counter == 0)

>> +                       arm_smmu_destroy_iommu_domain(domain);

>> +       } else {

>> +               atomic_inc(&domain->ref);

>> +       }

>> +

>> +out:

>> +       spin_unlock(&xen_domain->lock);

>> +       return ret;

>> +}

>> +

>> +static int arm_smmu_deassign_dev(struct domain *d, struct device *dev)

>> +{

>> +       struct iommu_domain *domain = arm_smmu_get_domain(d, dev);

>> +       struct arm_smmu_xen_domain *xen_domain;

>> +       struct arm_smmu_domain *arm_smmu = to_smmu_domain(domain);

>> +

>> +       xen_domain = dom_iommu(d)->arch.priv;

>> +

>> +       if (!arm_smmu || arm_smmu->s2_cfg.domain != d) {

>> +               dev_err(dev, " not attached to domain %d\n",

>> d->domain_id);

>> +               return -ESRCH;

>> +       }

>> +

>> +       spin_lock(&xen_domain->lock);

>> +

>> +       arm_smmu_detach_dev(dev);

>> +       atomic_dec(&domain->ref);

>> +

>> +       if (domain->ref.counter == 0)

>> +               arm_smmu_destroy_iommu_domain(domain);

>> +

>> +       spin_unlock(&xen_domain->lock);

>> +

>> +       return 0;

>> +}

>> +

>> +static int arm_smmu_reassign_dev(struct domain *s, struct domain *t,

>> +                                u8 devfn,  struct device *dev)

>> +{

>> +       int ret = 0;

>> +

>> +       /* Don't allow remapping on other domain than hwdom */

>> +       if (t && t != hardware_domain)

>> +               return -EPERM;

>> +

>> +       if (t == s)

>> +               return 0;

>> +

>> +       ret = arm_smmu_deassign_dev(s, dev);

>> +       if (ret)

>> +               return ret;

>> +

>> +       if (t) {

>> +               /* No flags are defined for ARM. */

>> +               ret = arm_smmu_assign_dev(t, devfn, dev, 0);

>> +               if (ret)

>> +                       return ret;

>> +       }

>> +

>> +       return 0;

>> +}

>> +

>> +static int arm_smmu_iommu_domain_init(struct domain *d)

>> +{

>> +       struct arm_smmu_xen_domain *xen_domain;

>> +

>> +       xen_domain = xzalloc(struct arm_smmu_xen_domain);

>> +       if (!xen_domain)

>> +               return -ENOMEM;

>> +

>> +       spin_lock_init(&xen_domain->lock);

>> +       INIT_LIST_HEAD(&xen_domain->contexts);

>> +

>> +       dom_iommu(d)->arch.priv = xen_domain;

>> +

>> +       return 0;

>> +}

>> +

>> +static void __hwdom_init arm_smmu_iommu_hwdom_init(struct domain *d)

>> +{

>> +}

>> +

>> +static void arm_smmu_iommu_domain_teardown(struct domain *d)

>> +{

>> +       struct arm_smmu_xen_domain *xen_domain = dom_iommu(d)->arch.priv;

>> +

>> +       ASSERT(list_empty(&xen_domain->contexts));

>> +       xfree(xen_domain);

>> +}

>> +

>> +static int __must_check arm_smmu_map_page(struct domain *d, unsigned

long
>> gfn,

>> +                       unsigned long mfn, unsigned int flags)

>> +{

>> +       p2m_type_t t;

>> +

>> +       /*

>> +        * Grant mappings can be used for DMA requests. The dev_bus_addr

>> +        * returned by the hypercall is the MFN (not the IPA). For device

>> +        * protected by an IOMMU, Xen needs to add a 1:1 mapping in the

>> domain

>> +        * p2m to allow DMA request to work.

>> +        * This is only valid when the domain is directed mapped. Hence

>> this

>> +        * function should only be used by gnttab code with gfn == mfn.

>> +        */

>> +       BUG_ON(!is_domain_direct_mapped(d));

>> +       BUG_ON(mfn != gfn);

>> +

>> +       /* We only support readable and writable flags */

>> +       if (!(flags & (IOMMUF_readable | IOMMUF_writable)))

>> +               return -EINVAL;

>> +

>> +       t = (flags & IOMMUF_writable) ? p2m_iommu_map_rw :

>> p2m_iommu_map_ro;

>> +

>> +       /*

>> +        * The function guest_physmap_add_entry replaces the current

>> mapping

>> +        * if there is already one...

>> +        */

>> +       return guest_physmap_add_entry(d, _gfn(gfn), _mfn(mfn), 0, t);

>> +}

>> +

>> +static int __must_check arm_smmu_unmap_page(struct domain *d, unsigned

>> long gfn)

>> +{

>> +       /*

>> +        * This function should only be used by gnttab code when the

>> domain

>> +        * is direct mapped

>> +        */

>> +       if (!is_domain_direct_mapped(d))

>> +               return -EINVAL;

>> +

>> +       return guest_physmap_remove_page(d, _gfn(gfn), _mfn(gfn), 0);

>> +}

>> +

>> +static const struct iommu_ops arm_smmu_iommu_ops = {

>> +       .init = arm_smmu_iommu_domain_init,

>> +       .hwdom_init = arm_smmu_iommu_hwdom_init,

>> +       .teardown = arm_smmu_iommu_domain_teardown,

>> +       .iotlb_flush = arm_smmu_iotlb_flush,

>> +       .iotlb_flush_all = arm_smmu_iotlb_flush_all,

>> +       .assign_device = arm_smmu_assign_dev,

>> +       .reassign_device = arm_smmu_reassign_dev,

>> +       .map_page = arm_smmu_map_page,

>> +       .unmap_page = arm_smmu_unmap_page,

>> +};

>> +

>> +static

>> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle

>> *fwnode)

>> +{

>> +       struct arm_smmu_device *smmu = NULL;

>> +

>> +       spin_lock(&arm_smmu_devices_lock);

>> +       list_for_each_entry(smmu, &arm_smmu_devices, devices) {

>> +               if (smmu->dev->fwnode == fwnode)

>> +                       break;

>> +       }

>> +       spin_unlock(&arm_smmu_devices_lock);

>> +

>> +       return smmu;

>> +}

>> +

>> +static __init int arm_smmu_dt_init(struct dt_device_node *dev,

>> +                                  const void *data)

>> +{

>> +       int rc;

>> +

>> +       /*

>> +        * Even if the device can't be initialized, we don't want to

>> +        * give the SMMU device to dom0.

>> +        */

>> +       dt_device_set_used_by(dev, DOMID_XEN);

>> +

>> +       rc = arm_smmu_device_probe(dt_to_dev(dev));

>> +       if (rc)

>> +               return rc;

>> +

>> +       iommu_set_ops(&arm_smmu_iommu_ops);

>> +

>> +       return 0;

>> +}

>> +

>> +DT_DEVICE_START(smmuv3, "ARM SMMU V3", DEVICE_IOMMU)

>> +       .dt_match = arm_smmu_of_match,

>> +       .init = arm_smmu_dt_init,

>> +DT_DEVICE_END

>> +

>> +#ifdef CONFIG_ACPI

>> +/* Set up the IOMMU */

>> +static int __init arm_smmu_acpi_init(const void *data)

>> +{

>> +       int rc;

>> +

>> +       rc = arm_smmu_device_probe((struct device *)data);

>> +       if (rc)

>> +               return rc;

>> +

>> +       iommu_set_ops(&arm_smmu_iommu_ops);

>> +       return 0;

>> +}

>> +

>> +ACPI_DEVICE_START(asmmuv3, "ARM SMMU V3", DEVICE_IOMMU)

>> +       .class_type = ACPI_IORT_NODE_SMMU_V3,

>> +       .init = arm_smmu_acpi_init,

>> +ACPI_DEVICE_END

>> +

>> +#endif

>> diff --git a/xen/include/xen/linux_compat.h

>> b/xen/include/xen/linux_compat.h

>> new file mode 100644

>> index 0000000000..8037be0a3e

>> --- /dev/null

>> +++ b/xen/include/xen/linux_compat.h

>> @@ -0,0 +1,84 @@

>>

>>

+/******************************************************************************
>> + * include/xen/linux_compat.h

>> + *

>> + * Compatibility defines for porting code from Linux to Xen

>> + *

>> + * Copyright (c) 2017 Linaro Limited

>> + *

>> + * This program is free software; you can redistribute it and/or modify

>> + * it under the terms of the GNU General Public License as published by

>> + * the Free Software Foundation; either version 2 of the License, or

>> + * (at your option) any later version.

>> + *

>> + * This program is distributed in the hope that it will be useful,

>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of

>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

>> + * GNU General Public License for more details.

>> + *

>> + * You should have received a copy of the GNU General Public License

>> + * along with this program; If not, see <http://www.gnu.org/licenses/>.

>> + */

>> +

>> +#ifndef __XEN_LINUX_COMPAT_H__

>> +#define __XEN_LINUX_COMPAT_H__

>> +

>> +#include <asm/types.h>

>> +

>> +typedef paddr_t phys_addr_t;

>> +typedef paddr_t dma_addr_t;

>> +

>> +typedef unsigned int gfp_t;

>> +#define GFP_KERNEL 0

>> +#define __GFP_ZERO 0x01U

>> +

>> +/* Helpers for IRQ functions */

>> +#define free_irq release_irq

>> +

>> +enum irqreturn {

>> +    IRQ_NONE,

>> +    IRQ_HANDLED,

>> +    IRQ_WAKE_THREAD,

>> +};

>> +

>> +typedef enum irqreturn irqreturn_t;

>> +

>> +/* Device logger functions */

>> +#define dev_dbg(dev, fmt, ...) printk(XENLOG_DEBUG fmt, ## __VA_ARGS__)

>> +#define dev_notice(dev, fmt, ...) printk(XENLOG_INFO fmt, ##

__VA_ARGS__)
>> +#define dev_warn(dev, fmt, ...) printk(XENLOG_WARNING fmt, ##

>> __VA_ARGS__)

>> +#define dev_err(dev, fmt, ...) printk(XENLOG_ERR fmt, ## __VA_ARGS__)

>> +#define dev_info(dev, fmt, ...) printk(XENLOG_INFO fmt, ## __VA_ARGS__)

>> +

>> +#define dev_err_ratelimited(dev, fmt, ...)                  \

>> +     printk(XENLOG_ERR fmt, ## __VA_ARGS__)

>> +

>> +#define dev_name(dev) dt_node_full_name(dev_to_dt(dev))

>> +

>> +/* Alias to Xen allocation helpers */

>> +#define kfree xfree

>> +#define kmalloc(size, flags) ({\

>> +       void *__ret_alloc = NULL; \

>> +       if (flags & __GFP_ZERO) \

>> +               __ret_alloc = _xzalloc(size, sizeof(void *)); \

>> +       else \

>> +               __ret_alloc = _xmalloc(size, sizeof(void *)); \

>> +       __ret_alloc; \

>> +})

>> +#define kzalloc(size, flags)        _xzalloc(size, sizeof(void *))

>> +#define devm_kzalloc(dev, size, flags)  _xzalloc(size, sizeof(void *))

>> +#define kmalloc_array(size, n, flags) ({\

>> +       void *__ret_alloc = NULL; \

>> +       if (flags & __GFP_ZERO) \

>> +               __ret_alloc = _xzalloc_array(size, sizeof(void *), n); \

>> +       else \

>> +               __ret_alloc = _xmalloc_array(size, sizeof(void *), n); \

>> +       __ret_alloc; \

>> +})

>> +

>> +/* Alias to Xen time functions */

>> +#define ktime_t s_time_t

>> +#define ktime_get()             (NOW())

>> +#define ktime_add_us(t,i)       (t + MICROSECS(i))

>> +#define ktime_compare(t,i)      (t > (i))

>> +

>> +#endif /* __XEN_LINUX_COMPAT_H__ */

>

>

>

> _______________________________________________

> Xen-devel mailing list

> Xen-devel@lists.xenproject.org

> https://lists.xenproject.org/mailman/listinfo/xen-devel
<div dir="ltr"><br><br>On 10 March 2018 at 23:23, Manish Jaggi &lt;<a href="mailto:mjaggi@caviumnetworks.com">mjaggi@caviumnetworks.com</a>&gt; wrote:<br>&gt; Hi Sameer,<br>&gt;<br>&gt;<br>&gt;<br>&gt; On 02/09/2018 08:40 AM, Sameer Goel wrote:<br>&gt;&gt;<br>&gt;&gt; This driver follows an approach similar to smmu driver. The intent here<br>&gt;&gt; is to reuse as much Linux code as possible.<br>&gt;&gt; - Glue code has been introduced to bridge the API calls.<br>&gt;&gt; - Called Linux functions from the Xen IOMMU function calls.<br>&gt;&gt; - Xen modifications are preceded by /*Xen: comment */<br>&gt;&gt; - xen/linux_compat: Add a Linux compat header<br>&gt;&gt;    For porting files directly from Linux it is useful to have a function<br>&gt;&gt; mapping<br>&gt;&gt;    definitions from Linux to Xen. This file adds common API functions and<br>&gt;&gt;    other defines that are needed for porting arm SMMU drivers.<br>&gt;&gt;<br>&gt;&gt; Signed-off-by: Sameer Goel &lt;<a href="mailto:sameer.goel@linaro.org">sameer.goel@linaro.org</a>&gt;<br>&gt;&gt; ---<br>&gt;&gt;   xen/arch/arm/p2m.c                    |   1 +<br>&gt;&gt;   xen/drivers/Kconfig                   |   2 +<br>&gt;&gt;   xen/drivers/passthrough/arm/Kconfig   |   8 +<br>&gt;&gt;   xen/drivers/passthrough/arm/Makefile  |   1 +<br>&gt;&gt;   xen/drivers/passthrough/arm/smmu-v3.c | 892<br>&gt;&gt; ++++++++++++++++++++++++++++++++--<br>&gt;&gt;   xen/include/xen/linux_compat.h        |  84 ++++<br>&gt;&gt;   6 files changed, 959 insertions(+), 29 deletions(-)<br>&gt;&gt;   create mode 100644 xen/drivers/passthrough/arm/Kconfig<br>&gt;&gt;   create mode 100644 xen/include/xen/linux_compat.h<br>&gt;&gt;<br>&gt;&gt; diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c<br>&gt;&gt; index 65e8b9c6ea..fef7605fd6 100644<br>&gt;&gt; --- a/xen/arch/arm/p2m.c<br>&gt;&gt; +++ b/xen/arch/arm/p2m.c<br>&gt;&gt; @@ -1460,6 +1460,7 @@ err:<br>&gt;&gt;   static void __init setup_virt_paging_one(void *data)<br>&gt;&gt;   {<br>&gt;&gt;       unsigned long val = (unsigned long)data;<br>&gt;&gt; +    /* SMMUv3 S2 cfg vtcr reuses the following value */<br>&gt;&gt;       WRITE_SYSREG32(val, VTCR_EL2);<br>&gt;&gt;       isb();<br>&gt;&gt;   }<br>&gt;&gt; diff --git a/xen/drivers/Kconfig b/xen/drivers/Kconfig<br>&gt;&gt; index bc3a54f0ea..612655386d 100644<br>&gt;&gt; --- a/xen/drivers/Kconfig<br>&gt;&gt; +++ b/xen/drivers/Kconfig<br>&gt;&gt; @@ -12,4 +12,6 @@ source &quot;drivers/pci/Kconfig&quot;<br>&gt;&gt;     source &quot;drivers/video/Kconfig&quot;<br>&gt;&gt;   +source &quot;drivers/passthrough/arm/Kconfig&quot;<br>&gt;&gt; +<br>&gt;&gt;   endmenu<br>&gt;&gt; diff --git a/xen/drivers/passthrough/arm/Kconfig<br>&gt;&gt; b/xen/drivers/passthrough/arm/Kconfig<br>&gt;&gt; new file mode 100644<br>&gt;&gt; index 0000000000..cda899f608<br>&gt;&gt; --- /dev/null<br>&gt;&gt; +++ b/xen/drivers/passthrough/arm/Kconfig<br>&gt;&gt; @@ -0,0 +1,8 @@<br>&gt;&gt; +<br>&gt;&gt; +config ARM_SMMU_v3<br>&gt;&gt; +       bool &quot;ARM SMMUv3 Support&quot;<br>&gt;&gt; +       depends on ARM_64<br>&gt;&gt; +       help<br>&gt;&gt; +        Support for implementations of the ARM System MMU architecture<br>&gt;&gt; +        version 3.<br>&gt;&gt; +<br>&gt;&gt; diff --git a/xen/drivers/passthrough/arm/Makefile<br>&gt;&gt; b/xen/drivers/passthrough/arm/Makefile<br>&gt;&gt; index f4cd26e15d..e14732b55c 100644<br>&gt;&gt; --- a/xen/drivers/passthrough/arm/Makefile<br>&gt;&gt; +++ b/xen/drivers/passthrough/arm/Makefile<br>&gt;&gt; @@ -1,2 +1,3 @@<br>&gt;&gt;   obj-y += iommu.o<br>&gt;&gt;   obj-y += smmu.o<br>&gt;&gt; +obj-$(CONFIG_ARM_SMMU_v3) += smmu-v3.o<br>&gt;&gt; diff --git a/xen/drivers/passthrough/arm/smmu-v3.c<br>&gt;&gt; b/xen/drivers/passthrough/arm/smmu-v3.c<br>&gt;&gt; index e67ba6c40f..f43485fe6e 100644<br>&gt;&gt; --- a/xen/drivers/passthrough/arm/smmu-v3.c<br>&gt;&gt; +++ b/xen/drivers/passthrough/arm/smmu-v3.c<br>&gt;&gt; @@ -18,28 +18,414 @@<br>&gt;&gt;    * Author: Will Deacon &lt;<a href="mailto:will.deacon@arm.com">will.deacon@arm.com</a>&gt;<br>&gt;&gt;    *<br>&gt;&gt;    * This driver is powered by bad coffee and bombay mix.<br>&gt;&gt; + *<br>&gt;&gt; + *<br>&gt;&gt; + * Based on Linux drivers/iommu/arm-smmu-v3.c<br>&gt;&gt; + * =&gt; commit 7aa8619a66aea52b145e04cbab4f8d6a4e5f3f3b<br>&gt;&gt; + *<br>&gt;&gt; + * Xen modifications:<br>&gt;&gt; + * Sameer Goel &lt;<a href="mailto:sameer.goel@linaro.org">sameer.goel@linaro.org</a>&gt;<br>&gt;&gt; + * Copyright (C) 2017, The Linux Foundation, All rights reserved.<br>&gt;&gt; + *<br>&gt;&gt; + */<br>&gt;&gt; +<br>&gt;&gt; +#include &lt;xen/acpi.h&gt;<br>&gt;&gt; +#include &lt;xen/config.h&gt;<br>&gt;&gt; +#include &lt;xen/delay.h&gt;<br>&gt;&gt; +#include &lt;xen/errno.h&gt;<br>&gt;&gt; +#include &lt;xen/err.h&gt;<br>&gt;&gt; +#include &lt;xen/irq.h&gt;<br>&gt;&gt; +#include &lt;xen/lib.h&gt;<br>&gt;&gt; +#include &lt;xen/linux_compat.h&gt;<br>&gt;&gt; +#include &lt;xen/list.h&gt;<br>&gt;&gt; +#include &lt;xen/mm.h&gt;<br>&gt;&gt; +#include &lt;xen/rbtree.h&gt;<br>&gt;&gt; +#include &lt;xen/sched.h&gt;<br>&gt;&gt; +#include &lt;xen/sizes.h&gt;<br>&gt;&gt; +#include &lt;xen/vmap.h&gt;<br>&gt;&gt; +#include &lt;acpi/acpi_iort.h&gt;<br>&gt;&gt; +#include &lt;asm/atomic.h&gt;<br>&gt;&gt; +#include &lt;asm/device.h&gt;<br>&gt;&gt; +#include &lt;asm/io.h&gt;<br>&gt;&gt; +#include &lt;asm/platform.h&gt;<br>&gt;&gt; +<br>&gt;&gt; +/* Alias to Xen device tree helpers */<br>&gt;&gt; +#define device_node dt_device_node<br>&gt;&gt; +#define of_phandle_args dt_phandle_args<br>&gt;&gt; +#define of_device_id dt_device_match<br>&gt;&gt; +#define of_match_node dt_match_node<br>&gt;&gt; +#define of_property_read_u32(np, pname, out) (!dt_property_read_u32(np,<br>&gt;&gt; pname, out))<br>&gt;&gt; +#define of_property_read_bool dt_property_read_bool<br>&gt;&gt; +#define of_parse_phandle_with_args dt_parse_phandle_with_args<br>&gt;&gt; +<br>&gt;&gt; +/* Xen: Helpers to get device MMIO and IRQs */<br>&gt;&gt; +struct resource {<br>&gt;&gt; +       u64 addr;<br>&gt;&gt; +       u64 size;<br>&gt;&gt; +       unsigned int type;<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +#define resource_size(res) ((res)-&gt;size)<br>&gt;&gt; +<br>&gt;&gt; +#define platform_device device<br>&gt;&gt; +<br>&gt;&gt; +#define IORESOURCE_MEM 0<br>&gt;&gt; +#define IORESOURCE_IRQ 1<br>&gt;&gt; +<br>&gt;&gt; +static struct resource *platform_get_resource(struct platform_device<br>&gt;&gt; *pdev,<br>&gt;&gt; +                                             unsigned int type,<br>&gt;&gt; +                                             unsigned int num)<br>&gt;&gt; +{<br>&gt;&gt; +       /*<br>&gt;&gt; +        * The resource is only used between 2 calls of<br>&gt;&gt; platform_get_resource.<br>&gt;&gt; +        * It&#39;s quite ugly but it&#39;s avoid to add too much code in the part<br>&gt;&gt; +        * imported from Linux<br>&gt;&gt; +        */<br>&gt;&gt; +       static struct resource res;<br>&gt;&gt; +       struct acpi_iort_node *iort_node;<br>&gt;&gt; +       struct acpi_iort_smmu_v3 *node_smmu_data;<br>&gt;&gt; +       int ret = 0;<br>&gt;&gt; +<br>&gt;&gt; +       res.type = type;<br>&gt;&gt; +<br>&gt;&gt; +       switch (type) {<br>&gt;&gt; +       case IORESOURCE_MEM:<br>&gt;&gt; +               if (pdev-&gt;type == DEV_ACPI) {<br>&gt;&gt; +                       ret = 1;<br>&gt;&gt; +                       iort_node = pdev-&gt;acpi_node;<br>&gt;&gt; +                       node_smmu_data =<br>&gt;&gt; +                               (struct acpi_iort_smmu_v3<br>&gt;&gt; *)iort_node-&gt;node_data;<br>&gt;&gt; +<br>&gt;&gt; +                       if (node_smmu_data != NULL) {<br>&gt;&gt; +                               res.addr = node_smmu_data-&gt;base_address;<br>&gt;&gt; +                               res.size = SZ_128K;<br>&gt;&gt; +                               ret = 0;<br>&gt;&gt; +                       }<br>&gt;&gt; +               } else {<br>&gt;&gt; +                       ret = dt_device_get_address(dev_to_dt(pdev), num,<br>&gt;&gt; +                                                   &amp;res.addr, &amp;res.size);<br>&gt;&gt; +               }<br>&gt;&gt; +<br>&gt;&gt; +               return ((ret) ? NULL : &amp;res);<br>&gt;&gt; +<br>&gt;&gt; +       case IORESOURCE_IRQ:<br>&gt;&gt; +               /* ACPI case not implemented as there is no use case for<br>&gt;&gt; it */<br>&gt;&gt; +               ret = platform_get_irq(dev_to_dt(pdev), num);<br>&gt;&gt; +<br>&gt;&gt; +               if (ret &lt; 0)<br>&gt;&gt; +                       return NULL;<br>&gt;&gt; +<br>&gt;&gt; +               res.addr = ret;<br>&gt;&gt; +               res.size = 1;<br>&gt;&gt; +<br>&gt;&gt; +               return &amp;res;<br>&gt;&gt; +<br>&gt;&gt; +       default:<br>&gt;&gt; +               return NULL;<br>&gt;&gt; +       }<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static int platform_get_irq_byname(struct platform_device *pdev, const<br>&gt;&gt; char *name)<br>&gt;&gt; +{<br>&gt;&gt; +       const struct dt_property *dtprop;<br>&gt;&gt; +       struct acpi_iort_node *iort_node;<br>&gt;&gt; +       struct acpi_iort_smmu_v3 *node_smmu_data;<br>&gt;&gt; +       int ret = 0;<br>&gt;&gt; +<br>&gt;&gt; +       if (pdev-&gt;type == DEV_ACPI) {<br>&gt;&gt; +               iort_node = pdev-&gt;acpi_node;<br>&gt;&gt; +               node_smmu_data = (struct acpi_iort_smmu_v3<br>&gt;&gt; *)iort_node-&gt;node_data;<br>&gt;&gt; +<br>&gt;&gt; +               if (node_smmu_data != NULL) {<br>&gt;&gt; +                       if (!strcmp(name, &quot;eventq&quot;))<br>&gt;&gt; +                               ret = node_smmu_data-&gt;event_gsiv;<br>&gt;&gt; +                       else if (!strcmp(name, &quot;priq&quot;))<br>&gt;&gt; +                               ret = node_smmu_data-&gt;pri_gsiv;<br>&gt;&gt; +                       else if (!strcmp(name, &quot;cmdq-sync&quot;))<br>&gt;&gt; +                               ret = node_smmu_data-&gt;sync_gsiv;<br>&gt;&gt; +                       else if (!strcmp(name, &quot;gerror&quot;))<br>&gt;&gt; +                               ret = node_smmu_data-&gt;gerr_gsiv;<br>&gt;&gt; +                       else<br>&gt;&gt; +                               ret = -EINVAL;<br>&gt;&gt; +               }<br>&gt;&gt; +       } else {<br>&gt;&gt; +               dtprop = dt_find_property(dev_to_dt(pdev),<br>&gt;&gt; &quot;interrupt-names&quot;, NULL);<br>&gt;&gt; +               if (!dtprop)<br>&gt;&gt; +                       return -EINVAL;<br>&gt;&gt; +<br>&gt;&gt; +               if (!dtprop-&gt;value)<br>&gt;&gt; +                       return -ENODATA;<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +       return ret;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +/*<br>&gt;&gt; + * Xen: Helpers for DMA allocation. Just the function name is reused for<br>&gt;&gt; + * porting code these allocation are not managed allocations<br>&gt;&gt;    */<br>&gt;&gt;   -#include &lt;linux/acpi.h&gt;<br>&gt;&gt; -#include &lt;linux/acpi_iort.h&gt;<br>&gt;&gt; -#include &lt;linux/delay.h&gt;<br>&gt;&gt; -#include &lt;linux/dma-iommu.h&gt;<br>&gt;&gt; -#include &lt;linux/err.h&gt;<br>&gt;&gt; -#include &lt;linux/interrupt.h&gt;<br>&gt;&gt; -#include &lt;linux/iommu.h&gt;<br>&gt;&gt; -#include &lt;linux/iopoll.h&gt;<br>&gt;&gt; -#include &lt;linux/module.h&gt;<br>&gt;&gt; -#include &lt;linux/msi.h&gt;<br>&gt;&gt; -#include &lt;linux/of.h&gt;<br>&gt;&gt; -#include &lt;linux/of_address.h&gt;<br>&gt;&gt; -#include &lt;linux/of_iommu.h&gt;<br>&gt;&gt; -#include &lt;linux/of_platform.h&gt;<br>&gt;&gt; -#include &lt;linux/pci.h&gt;<br>&gt;&gt; -#include &lt;linux/platform_device.h&gt;<br>&gt;&gt; -<br>&gt;&gt; -#include &lt;linux/amba/bus.h&gt;<br>&gt;&gt; -<br>&gt;&gt; -#include &quot;io-pgtable.h&quot;<br>&gt;&gt; +static void *dmam_alloc_coherent(struct device *dev, size_t size,<br>&gt;&gt; +                          dma_addr_t *dma_handle, gfp_t gfp)<br>&gt;&gt; +{<br>&gt;&gt; +       void *vaddr;<br>&gt;&gt; +       unsigned long alignment = size;<br>&gt;&gt; +<br>&gt;&gt; +       /*<br>&gt;&gt; +        * _xzalloc requires that the (align &amp; (align -1)) = 0. Most of<br>&gt;&gt; the<br>&gt;&gt; +        * allocations in SMMU code should send the right value for size.<br>&gt;&gt; In<br>&gt;&gt; +        * case this is not true print a warning and align to the size of<br>&gt;&gt; a<br>&gt;&gt; +        * (void *)<br>&gt;&gt; +        */<br>&gt;&gt; +       if (size &amp; (size - 1)) {<br>&gt;&gt; +               dev_warn(dev, &quot;Fixing alignment for the DMA buffer\n&quot;);<br>&gt;&gt; +               alignment = sizeof(void *);<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +       vaddr = _xzalloc(size, alignment);<br>&gt;&gt; +       if (!vaddr) {<br>&gt;&gt; +               dev_err(dev, &quot;DMA allocation failed\n&quot;);<br>&gt;&gt; +               return NULL;<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +       *dma_handle = virt_to_maddr(vaddr);<br>&gt;&gt; +<br>&gt;&gt; +       return vaddr;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +<br>&gt;&gt; +static void dmam_free_coherent(struct device *dev, size_t size, void<br>&gt;&gt; *vaddr,<br>&gt;&gt; +                       dma_addr_t dma_handle)<br>&gt;&gt; +{<br>&gt;&gt; +       xfree(vaddr);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +/* Xen: Stub out DMA domain related functions */<br>&gt;&gt; +#define iommu_get_dma_cookie(dom) 0<br>&gt;&gt; +#define iommu_put_dma_cookie(dom)<br>&gt;&gt; +<br>&gt;&gt; +/* Xen: Stub out module param related function */<br>&gt;&gt; +#define module_param_named(a, b, c, d)<br>&gt;&gt; +#define MODULE_PARM_DESC(a, b)<br>&gt;&gt; +<br>&gt;&gt; +#define dma_set_mask_and_coherent(d, b) 0<br>&gt;&gt; +<br>&gt;&gt; +#define of_dma_is_coherent(n) 0<br>&gt;&gt; +<br>&gt;&gt; +#define MODULE_DEVICE_TABLE(type, name)<br>&gt;&gt; +<br>&gt;&gt; +static void __iomem *devm_ioremap_resource(struct device *dev,<br>&gt;&gt; +                                          struct resource *res)<br>&gt;&gt; +{<br>&gt;&gt; +       void __iomem *ptr;<br>&gt;&gt; +<br>&gt;&gt; +       if (!res || res-&gt;type != IORESOURCE_MEM) {<br>&gt;&gt; +               dev_err(dev, &quot;Invalid resource\n&quot;);<br>&gt;&gt; +               return ERR_PTR(-EINVAL);<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +       ptr = ioremap_nocache(res-&gt;addr, res-&gt;size);<br>&gt;&gt; +       if (!ptr) {<br>&gt;&gt; +               dev_err(dev,<br>&gt;&gt; +                       &quot;ioremap failed (addr 0x%&quot;PRIx64&quot; size<br>&gt;&gt; 0x%&quot;PRIx64&quot;)\n&quot;,<br>&gt;&gt; +                       res-&gt;addr, res-&gt;size);<br>&gt;&gt; +               return ERR_PTR(-ENOMEM);<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +       return ptr;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +/* Xen: Compatibility define for iommu_domain_geometry.*/<br>&gt;&gt; +struct iommu_domain_geometry {<br>&gt;&gt; +       dma_addr_t aperture_start; /* First address that can be mapped  <br>&gt;&gt; */<br>&gt;&gt; +       dma_addr_t aperture_end;   /* Last address that can be mapped    <br>&gt;&gt; */<br>&gt;&gt; +       bool force_aperture;       /* DMA only allowed in mappable range?<br>&gt;&gt; */<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +<br>&gt;&gt; +/* Xen: Type definitions for iommu_domain */<br>&gt;&gt; +#define IOMMU_DOMAIN_UNMANAGED 0<br>&gt;&gt; +#define IOMMU_DOMAIN_DMA 1<br>&gt;&gt; +#define IOMMU_DOMAIN_IDENTITY 2<br>&gt;&gt; +<br>&gt;&gt; +/* Xen: Dummy iommu_domain */<br>&gt;&gt; +struct iommu_domain {<br>&gt;&gt; +       /* Runtime SMMU configuration for this iommu_domain */<br>&gt;&gt; +       struct arm_smmu_domain          *priv;<br>&gt;&gt; +       unsigned int type;<br>&gt;&gt; +<br>&gt;&gt; +       /* Dummy compatibility defines */<br>&gt;&gt; +       unsigned long pgsize_bitmap;<br>&gt;&gt; +       struct iommu_domain_geometry geometry;<br>&gt;&gt; +<br>&gt;&gt; +       atomic_t ref;<br>&gt;&gt; +       /*<br>&gt;&gt; +        * Used to link iommu_domain contexts for a same domain.<br>&gt;&gt; +        * There is at least one per-SMMU to used by the domain.<br>&gt;&gt; +        */<br>&gt;&gt; +       struct list_head                list;<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +/* Xen: Describes information required for a Xen domain */<br>&gt;&gt; +struct arm_smmu_xen_domain {<br>&gt;&gt; +       spinlock_t                      lock;<br>&gt;&gt; +       /* List of iommu domains associated to this domain */<br>&gt;&gt; +       struct list_head                contexts;<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +/*<br>&gt;&gt; + * Xen: Information about each device stored in dev-&gt;archdata.iommu<br>&gt;&gt; + *<br>&gt;&gt; + * The dev-&gt;archdata.iommu stores the iommu_domain (runtime configuration<br>&gt;&gt; of<br>&gt;&gt; + * the SMMU).<br>&gt;&gt; + */<br>&gt;&gt; +struct arm_smmu_xen_device {<br>&gt;&gt; +       struct iommu_domain *domain;<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +/*<br>&gt;&gt; + * Xen: io_pgtable compatibility defines.<br>&gt;&gt; + * Most of these are to port in the S1 translation code as is.<br>&gt;&gt; + */<br>&gt;&gt; +struct io_pgtable_ops {<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +struct iommu_gather_ops {<br>&gt;&gt; +       void (*tlb_flush_all)(void *cookie);<br>&gt;&gt; +       void (*tlb_add_flush)(unsigned long iova, size_t size, size_t<br>&gt;&gt; granule,<br>&gt;&gt; +                             bool leaf, void *cookie);<br>&gt;&gt; +       void (*tlb_sync)(void *cookie);<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +struct io_pgtable_cfg {<br>&gt;&gt; +       /*<br>&gt;&gt; +        * IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE bits<br>&gt;&gt; in<br>&gt;&gt; +        *      stage 1 PTEs, for hardware which insists on validating<br>&gt;&gt; them<br>&gt;&gt; +        *      even in non-secure state where they should normally be<br>&gt;&gt; ignored.<br>&gt;&gt; +        *<br>&gt;&gt; +        * IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE<br>&gt;&gt; and<br>&gt;&gt; +        *      IOMMU_NOEXEC flags and map everything with full access,<br>&gt;&gt; for<br>&gt;&gt; +        *      hardware which does not implement the permissions of a<br>&gt;&gt; given<br>&gt;&gt; +        *      format, and/or requires some format-specific default<br>&gt;&gt; value.<br>&gt;&gt; +        *<br>&gt;&gt; +        * IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching<br>&gt;&gt; invalid<br>&gt;&gt; +        *      (unmapped) entries but the hardware might do so anyway,<br>&gt;&gt; perform<br>&gt;&gt; +        *      TLB maintenance when mapping as well as when unmapping.<br>&gt;&gt; +        *<br>&gt;&gt; +        * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all<br>&gt;&gt; +        *      PTEs, for Mediatek IOMMUs which treat it as a 33rd address<br>&gt;&gt; bit<br>&gt;&gt; +        *      when the SoC is in &quot;4GB mode&quot; and they can only access the<br>&gt;&gt; high<br>&gt;&gt; +        *      remap of DRAM (0x1_00000000 to 0x1_ffffffff).<br>&gt;&gt; +        *<br>&gt;&gt; +        * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only<br>&gt;&gt; ever<br>&gt;&gt; +        *      be accessed by a fully cache-coherent IOMMU or CPU (e.g.<br>&gt;&gt; for a<br>&gt;&gt; +        *      software-emulated IOMMU), such that pagetable updates need<br>&gt;&gt; not<br>&gt;&gt; +        *      be treated as explicit DMA data.<br>&gt;&gt; +        */<br>&gt;&gt; +       #define IO_PGTABLE_QUIRK_ARM_NS         BIT(0)<br>&gt;&gt; +       #define IO_PGTABLE_QUIRK_NO_PERMS       BIT(1)<br>&gt;&gt; +       #define IO_PGTABLE_QUIRK_TLBI_ON_MAP    BIT(2)<br>&gt;&gt; +       #define IO_PGTABLE_QUIRK_ARM_MTK_4GB    BIT(3)<br>&gt;&gt; +       #define IO_PGTABLE_QUIRK_NO_DMA         BIT(4)<br>&gt;&gt; +       unsigned long                   quirks;<br>&gt;&gt; +       unsigned long                   pgsize_bitmap;<br>&gt;&gt; +       unsigned int                    ias;<br>&gt;&gt; +       unsigned int                    oas;<br>&gt;&gt; +       const struct iommu_gather_ops   *tlb;<br>&gt;&gt; +       struct device                   *iommu_dev;<br>&gt;&gt; +<br>&gt;&gt; +       /* Low-level data specific to the table format */<br>&gt;&gt; +       union {<br>&gt;&gt; +               struct {<br>&gt;&gt; +                       u64     ttbr[2];<br>&gt;&gt; +                       u64     tcr;<br>&gt;&gt; +                       u64     mair[2];<br>&gt;&gt; +               } arm_lpae_s1_cfg;<br>&gt;&gt; +<br>&gt;&gt; +               struct {<br>&gt;&gt; +                       u64     vttbr;<br>&gt;&gt; +                       u64     vtcr;<br>&gt;&gt; +               } arm_lpae_s2_cfg;<br>&gt;&gt; +<br>&gt;&gt; +               struct {<br>&gt;&gt; +                       u32     ttbr[2];<br>&gt;&gt; +                       u32     tcr;<br>&gt;&gt; +                       u32     nmrr;<br>&gt;&gt; +                       u32     prrr;<br>&gt;&gt; +               } arm_v7s_cfg;<br>&gt;&gt; +       };<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +enum io_pgtable_fmt {<br>&gt;&gt; +       ARM_32_LPAE_S1,<br>&gt;&gt; +       ARM_32_LPAE_S2,<br>&gt;&gt; +       ARM_64_LPAE_S1,<br>&gt;&gt; +       ARM_64_LPAE_S2,<br>&gt;&gt; +       ARM_V7S,<br>&gt;&gt; +       IO_PGTABLE_NUM_FMTS,<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +/*<br>&gt;&gt; + * Xen: The pgtable_ops are used by the S1 translations, so return the<br>&gt;&gt; dummy<br>&gt;&gt; + * address.<br>&gt;&gt; + */<br>&gt;&gt; +#define alloc_io_pgtable_ops(f, c, o) ((struct io_pgtable_ops *)0x0)<br>&gt;<br>&gt; Is this correct? it will make the caller null check fail<br>In your earlier patch it was<br><br>#define alloc_io_pgtable_ops(f, c, o) ((struct io_pgtable_ops *)0xDEADBEEF)<br><br>&gt;<br>&gt;&gt; +#define free_io_pgtable_ops(o)<br>&gt;&gt; +<br>&gt;&gt; +/* Xen: Define wrapper for requesting IRQs */<br>&gt;&gt; +#define IRQF_ONESHOT 0<br>&gt;&gt; +<br>&gt;&gt; +typedef void (*irq_handler_t)(int, void *, struct cpu_user_regs *);<br>&gt;&gt; +<br>&gt;&gt; +static inline int devm_request_irq(struct device *dev, unsigned int irq,<br>&gt;&gt; +                                  irq_handler_t handler, unsigned long<br>&gt;&gt; irqflags,<br>&gt;&gt; +                                  const char *devname, void *dev_id)<br>&gt;&gt; +{<br>&gt;&gt; +       /*<br>&gt;&gt; +        * SMMUv3 implementation can support wired interrupt outputs that<br>&gt;&gt; are<br>&gt;&gt; +        * edge-triggered. Set the irq type as per the spec.<br>&gt;&gt; +        */<br>&gt;&gt; +       irq_set_type(irq, IRQ_TYPE_EDGE_BOTH);<br>&gt;&gt; +       return request_irq(irq, irqflags, handler, devname, dev_id);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +/*<br>&gt;&gt; + * Xen does not have a concept of threaded irq, but eventually we can use<br>&gt;&gt; + * tasklets to optimize the following function.<br>&gt;&gt; + */<br>&gt;&gt; +int devm_request_threaded_irq(struct device *dev, unsigned int irq,<br>&gt;&gt; irq_handler_t handler,<br>&gt;&gt; +                             irq_handler_t thread_fn, unsigned long<br>&gt;&gt; irqflags,<br>&gt;&gt; +                             const char *devname, void *dev_id)<br>&gt;&gt; +{<br>&gt;&gt; +       return devm_request_irq(dev, irq, thread_fn, irqflags, devname,<br>&gt;&gt; dev_id);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +/* Xen: The mutex is used only during initialization so the typecast is<br>&gt;&gt; safe */<br>&gt;&gt; +#define mutex spinlock<br>&gt;&gt; +#define mutex_init spin_lock_init<br>&gt;&gt; +#define mutex_lock spin_lock<br>&gt;&gt; +#define mutex_unlock spin_unlock<br>&gt;&gt; +<br>&gt;&gt; +#define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \<br>&gt;&gt; +({ \<br>&gt;&gt; +       s_time_t deadline = NOW() + MICROSECS(timeout_us); \<br>&gt;&gt; +       for (;;) { \<br>&gt;&gt; +               (val) = op(addr); \<br>&gt;&gt; +               if (cond) \<br>&gt;&gt; +                       break; \<br>&gt;&gt; +               if (NOW() &gt; deadline) { \<br>&gt;&gt; +                       (val) = op(addr); \<br>&gt;&gt; +                       break; \<br>&gt;&gt; +               } \<br>&gt;&gt; +       udelay(sleep_us); \<br>&gt;&gt; +       } \<br>&gt;&gt; +       (cond) ? 0 : -ETIMEDOUT; \<br>&gt;&gt; +})<br>&gt;&gt; +<br>&gt;&gt; +#define readl_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us)<br>&gt;&gt; \<br>&gt;&gt; +       readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us,<br>&gt;&gt; timeout_us)<br>&gt;&gt; +<br>&gt;&gt; +#define VA_BITS 0 /* Only needed for S1 translations */<br>&gt;&gt;     /* MMIO registers */<br>&gt;&gt;   #define ARM_SMMU_IDR0                 0x0<br>&gt;&gt; @@ -433,6 +819,7 @@ enum pri_resp {<br>&gt;&gt;         PRI_RESP_SUCC,<br>&gt;&gt;   };<br>&gt;&gt;   +#if 0 /* Xen: No MSI support in this iteration */<br>&gt;&gt;   enum arm_smmu_msi_index {<br>&gt;&gt;         EVTQ_MSI_INDEX,<br>&gt;&gt;         GERROR_MSI_INDEX,<br>&gt;&gt; @@ -457,6 +844,7 @@ static phys_addr_t<br>&gt;&gt; arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {<br>&gt;&gt;                 ARM_SMMU_PRIQ_IRQ_CFG2,<br>&gt;&gt;         },<br>&gt;&gt;   };<br>&gt;&gt; +#endif<br>&gt;&gt;     struct arm_smmu_cmdq_ent {<br>&gt;&gt;         /* Common fields */<br>&gt;&gt; @@ -561,6 +949,8 @@ struct arm_smmu_s2_cfg {<br>&gt;&gt;         u16                             vmid;<br>&gt;&gt;         u64                             vttbr;<br>&gt;&gt;         u64                             vtcr;<br>&gt;&gt; +       /* Xen: Domain associated to this configuration */<br>&gt;&gt; +       struct domain                   *domain;<br>&gt;&gt;   };<br>&gt;&gt;     struct arm_smmu_strtab_ent {<br>&gt;&gt; @@ -635,9 +1025,21 @@ struct arm_smmu_device {<br>&gt;&gt;         struct arm_smmu_strtab_cfg      strtab_cfg;<br>&gt;&gt;         /* IOMMU core code handle */<br>&gt;&gt; +#if 0 /*Xen: Generic iommu_device ref not needed here */<br>&gt;&gt;         struct iommu_device             iommu;<br>&gt;&gt; +#endif<br>&gt;&gt; +       /* Xen: Need to keep a list of SMMU devices */<br>&gt;&gt; +       struct list_head                devices;<br>&gt;&gt;   };<br>&gt;&gt;   +/* Xen: Keep a list of devices associated with this driver */<br>&gt;&gt; +static DEFINE_SPINLOCK(arm_smmu_devices_lock);<br>&gt;&gt; +static LIST_HEAD(arm_smmu_devices);<br>&gt;&gt; +/* Xen: Helper for finding a device using fwnode */<br>&gt;&gt; +static<br>&gt;&gt; +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle<br>&gt;&gt; *fwnode);<br>&gt;&gt; +<br>&gt;&gt; +<br>&gt;&gt;   /* SMMU private data for each master */<br>&gt;&gt;   struct arm_smmu_master_data {<br>&gt;&gt;         struct arm_smmu_device          *smmu;<br>&gt;&gt; @@ -1232,7 +1634,7 @@ static void arm_smmu_handle_ppr(struct<br>&gt;&gt; arm_smmu_device *smmu, u64 *evt)<br>&gt;&gt;         dev_info(smmu-&gt;dev, &quot;unexpected PRI request received:\n&quot;);<br>&gt;&gt;         dev_info(smmu-&gt;dev,<br>&gt;&gt; -                &quot;\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access<br>&gt;&gt; at iova 0x%016llx\n&quot;,<br>&gt;&gt; +                &quot;\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access<br>&gt;&gt; at iova %#&quot; PRIx64 &quot;\n&quot;,<br>&gt;&gt;                  sid, ssid, grpid, last ? &quot;L&quot; : &quot;&quot;,<br>&gt;&gt;                  evt[0] &amp; PRIQ_0_PERM_PRIV ? &quot;&quot; : &quot;un&quot;,<br>&gt;&gt;                  evt[0] &amp; PRIQ_0_PERM_READ ? &quot;R&quot; : &quot;&quot;,<br>&gt;&gt; @@ -1346,6 +1748,8 @@ static irqreturn_t arm_smmu_combined_irq_handler(int<br>&gt;&gt; irq, void *dev)<br>&gt;&gt;   {<br>&gt;&gt;         arm_smmu_gerror_handler(irq, dev);<br>&gt;&gt;         arm_smmu_cmdq_sync_handler(irq, dev);<br>&gt;&gt; +       /*Xen: No threaded irq. So call the required function from here */<br>&gt;&gt; +       arm_smmu_combined_irq_thread(irq, dev);<br>&gt;&gt;         return IRQ_WAKE_THREAD;<br>&gt;&gt;   }<br>&gt;&gt;   @@ -1358,6 +1762,46 @@ static void __arm_smmu_tlb_sync(struct<br>&gt;&gt; arm_smmu_device *smmu)<br>&gt;&gt;         arm_smmu_cmdq_issue_cmd(smmu, &amp;cmd);<br>&gt;&gt;   }<br>&gt;&gt;   +/*<br>&gt;&gt; + * Xen: Define the IRQ handlers for xen. The linux functions would be<br>&gt;&gt; + * modified to use the functions defined in the following code.<br>&gt;&gt; + */<br>&gt;&gt; +static void arm_smmu_evtq_thread_xen(int irq, void *dev,<br>&gt;&gt; +                                      struct cpu_user_regs *regs)<br>&gt;&gt; +{<br>&gt;&gt; +       arm_smmu_evtq_thread(irq, dev);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static void arm_smmu_priq_thread_xen(int irq, void *dev,<br>&gt;&gt; +                                      struct cpu_user_regs *regs)<br>&gt;&gt; +{<br>&gt;&gt; +       arm_smmu_priq_thread(irq, dev);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static void arm_smmu_cmdq_sync_handler_xen(int irq, void *dev,<br>&gt;&gt; +                                      struct cpu_user_regs *regs)<br>&gt;&gt; +{<br>&gt;&gt; +       arm_smmu_cmdq_sync_handler(irq, dev);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static void arm_smmu_gerror_handler_xen(int irq, void *dev,<br>&gt;&gt; +                                      struct cpu_user_regs *regs)<br>&gt;&gt; +{<br>&gt;&gt; +       arm_smmu_gerror_handler(irq, dev);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static void arm_smmu_combined_irq_handler_xen(int irq, void *dev,<br>&gt;&gt; +                                      struct cpu_user_regs *regs)<br>&gt;&gt; +{<br>&gt;&gt; +       arm_smmu_combined_irq_handler(irq, dev);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +#define arm_smmu_evtq_thread arm_smmu_evtq_thread_xen<br>&gt;&gt; +#define arm_smmu_priq_thread arm_smmu_priq_thread_xen<br>&gt;&gt; +#define arm_smmu_cmdq_sync_handler arm_smmu_cmdq_sync_handler_xen<br>&gt;&gt; +#define arm_smmu_gerror_handler arm_smmu_gerror_handler_xen<br>&gt;&gt; +#define arm_smmu_combined_irq_handler arm_smmu_combined_irq_handler_xen<br>&gt;&gt; +<br>&gt;&gt;   static void arm_smmu_tlb_sync(void *cookie)<br>&gt;&gt;   {<br>&gt;&gt;         struct arm_smmu_domain *smmu_domain = cookie;<br>&gt;&gt; @@ -1415,6 +1859,7 @@ static const struct iommu_gather_ops<br>&gt;&gt; arm_smmu_gather_ops = {<br>&gt;&gt;         .tlb_sync       = arm_smmu_tlb_sync,<br>&gt;&gt;   };<br>&gt;&gt;   +#if 0 /*Xen: Unused functionality */<br>&gt;&gt;   /* IOMMU API */<br>&gt;&gt;   static bool arm_smmu_capable(enum iommu_cap cap)<br>&gt;&gt;   {<br>&gt;&gt; @@ -1427,6 +1872,7 @@ static bool arm_smmu_capable(enum iommu_cap cap)<br>&gt;&gt;                 return false;<br>&gt;&gt;         }<br>&gt;&gt;   }<br>&gt;&gt; +#endif<br>&gt;&gt;     static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)<br>&gt;&gt;   {<br>&gt;&gt; @@ -1546,9 +1992,16 @@ static int arm_smmu_domain_finalise_s2(struct<br>&gt;&gt; arm_smmu_domain *smmu_domain,<br>&gt;&gt;         if (vmid &lt; 0)<br>&gt;&gt;                 return vmid;<br>&gt;&gt;   -     cfg-&gt;vmid       = (u16)vmid;<br>&gt;&gt; -       cfg-&gt;vttbr      = pgtbl_cfg-&gt;arm_lpae_s2_cfg.vttbr;<br>&gt;&gt; -       cfg-&gt;vtcr       = pgtbl_cfg-&gt;arm_lpae_s2_cfg.vtcr;<br>&gt;&gt; +       /*<br>&gt;&gt; +        * Xen: Get the ttbr and vtcr values<br>&gt;&gt; +        * vttbr: This is a shared value with the domain page table<br>&gt;&gt; +        * vtcr: The TCR settings are the same as CPU since the page<br>&gt;&gt; +        * tables are shared<br>&gt;&gt; +        */<br>&gt;&gt; +<br>&gt;&gt; +       cfg-&gt;vmid       = vmid;<br>&gt;&gt; +       cfg-&gt;vttbr      = page_to_maddr(cfg-&gt;domain-&gt;arch.p2m.root);<br>&gt;&gt; +       cfg-&gt;vtcr       = READ_SYSREG32(VTCR_EL2) &amp;<br>&gt;&gt; STRTAB_STE_2_VTCR_MASK;<br>&gt;&gt;         return 0;<br>&gt;&gt;   }<br>&gt;&gt;   @@ -1604,6 +2057,7 @@ static int arm_smmu_domain_finalise(struct<br>&gt;&gt; iommu_domain *domain)<br>&gt;&gt;         if (smmu-&gt;features &amp; ARM_SMMU_FEAT_COHERENCY)<br>&gt;&gt;                 pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_NO_DMA;<br>&gt;&gt;   +     /* Xen: pgtbl_ops gets an invalid address */<br>&gt;&gt;         pgtbl_ops = alloc_io_pgtable_ops(fmt, &amp;pgtbl_cfg, smmu_domain);<br>&gt;&gt;         if (!pgtbl_ops)<br>&gt;&gt;                 return -ENOMEM;<br>&gt;<br>&gt; Will this not fail ?<br>&gt;<br>&gt;&gt; @@ -1721,6 +2175,7 @@ out_unlock:<br>&gt;&gt;         return ret;<br>&gt;&gt;   }<br>&gt;&gt;   +#if 0 /* Xen: Unused functionality */<br>&gt;&gt;   static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,<br>&gt;&gt;                         phys_addr_t paddr, size_t size, int prot)<br>&gt;&gt;   {<br>&gt;&gt; @@ -1772,6 +2227,7 @@ struct arm_smmu_device<br>&gt;&gt; *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)<br>&gt;&gt;         put_device(dev);<br>&gt;&gt;         return dev ? dev_get_drvdata(dev) : NULL;<br>&gt;&gt;   }<br>&gt;&gt; +#endif<br>&gt;&gt;     static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32<br>&gt;&gt; sid)<br>&gt;&gt;   {<br>&gt;&gt; @@ -1783,7 +2239,14 @@ static bool arm_smmu_sid_in_range(struct<br>&gt;&gt; arm_smmu_device *smmu, u32 sid)<br>&gt;&gt;         return sid &lt; limit;<br>&gt;&gt;   }<br>&gt;&gt;   +/* Xen: Unused */<br>&gt;&gt; +#if 0<br>&gt;&gt;   static struct iommu_ops arm_smmu_ops;<br>&gt;&gt; +#endif<br>&gt;&gt; +<br>&gt;&gt; +/* Xen: Redefine arm_smmu_ops to what fwspec should evaluate */<br>&gt;&gt; +static const struct iommu_ops arm_smmu_iommu_ops;<br>&gt;&gt; +#define arm_smmu_ops arm_smmu_iommu_ops<br>&gt;&gt;     static int arm_smmu_add_device(struct device *dev)<br>&gt;&gt;   {<br>&gt;&gt; @@ -1791,8 +2254,11 @@ static int arm_smmu_add_device(struct device *dev)<br>&gt;&gt;         struct arm_smmu_device *smmu;<br>&gt;&gt;         struct arm_smmu_master_data *master;<br>&gt;&gt;         struct iommu_fwspec *fwspec = dev-&gt;iommu_fwspec;<br>&gt;&gt; +#if 0 /*Xen: iommu_group is not needed */<br>&gt;&gt;         struct iommu_group *group;<br>&gt;&gt; +#endif<br>&gt;&gt;   +     /* Xen: fwspec-&gt;ops are not needed */<br>&gt;&gt;         if (!fwspec || fwspec-&gt;ops != &amp;arm_smmu_ops)<br>&gt;&gt;                 return -ENODEV;<br>&gt;&gt;         /*<br>&gt;&gt; @@ -1830,6 +2296,11 @@ static int arm_smmu_add_device(struct device *dev)<br>&gt;&gt;                 }<br>&gt;&gt;         }<br>&gt;&gt;   +/*<br>&gt;&gt; + * Xen: Do not need an iommu group as the stream data is carried by the<br>&gt;&gt; SMMU<br>&gt;&gt; + * master device object<br>&gt;&gt; + */<br>&gt;&gt; +#if 0<br>&gt;&gt;         group = iommu_group_get_for_dev(dev);<br>&gt;&gt;         if (!IS_ERR(group)) {<br>&gt;&gt;                 iommu_group_put(group);<br>&gt;&gt; @@ -1837,8 +2308,16 @@ static int arm_smmu_add_device(struct device *dev)<br>&gt;&gt;         }<br>&gt;&gt;         return PTR_ERR_OR_ZERO(group);<br>&gt;&gt; +#endif<br>&gt;&gt; +       return 0;<br>&gt;&gt;   }<br>&gt;&gt;   +/*<br>&gt;&gt; + * Xen: We can potentially support this function and destroy a device.<br>&gt;&gt; This<br>&gt;&gt; + * will be relevant for PCI hotplug. So, will be implemented as needed<br>&gt;&gt; after<br>&gt;&gt; + * passthrough support is available.<br>&gt;&gt; + */<br>&gt;&gt; +#if 0<br>&gt;&gt;   static void arm_smmu_remove_device(struct device *dev)<br>&gt;&gt;   {<br>&gt;&gt;         struct iommu_fwspec *fwspec = dev-&gt;iommu_fwspec;<br>&gt;&gt; @@ -1974,6 +2453,7 @@ static struct iommu_ops arm_smmu_ops = {<br>&gt;&gt;         .put_resv_regions       = arm_smmu_put_resv_regions,<br>&gt;&gt;         .pgsize_bitmap          = -1UL, /* Restricted during device attach<br>&gt;&gt; */<br>&gt;&gt;   };<br>&gt;&gt; +#endif<br>&gt;&gt;     /* Probing and initialisation functions */<br>&gt;&gt;   static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,<br>&gt;&gt; @@ -2182,6 +2662,7 @@ static int arm_smmu_update_gbpa(struct<br>&gt;&gt; arm_smmu_device *smmu, u32 set, u32 clr)<br>&gt;&gt;                                           1, ARM_SMMU_POLL_TIMEOUT_US);<br>&gt;&gt;   }<br>&gt;&gt;   +#if 0 /* Xen: There is no MSI support as yet */<br>&gt;&gt;   static void arm_smmu_free_msis(void *data)<br>&gt;&gt;   {<br>&gt;&gt;         struct device *dev = data;<br>&gt;&gt; @@ -2247,12 +2728,15 @@ static void arm_smmu_setup_msis(struct<br>&gt;&gt; arm_smmu_device *smmu)<br>&gt;&gt;         /* Add callback to free MSIs on teardown */<br>&gt;&gt;         devm_add_action(dev, arm_smmu_free_msis, dev);<br>&gt;&gt;   }<br>&gt;&gt; +#endif<br>&gt;&gt;     static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)<br>&gt;&gt;   {<br>&gt;&gt;         int irq, ret;<br>&gt;&gt;   +#if 0 /*Xen: Cannot setup msis for now */<br>&gt;&gt;         arm_smmu_setup_msis(smmu);<br>&gt;&gt; +#endif<br>&gt;&gt;         /* Request interrupt lines */<br>&gt;&gt;         irq = smmu-&gt;evtq.q.irq;<br>&gt;&gt; @@ -2316,9 +2800,13 @@ static int arm_smmu_setup_irqs(struct<br>&gt;&gt; arm_smmu_device *smmu)<br>&gt;&gt;                  * Cavium ThunderX2 implementation doesn&#39;t not support<br>&gt;&gt; unique<br>&gt;&gt;                  * irq lines. Use single irq line for all the SMMUv3<br>&gt;&gt; interrupts.<br>&gt;&gt;                  */<br>&gt;&gt; -               ret = devm_request_threaded_irq(smmu-&gt;dev, irq,<br>&gt;&gt; +               /*<br>&gt;&gt; +                * Xen: Does not support threaded irqs, so serialise the<br>&gt;&gt; setup.<br>&gt;&gt; +                * This is the same for pris and event interrupt lines on<br>&gt;&gt; other<br>&gt;&gt; +                * systems<br>&gt;&gt; +                */<br>&gt;&gt; +               ret = devm_request_irq(smmu-&gt;dev, irq,<br>&gt;&gt;                                         arm_smmu_combined_irq_handler,<br>&gt;&gt; -                                       arm_smmu_combined_irq_thread,<br>&gt;&gt;                                         IRQF_ONESHOT,<br>&gt;&gt;                                         &quot;arm-smmu-v3-combined-irq&quot;, smmu);<br>&gt;&gt;                 if (ret &lt; 0)<br>&gt;&gt; @@ -2542,8 +3030,14 @@ static int arm_smmu_device_hw_probe(struct<br>&gt;&gt; arm_smmu_device *smmu)<br>&gt;&gt;                 smmu-&gt;features |= ARM_SMMU_FEAT_STALLS;<br>&gt;&gt;         }<br>&gt;&gt;   +/*<br>&gt;&gt; + * Xen: Block stage 1 translations. By doing this here we do not need to<br>&gt;&gt; set the<br>&gt;&gt; + * domain-&gt;stage explicitly.<br>&gt;&gt; + */<br>&gt;&gt; +#if 0<br>&gt;&gt;         if (reg &amp; IDR0_S1P)<br>&gt;&gt;                 smmu-&gt;features |= ARM_SMMU_FEAT_TRANS_S1;<br>&gt;&gt; +#endif<br>&gt;&gt;         if (reg &amp; IDR0_S2P)<br>&gt;&gt;                 smmu-&gt;features |= ARM_SMMU_FEAT_TRANS_S2;<br>&gt;&gt; @@ -2616,10 +3110,12 @@ static int arm_smmu_device_hw_probe(struct<br>&gt;&gt; arm_smmu_device *smmu)<br>&gt;&gt;         if (reg &amp; IDR5_GRAN4K)<br>&gt;&gt;                 smmu-&gt;pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;<br>&gt;&gt;   +#if 0 /* Xen: SMMU ops do not have a pgsize_bitmap member for Xen */<br>&gt;&gt;         if (arm_smmu_ops.pgsize_bitmap == -1UL)<br>&gt;&gt;                 arm_smmu_ops.pgsize_bitmap = smmu-&gt;pgsize_bitmap;<br>&gt;&gt;         else<br>&gt;&gt;                 arm_smmu_ops.pgsize_bitmap |= smmu-&gt;pgsize_bitmap;<br>&gt;&gt; +#endif<br>&gt;&gt;         /* Output address size */<br>&gt;&gt;         switch (reg &amp; IDR5_OAS_MASK &lt;&lt; IDR5_OAS_SHIFT) {<br>&gt;&gt; @@ -2680,7 +3176,8 @@ static int arm_smmu_device_acpi_probe(struct<br>&gt;&gt; platform_device *pdev,<br>&gt;&gt;         struct device *dev = smmu-&gt;dev;<br>&gt;&gt;         struct acpi_iort_node *node;<br>&gt;&gt;   -     node = *(struct acpi_iort_node **)dev_get_platdata(dev);<br>&gt;&gt; +       /* Xen: Modification to get iort_node */<br>&gt;&gt; +       node = (struct acpi_iort_node *)dev-&gt;acpi_node;<br>&gt;&gt;         /* Retrieve SMMUv3 specific data */<br>&gt;&gt;         iort_smmu = (struct acpi_iort_smmu_v3 *)node-&gt;node_data;<br>&gt;&gt; @@ -2703,7 +3200,7 @@ static inline int arm_smmu_device_acpi_probe(struct<br>&gt;&gt; platform_device *pdev,<br>&gt;&gt;   static int arm_smmu_device_dt_probe(struct platform_device *pdev,<br>&gt;&gt;                                     struct arm_smmu_device *smmu)<br>&gt;&gt;   {<br>&gt;&gt; -       struct device *dev = &amp;pdev-&gt;dev;<br>&gt;&gt; +       struct device *dev = pdev;<br>&gt;&gt;         u32 cells;<br>&gt;&gt;         int ret = -EINVAL;<br>&gt;&gt;   @@ -2716,6 +3213,7 @@ static int arm_smmu_device_dt_probe(struct<br>&gt;&gt; platform_device *pdev,<br>&gt;&gt;         parse_driver_options(smmu);<br>&gt;&gt;   +     /* Xen: of_dma_is_coherent is a stub till dt support is introduced<br>&gt;&gt; */<br>&gt;&gt;         if (of_dma_is_coherent(dev-&gt;of_node))<br>&gt;&gt;                 smmu-&gt;features |= ARM_SMMU_FEAT_COHERENCY;<br>&gt;&gt;   @@ -2734,9 +3232,11 @@ static int arm_smmu_device_probe(struct<br>&gt;&gt; platform_device *pdev)<br>&gt;&gt;   {<br>&gt;&gt;         int irq, ret;<br>&gt;&gt;         struct resource *res;<br>&gt;&gt; +#if 0 /*Xen: Do not need to setup sysfs */<br>&gt;&gt;         resource_size_t ioaddr;<br>&gt;&gt; +#endif<br>&gt;&gt;         struct arm_smmu_device *smmu;<br>&gt;&gt; -       struct device *dev = &amp;pdev-&gt;dev;<br>&gt;&gt; +       struct device *dev = pdev;/* Xen: dev is ignored */<br>&gt;&gt;         bool bypass;<br>&gt;&gt;         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);<br>&gt;&gt; @@ -2763,7 +3263,9 @@ static int arm_smmu_device_probe(struct<br>&gt;&gt; platform_device *pdev)<br>&gt;&gt;                 dev_err(dev, &quot;MMIO region too small (%pr)\n&quot;, res);<br>&gt;&gt;                 return -EINVAL;<br>&gt;&gt;         }<br>&gt;&gt; +#if 0 /*Xen: Do not need to setup sysfs */<br>&gt;&gt;         ioaddr = res-&gt;start;<br>&gt;&gt; +#endif<br>&gt;&gt;         smmu-&gt;base = devm_ioremap_resource(dev, res);<br>&gt;&gt;         if (IS_ERR(smmu-&gt;base))<br>&gt;&gt; @@ -2802,13 +3304,18 @@ static int arm_smmu_device_probe(struct<br>&gt;&gt; platform_device *pdev)<br>&gt;&gt;                 return ret;<br>&gt;&gt;         /* Record our private device structure */<br>&gt;&gt; +       /* Xen: SMMU is not treated a a platform device*/<br>&gt;&gt; +#if 0<br>&gt;&gt;         platform_set_drvdata(pdev, smmu);<br>&gt;&gt; +#endif<br>&gt;&gt;         /* Reset the device */<br>&gt;&gt;         ret = arm_smmu_device_reset(smmu, bypass);<br>&gt;&gt;         if (ret)<br>&gt;&gt;                 return ret;<br>&gt;&gt;   +/* Xen: Not creating an IOMMU device list for Xen */<br>&gt;&gt; +#if 0<br>&gt;&gt;         /* And we&#39;re up. Go go go! */<br>&gt;&gt;         ret = iommu_device_sysfs_add(&amp;smmu-&gt;iommu, dev, NULL,<br>&gt;&gt;                                      &quot;smmu3.%pa&quot;, &amp;ioaddr);<br>&gt;&gt; @@ -2844,9 +3351,20 @@ static int arm_smmu_device_probe(struct<br>&gt;&gt; platform_device *pdev)<br>&gt;&gt;                 if (ret)<br>&gt;&gt;                         return ret;<br>&gt;&gt;         }<br>&gt;&gt; +#endif<br>&gt;&gt; +       /*<br>&gt;&gt; +        * Xen: Keep a list of all probed devices. This will be used to<br>&gt;&gt; query<br>&gt;&gt; +        * the smmu devices based on the fwnode.<br>&gt;&gt; +        */<br>&gt;&gt; +       INIT_LIST_HEAD(&amp;smmu-&gt;devices);<br>&gt;&gt; +       spin_lock(&amp;arm_smmu_devices_lock);<br>&gt;&gt; +       list_add(&amp;smmu-&gt;devices, &amp;arm_smmu_devices);<br>&gt;&gt; +       spin_unlock(&amp;arm_smmu_devices_lock);<br>&gt;&gt;         return 0;<br>&gt;&gt;   }<br>&gt;&gt;   +/* Xen: Unused function */<br>&gt;&gt; +#if 0<br>&gt;&gt;   static int arm_smmu_device_remove(struct platform_device *pdev)<br>&gt;&gt;   {<br>&gt;&gt;         struct arm_smmu_device *smmu = platform_get_drvdata(pdev);<br>&gt;&gt; @@ -2860,6 +3378,8 @@ static void arm_smmu_device_shutdown(struct<br>&gt;&gt; platform_device *pdev)<br>&gt;&gt;   {<br>&gt;&gt;         arm_smmu_device_remove(pdev);<br>&gt;&gt;   }<br>&gt;&gt; +#endif<br>&gt;&gt; +<br>&gt;&gt;     static const struct of_device_id arm_smmu_of_match[] = {<br>&gt;&gt;         { .compatible = &quot;arm,smmu-v3&quot;, },<br>&gt;&gt; @@ -2867,6 +3387,7 @@ static const struct of_device_id arm_smmu_of_match[]<br>&gt;&gt; = {<br>&gt;&gt;   };<br>&gt;&gt;   MODULE_DEVICE_TABLE(of, arm_smmu_of_match);<br>&gt;&gt;   +#if 0<br>&gt;&gt;   static struct platform_driver arm_smmu_driver = {<br>&gt;&gt;         .driver = {<br>&gt;&gt;                 .name           = &quot;arm-smmu-v3&quot;,<br>&gt;&gt; @@ -2883,3 +3404,316 @@ IOMMU_OF_DECLARE(arm_smmuv3, &quot;arm,smmu-v3&quot;, NULL);<br>&gt;&gt;   MODULE_DESCRIPTION(&quot;IOMMU API for ARM architected SMMUv3<br>&gt;&gt; implementations&quot;);<br>&gt;&gt;   MODULE_AUTHOR(&quot;Will Deacon &lt;<a href="mailto:will.deacon@arm.com">will.deacon@arm.com</a>&gt;&quot;);<br>&gt;&gt;   MODULE_LICENSE(&quot;GPL v2&quot;);<br>&gt;&gt; +#endif<br>&gt;&gt; +<br>&gt;&gt; +/***** Start of Xen specific code *****/<br>&gt;&gt; +<br>&gt;&gt; +static int __must_check arm_smmu_iotlb_flush_all(struct domain *d)<br>&gt;&gt; +{<br>&gt;&gt; +       struct arm_smmu_xen_domain *smmu_domain = dom_iommu(d)-&gt;arch.priv;<br>&gt;&gt; +       struct iommu_domain *cfg;<br>&gt;&gt; +<br>&gt;&gt; +       spin_lock(&amp;smmu_domain-&gt;lock);<br>&gt;&gt; +       list_for_each_entry(cfg, &amp;smmu_domain-&gt;contexts, list) {<br>&gt;&gt; +               /*<br>&gt;&gt; +                * Only invalidate the context when SMMU is present.<br>&gt;&gt; +                * This is because the context initialization is delayed<br>&gt;&gt; +                * until a master has been added.<br>&gt;&gt; +                */<br>&gt;&gt; +               if (unlikely(!ACCESS_ONCE(cfg-&gt;priv-&gt;smmu)))<br>&gt;&gt; +                       continue;<br>&gt;&gt; +               arm_smmu_tlb_inv_context(cfg-&gt;priv);<br>&gt;&gt; +       }<br>&gt;&gt; +       spin_unlock(&amp;smmu_domain-&gt;lock);<br>&gt;&gt; +       return 0;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static int __must_check arm_smmu_iotlb_flush(struct domain *d,<br>&gt;&gt; +                                            unsigned long gfn,<br>&gt;&gt; +                                            unsigned int page_count)<br>&gt;&gt; +{<br>&gt;&gt; +       return arm_smmu_iotlb_flush_all(d);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static struct iommu_domain *arm_smmu_get_domain(struct domain *d,<br>&gt;&gt; +                                               struct device *dev)<br>&gt;&gt; +{<br>&gt;&gt; +       struct iommu_domain *domain;<br>&gt;&gt; +       struct arm_smmu_xen_domain *xen_domain;<br>&gt;&gt; +       struct arm_smmu_device *smmu;<br>&gt;&gt; +       struct arm_smmu_domain *smmu_domain;<br>&gt;&gt; +<br>&gt;&gt; +       xen_domain = dom_iommu(d)-&gt;arch.priv;<br>&gt;&gt; +<br>&gt;&gt; +       smmu = arm_smmu_get_by_fwnode(dev-&gt;iommu_fwspec-&gt;iommu_fwnode);<br>&gt;&gt; +       if (!smmu)<br>&gt;&gt; +               return NULL;<br>&gt;&gt; +<br>&gt;&gt; +       /*<br>&gt;&gt; +        * Loop through the &amp;xen_domain-&gt;contexts to locate a context<br>&gt;&gt; +        * assigned to this SMMU<br>&gt;&gt; +        */<br>&gt;&gt; +       list_for_each_entry(domain, &amp;xen_domain-&gt;contexts, list) {<br>&gt;&gt; +               smmu_domain = to_smmu_domain(domain);<br>&gt;&gt; +               if (smmu_domain-&gt;smmu == smmu)<br>&gt;&gt; +                       return domain;<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +       return NULL;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static void arm_smmu_destroy_iommu_domain(struct iommu_domain *domain)<br>&gt;&gt; +{<br>&gt;&gt; +       list_del(&amp;domain-&gt;list);<br>&gt;&gt; +       arm_smmu_domain_free(domain);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static int arm_smmu_assign_dev(struct domain *d, u8 devfn,<br>&gt;&gt; +                              struct device *dev, u32 flag)<br>&gt;&gt; +{<br>&gt;&gt; +       int ret = 0;<br>&gt;&gt; +       struct iommu_domain *domain;<br>&gt;&gt; +       struct arm_smmu_xen_domain *xen_domain;<br>&gt;&gt; +       struct arm_smmu_domain *arm_smmu;<br>&gt;&gt; +<br>&gt;&gt; +       xen_domain = dom_iommu(d)-&gt;arch.priv;<br>&gt;&gt; +<br>&gt;&gt; +       if (!dev-&gt;archdata.iommu) {<br>&gt;&gt; +               dev-&gt;archdata.iommu = xzalloc(struct arm_smmu_xen_device);<br>&gt;&gt; +               if (!dev-&gt;archdata.iommu)<br>&gt;&gt; +                       return -ENOMEM;<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +       ret = arm_smmu_add_device(dev);<br>&gt;&gt; +       if (ret)<br>&gt;&gt; +               return ret;<br>&gt;&gt; +<br>&gt;&gt; +       spin_lock(&amp;xen_domain-&gt;lock);<br>&gt;&gt; +<br>&gt;&gt; +       /*<br>&gt;&gt; +        * Check to see if an iommu_domain already exists for this xen<br>&gt;&gt; domain<br>&gt;&gt; +        * under the same SMMU<br>&gt;&gt; +        */<br>&gt;&gt; +       domain = arm_smmu_get_domain(d, dev);<br>&gt;&gt; +       if (!domain) {<br>&gt;&gt; +<br>&gt;&gt; +               domain = arm_smmu_domain_alloc(IOMMU_DOMAIN_DMA);<br>&gt;&gt; +               if (!domain) {<br>&gt;&gt; +                       ret = -ENOMEM;<br>&gt;&gt; +                       goto out;<br>&gt;&gt; +               }<br>&gt;&gt; +<br>&gt;&gt; +               arm_smmu = to_smmu_domain(domain);<br>&gt;&gt; +               arm_smmu-&gt;s2_cfg.domain = d;<br>&gt;&gt; +<br>&gt;&gt; +               /* Chain the new context to the domain */<br>&gt;&gt; +               list_add(&amp;domain-&gt;list, &amp;xen_domain-&gt;contexts);<br>&gt;&gt; +<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +       ret = arm_smmu_attach_dev(domain, dev);<br>&gt;&gt; +       if (ret) {<br>&gt;&gt; +               if (domain-&gt;ref.counter == 0)<br>&gt;&gt; +                       arm_smmu_destroy_iommu_domain(domain);<br>&gt;&gt; +       } else {<br>&gt;&gt; +               atomic_inc(&amp;domain-&gt;ref);<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +out:<br>&gt;&gt; +       spin_unlock(&amp;xen_domain-&gt;lock);<br>&gt;&gt; +       return ret;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static int arm_smmu_deassign_dev(struct domain *d, struct device *dev)<br>&gt;&gt; +{<br>&gt;&gt; +       struct iommu_domain *domain = arm_smmu_get_domain(d, dev);<br>&gt;&gt; +       struct arm_smmu_xen_domain *xen_domain;<br>&gt;&gt; +       struct arm_smmu_domain *arm_smmu = to_smmu_domain(domain);<br>&gt;&gt; +<br>&gt;&gt; +       xen_domain = dom_iommu(d)-&gt;arch.priv;<br>&gt;&gt; +<br>&gt;&gt; +       if (!arm_smmu || arm_smmu-&gt;s2_cfg.domain != d) {<br>&gt;&gt; +               dev_err(dev, &quot; not attached to domain %d\n&quot;,<br>&gt;&gt; d-&gt;domain_id);<br>&gt;&gt; +               return -ESRCH;<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +       spin_lock(&amp;xen_domain-&gt;lock);<br>&gt;&gt; +<br>&gt;&gt; +       arm_smmu_detach_dev(dev);<br>&gt;&gt; +       atomic_dec(&amp;domain-&gt;ref);<br>&gt;&gt; +<br>&gt;&gt; +       if (domain-&gt;ref.counter == 0)<br>&gt;&gt; +               arm_smmu_destroy_iommu_domain(domain);<br>&gt;&gt; +<br>&gt;&gt; +       spin_unlock(&amp;xen_domain-&gt;lock);<br>&gt;&gt; +<br>&gt;&gt; +       return 0;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static int arm_smmu_reassign_dev(struct domain *s, struct domain *t,<br>&gt;&gt; +                                u8 devfn,  struct device *dev)<br>&gt;&gt; +{<br>&gt;&gt; +       int ret = 0;<br>&gt;&gt; +<br>&gt;&gt; +       /* Don&#39;t allow remapping on other domain than hwdom */<br>&gt;&gt; +       if (t &amp;&amp; t != hardware_domain)<br>&gt;&gt; +               return -EPERM;<br>&gt;&gt; +<br>&gt;&gt; +       if (t == s)<br>&gt;&gt; +               return 0;<br>&gt;&gt; +<br>&gt;&gt; +       ret = arm_smmu_deassign_dev(s, dev);<br>&gt;&gt; +       if (ret)<br>&gt;&gt; +               return ret;<br>&gt;&gt; +<br>&gt;&gt; +       if (t) {<br>&gt;&gt; +               /* No flags are defined for ARM. */<br>&gt;&gt; +               ret = arm_smmu_assign_dev(t, devfn, dev, 0);<br>&gt;&gt; +               if (ret)<br>&gt;&gt; +                       return ret;<br>&gt;&gt; +       }<br>&gt;&gt; +<br>&gt;&gt; +       return 0;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static int arm_smmu_iommu_domain_init(struct domain *d)<br>&gt;&gt; +{<br>&gt;&gt; +       struct arm_smmu_xen_domain *xen_domain;<br>&gt;&gt; +<br>&gt;&gt; +       xen_domain = xzalloc(struct arm_smmu_xen_domain);<br>&gt;&gt; +       if (!xen_domain)<br>&gt;&gt; +               return -ENOMEM;<br>&gt;&gt; +<br>&gt;&gt; +       spin_lock_init(&amp;xen_domain-&gt;lock);<br>&gt;&gt; +       INIT_LIST_HEAD(&amp;xen_domain-&gt;contexts);<br>&gt;&gt; +<br>&gt;&gt; +       dom_iommu(d)-&gt;arch.priv = xen_domain;<br>&gt;&gt; +<br>&gt;&gt; +       return 0;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static void __hwdom_init arm_smmu_iommu_hwdom_init(struct domain *d)<br>&gt;&gt; +{<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static void arm_smmu_iommu_domain_teardown(struct domain *d)<br>&gt;&gt; +{<br>&gt;&gt; +       struct arm_smmu_xen_domain *xen_domain = dom_iommu(d)-&gt;arch.priv;<br>&gt;&gt; +<br>&gt;&gt; +       ASSERT(list_empty(&amp;xen_domain-&gt;contexts));<br>&gt;&gt; +       xfree(xen_domain);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static int __must_check arm_smmu_map_page(struct domain *d, unsigned long<br>&gt;&gt; gfn,<br>&gt;&gt; +                       unsigned long mfn, unsigned int flags)<br>&gt;&gt; +{<br>&gt;&gt; +       p2m_type_t t;<br>&gt;&gt; +<br>&gt;&gt; +       /*<br>&gt;&gt; +        * Grant mappings can be used for DMA requests. The dev_bus_addr<br>&gt;&gt; +        * returned by the hypercall is the MFN (not the IPA). For device<br>&gt;&gt; +        * protected by an IOMMU, Xen needs to add a 1:1 mapping in the<br>&gt;&gt; domain<br>&gt;&gt; +        * p2m to allow DMA request to work.<br>&gt;&gt; +        * This is only valid when the domain is directed mapped. Hence<br>&gt;&gt; this<br>&gt;&gt; +        * function should only be used by gnttab code with gfn == mfn.<br>&gt;&gt; +        */<br>&gt;&gt; +       BUG_ON(!is_domain_direct_mapped(d));<br>&gt;&gt; +       BUG_ON(mfn != gfn);<br>&gt;&gt; +<br>&gt;&gt; +       /* We only support readable and writable flags */<br>&gt;&gt; +       if (!(flags &amp; (IOMMUF_readable | IOMMUF_writable)))<br>&gt;&gt; +               return -EINVAL;<br>&gt;&gt; +<br>&gt;&gt; +       t = (flags &amp; IOMMUF_writable) ? p2m_iommu_map_rw :<br>&gt;&gt; p2m_iommu_map_ro;<br>&gt;&gt; +<br>&gt;&gt; +       /*<br>&gt;&gt; +        * The function guest_physmap_add_entry replaces the current<br>&gt;&gt; mapping<br>&gt;&gt; +        * if there is already one...<br>&gt;&gt; +        */<br>&gt;&gt; +       return guest_physmap_add_entry(d, _gfn(gfn), _mfn(mfn), 0, t);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static int __must_check arm_smmu_unmap_page(struct domain *d, unsigned<br>&gt;&gt; long gfn)<br>&gt;&gt; +{<br>&gt;&gt; +       /*<br>&gt;&gt; +        * This function should only be used by gnttab code when the<br>&gt;&gt; domain<br>&gt;&gt; +        * is direct mapped<br>&gt;&gt; +        */<br>&gt;&gt; +       if (!is_domain_direct_mapped(d))<br>&gt;&gt; +               return -EINVAL;<br>&gt;&gt; +<br>&gt;&gt; +       return guest_physmap_remove_page(d, _gfn(gfn), _mfn(gfn), 0);<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static const struct iommu_ops arm_smmu_iommu_ops = {<br>&gt;&gt; +       .init = arm_smmu_iommu_domain_init,<br>&gt;&gt; +       .hwdom_init = arm_smmu_iommu_hwdom_init,<br>&gt;&gt; +       .teardown = arm_smmu_iommu_domain_teardown,<br>&gt;&gt; +       .iotlb_flush = arm_smmu_iotlb_flush,<br>&gt;&gt; +       .iotlb_flush_all = arm_smmu_iotlb_flush_all,<br>&gt;&gt; +       .assign_device = arm_smmu_assign_dev,<br>&gt;&gt; +       .reassign_device = arm_smmu_reassign_dev,<br>&gt;&gt; +       .map_page = arm_smmu_map_page,<br>&gt;&gt; +       .unmap_page = arm_smmu_unmap_page,<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +static<br>&gt;&gt; +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle<br>&gt;&gt; *fwnode)<br>&gt;&gt; +{<br>&gt;&gt; +       struct arm_smmu_device *smmu = NULL;<br>&gt;&gt; +<br>&gt;&gt; +       spin_lock(&amp;arm_smmu_devices_lock);<br>&gt;&gt; +       list_for_each_entry(smmu, &amp;arm_smmu_devices, devices) {<br>&gt;&gt; +               if (smmu-&gt;dev-&gt;fwnode == fwnode)<br>&gt;&gt; +                       break;<br>&gt;&gt; +       }<br>&gt;&gt; +       spin_unlock(&amp;arm_smmu_devices_lock);<br>&gt;&gt; +<br>&gt;&gt; +       return smmu;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +static __init int arm_smmu_dt_init(struct dt_device_node *dev,<br>&gt;&gt; +                                  const void *data)<br>&gt;&gt; +{<br>&gt;&gt; +       int rc;<br>&gt;&gt; +<br>&gt;&gt; +       /*<br>&gt;&gt; +        * Even if the device can&#39;t be initialized, we don&#39;t want to<br>&gt;&gt; +        * give the SMMU device to dom0.<br>&gt;&gt; +        */<br>&gt;&gt; +       dt_device_set_used_by(dev, DOMID_XEN);<br>&gt;&gt; +<br>&gt;&gt; +       rc = arm_smmu_device_probe(dt_to_dev(dev));<br>&gt;&gt; +       if (rc)<br>&gt;&gt; +               return rc;<br>&gt;&gt; +<br>&gt;&gt; +       iommu_set_ops(&amp;arm_smmu_iommu_ops);<br>&gt;&gt; +<br>&gt;&gt; +       return 0;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +DT_DEVICE_START(smmuv3, &quot;ARM SMMU V3&quot;, DEVICE_IOMMU)<br>&gt;&gt; +       .dt_match = arm_smmu_of_match,<br>&gt;&gt; +       .init = arm_smmu_dt_init,<br>&gt;&gt; +DT_DEVICE_END<br>&gt;&gt; +<br>&gt;&gt; +#ifdef CONFIG_ACPI<br>&gt;&gt; +/* Set up the IOMMU */<br>&gt;&gt; +static int __init arm_smmu_acpi_init(const void *data)<br>&gt;&gt; +{<br>&gt;&gt; +       int rc;<br>&gt;&gt; +<br>&gt;&gt; +       rc = arm_smmu_device_probe((struct device *)data);<br>&gt;&gt; +       if (rc)<br>&gt;&gt; +               return rc;<br>&gt;&gt; +<br>&gt;&gt; +       iommu_set_ops(&amp;arm_smmu_iommu_ops);<br>&gt;&gt; +       return 0;<br>&gt;&gt; +}<br>&gt;&gt; +<br>&gt;&gt; +ACPI_DEVICE_START(asmmuv3, &quot;ARM SMMU V3&quot;, DEVICE_IOMMU)<br>&gt;&gt; +       .class_type = ACPI_IORT_NODE_SMMU_V3,<br>&gt;&gt; +       .init = arm_smmu_acpi_init,<br>&gt;&gt; +ACPI_DEVICE_END<br>&gt;&gt; +<br>&gt;&gt; +#endif<br>&gt;&gt; diff --git a/xen/include/xen/linux_compat.h<br>&gt;&gt; b/xen/include/xen/linux_compat.h<br>&gt;&gt; new file mode 100644<br>&gt;&gt; index 0000000000..8037be0a3e<br>&gt;&gt; --- /dev/null<br>&gt;&gt; +++ b/xen/include/xen/linux_compat.h<br>&gt;&gt; @@ -0,0 +1,84 @@<br>&gt;&gt;<br>&gt;&gt; +/******************************************************************************<br>&gt;&gt; + * include/xen/linux_compat.h<br>&gt;&gt; + *<br>&gt;&gt; + * Compatibility defines for porting code from Linux to Xen<br>&gt;&gt; + *<br>&gt;&gt; + * Copyright (c) 2017 Linaro Limited<br>&gt;&gt; + *<br>&gt;&gt; + * This program is free software; you can redistribute it and/or modify<br>&gt;&gt; + * it under the terms of the GNU General Public License as published by<br>&gt;&gt; + * the Free Software Foundation; either version 2 of the License, or<br>&gt;&gt; + * (at your option) any later version.<br>&gt;&gt; + *<br>&gt;&gt; + * This program is distributed in the hope that it will be useful,<br>&gt;&gt; + * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>&gt;&gt; + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the<br>&gt;&gt; + * GNU General Public License for more details.<br>&gt;&gt; + *<br>&gt;&gt; + * You should have received a copy of the GNU General Public License<br>&gt;&gt; + * along with this program; If not, see &lt;<a href="http://www.gnu.org/licenses/">http://www.gnu.org/licenses/</a>&gt;.<br>&gt;&gt; + */<br>&gt;&gt; +<br>&gt;&gt; +#ifndef __XEN_LINUX_COMPAT_H__<br>&gt;&gt; +#define __XEN_LINUX_COMPAT_H__<br>&gt;&gt; +<br>&gt;&gt; +#include &lt;asm/types.h&gt;<br>&gt;&gt; +<br>&gt;&gt; +typedef paddr_t phys_addr_t;<br>&gt;&gt; +typedef paddr_t dma_addr_t;<br>&gt;&gt; +<br>&gt;&gt; +typedef unsigned int gfp_t;<br>&gt;&gt; +#define GFP_KERNEL 0<br>&gt;&gt; +#define __GFP_ZERO 0x01U<br>&gt;&gt; +<br>&gt;&gt; +/* Helpers for IRQ functions */<br>&gt;&gt; +#define free_irq release_irq<br>&gt;&gt; +<br>&gt;&gt; +enum irqreturn {<br>&gt;&gt; +    IRQ_NONE,<br>&gt;&gt; +    IRQ_HANDLED,<br>&gt;&gt; +    IRQ_WAKE_THREAD,<br>&gt;&gt; +};<br>&gt;&gt; +<br>&gt;&gt; +typedef enum irqreturn irqreturn_t;<br>&gt;&gt; +<br>&gt;&gt; +/* Device logger functions */<br>&gt;&gt; +#define dev_dbg(dev, fmt, ...) printk(XENLOG_DEBUG fmt, ## __VA_ARGS__)<br>&gt;&gt; +#define dev_notice(dev, fmt, ...) printk(XENLOG_INFO fmt, ## __VA_ARGS__)<br>&gt;&gt; +#define dev_warn(dev, fmt, ...) printk(XENLOG_WARNING fmt, ##<br>&gt;&gt; __VA_ARGS__)<br>&gt;&gt; +#define dev_err(dev, fmt, ...) printk(XENLOG_ERR fmt, ## __VA_ARGS__)<br>&gt;&gt; +#define dev_info(dev, fmt, ...) printk(XENLOG_INFO fmt, ## __VA_ARGS__)<br>&gt;&gt; +<br>&gt;&gt; +#define dev_err_ratelimited(dev, fmt, ...)                  \<br>&gt;&gt; +     printk(XENLOG_ERR fmt, ## __VA_ARGS__)<br>&gt;&gt; +<br>&gt;&gt; +#define dev_name(dev) dt_node_full_name(dev_to_dt(dev))<br>&gt;&gt; +<br>&gt;&gt; +/* Alias to Xen allocation helpers */<br>&gt;&gt; +#define kfree xfree<br>&gt;&gt; +#define kmalloc(size, flags) ({\<br>&gt;&gt; +       void *__ret_alloc = NULL; \<br>&gt;&gt; +       if (flags &amp; __GFP_ZERO) \<br>&gt;&gt; +               __ret_alloc = _xzalloc(size, sizeof(void *)); \<br>&gt;&gt; +       else \<br>&gt;&gt; +               __ret_alloc = _xmalloc(size, sizeof(void *)); \<br>&gt;&gt; +       __ret_alloc; \<br>&gt;&gt; +})<br>&gt;&gt; +#define kzalloc(size, flags)        _xzalloc(size, sizeof(void *))<br>&gt;&gt; +#define devm_kzalloc(dev, size, flags)  _xzalloc(size, sizeof(void *))<br>&gt;&gt; +#define kmalloc_array(size, n, flags) ({\<br>&gt;&gt; +       void *__ret_alloc = NULL; \<br>&gt;&gt; +       if (flags &amp; __GFP_ZERO) \<br>&gt;&gt; +               __ret_alloc = _xzalloc_array(size, sizeof(void *), n); \<br>&gt;&gt; +       else \<br>&gt;&gt; +               __ret_alloc = _xmalloc_array(size, sizeof(void *), n); \<br>&gt;&gt; +       __ret_alloc; \<br>&gt;&gt; +})<br>&gt;&gt; +<br>&gt;&gt; +/* Alias to Xen time functions */<br>&gt;&gt; +#define ktime_t s_time_t<br>&gt;&gt; +#define ktime_get()             (NOW())<br>&gt;&gt; +#define ktime_add_us(t,i)       (t + MICROSECS(i))<br>&gt;&gt; +#define ktime_compare(t,i)      (t &gt; (i))<br>&gt;&gt; +<br>&gt;&gt; +#endif /* __XEN_LINUX_COMPAT_H__ */<br>&gt;<br>&gt;<br>&gt;<br>&gt; _______________________________________________<br>&gt; Xen-devel mailing list<br>&gt; <a href="mailto:Xen-devel@lists.xenproject.org">Xen-devel@lists.xenproject.org</a><br>&gt; <a href="https://lists.xenproject.org/mailman/listinfo/xen-devel">https://lists.xenproject.org/mailman/listinfo/xen-devel</a><br></div>

Sorry for top posting,

is someone working on the comments on this patch?

-Manish


On 03/10/2018 11:23 PM, Manish Jaggi wrote:
> Hi Sameer,
>
>
> On 02/09/2018 08:40 AM, Sameer Goel wrote:
>> This driver follows an approach similar to smmu driver. The intent here
>> is to reuse as much Linux code as possible.
>> - Glue code has been introduced to bridge the API calls.
>> - Called Linux functions from the Xen IOMMU function calls.
>> - Xen modifications are preceded by /*Xen: comment */
>> - xen/linux_compat: Add a Linux compat header
>>    For porting files directly from Linux it is useful to have a 
>> function mapping
>>    definitions from Linux to Xen. This file adds common API functions 
>> and
>>    other defines that are needed for porting arm SMMU drivers.
>>
>> Signed-off-by: Sameer Goel <sameer.goel@linaro.org>
>> ---
>>   xen/arch/arm/p2m.c                    |   1 +
>>   xen/drivers/Kconfig                   |   2 +
>>   xen/drivers/passthrough/arm/Kconfig   |   8 +
>>   xen/drivers/passthrough/arm/Makefile  |   1 +
>>   xen/drivers/passthrough/arm/smmu-v3.c | 892 
>> ++++++++++++++++++++++++++++++++--
>>   xen/include/xen/linux_compat.h        |  84 ++++
>>   6 files changed, 959 insertions(+), 29 deletions(-)
>>   create mode 100644 xen/drivers/passthrough/arm/Kconfig
>>   create mode 100644 xen/include/xen/linux_compat.h
>>
>> diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
>> index 65e8b9c6ea..fef7605fd6 100644
>> --- a/xen/arch/arm/p2m.c
>> +++ b/xen/arch/arm/p2m.c
>> @@ -1460,6 +1460,7 @@ err:
>>   static void __init setup_virt_paging_one(void *data)
>>   {
>>       unsigned long val = (unsigned long)data;
>> +    /* SMMUv3 S2 cfg vtcr reuses the following value */
>>       WRITE_SYSREG32(val, VTCR_EL2);
>>       isb();
>>   }
>> diff --git a/xen/drivers/Kconfig b/xen/drivers/Kconfig
>> index bc3a54f0ea..612655386d 100644
>> --- a/xen/drivers/Kconfig
>> +++ b/xen/drivers/Kconfig
>> @@ -12,4 +12,6 @@ source "drivers/pci/Kconfig"
>>     source "drivers/video/Kconfig"
>>   +source "drivers/passthrough/arm/Kconfig"
>> +
>>   endmenu
>> diff --git a/xen/drivers/passthrough/arm/Kconfig 
>> b/xen/drivers/passthrough/arm/Kconfig
>> new file mode 100644
>> index 0000000000..cda899f608
>> --- /dev/null
>> +++ b/xen/drivers/passthrough/arm/Kconfig
>> @@ -0,0 +1,8 @@
>> +
>> +config ARM_SMMU_v3
>> +    bool "ARM SMMUv3 Support"
>> +    depends on ARM_64
>> +    help
>> +     Support for implementations of the ARM System MMU architecture
>> +     version 3.
>> +
>> diff --git a/xen/drivers/passthrough/arm/Makefile 
>> b/xen/drivers/passthrough/arm/Makefile
>> index f4cd26e15d..e14732b55c 100644
>> --- a/xen/drivers/passthrough/arm/Makefile
>> +++ b/xen/drivers/passthrough/arm/Makefile
>> @@ -1,2 +1,3 @@
>>   obj-y += iommu.o
>>   obj-y += smmu.o
>> +obj-$(CONFIG_ARM_SMMU_v3) += smmu-v3.o
>> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c 
>> b/xen/drivers/passthrough/arm/smmu-v3.c
>> index e67ba6c40f..f43485fe6e 100644
>> --- a/xen/drivers/passthrough/arm/smmu-v3.c
>> +++ b/xen/drivers/passthrough/arm/smmu-v3.c
>> @@ -18,28 +18,414 @@
>>    * Author: Will Deacon <will.deacon@arm.com>
>>    *
>>    * This driver is powered by bad coffee and bombay mix.
>> + *
>> + *
>> + * Based on Linux drivers/iommu/arm-smmu-v3.c
>> + * => commit 7aa8619a66aea52b145e04cbab4f8d6a4e5f3f3b
>> + *
>> + * Xen modifications:
>> + * Sameer Goel <sameer.goel@linaro.org>
>> + * Copyright (C) 2017, The Linux Foundation, All rights reserved.
>> + *
>> + */
>> +
>> +#include <xen/acpi.h>
>> +#include <xen/config.h>
>> +#include <xen/delay.h>
>> +#include <xen/errno.h>
>> +#include <xen/err.h>
>> +#include <xen/irq.h>
>> +#include <xen/lib.h>
>> +#include <xen/linux_compat.h>
>> +#include <xen/list.h>
>> +#include <xen/mm.h>
>> +#include <xen/rbtree.h>
>> +#include <xen/sched.h>
>> +#include <xen/sizes.h>
>> +#include <xen/vmap.h>
>> +#include <acpi/acpi_iort.h>
>> +#include <asm/atomic.h>
>> +#include <asm/device.h>
>> +#include <asm/io.h>
>> +#include <asm/platform.h>
>> +
>> +/* Alias to Xen device tree helpers */
>> +#define device_node dt_device_node
>> +#define of_phandle_args dt_phandle_args
>> +#define of_device_id dt_device_match
>> +#define of_match_node dt_match_node
>> +#define of_property_read_u32(np, pname, out) 
>> (!dt_property_read_u32(np, pname, out))
>> +#define of_property_read_bool dt_property_read_bool
>> +#define of_parse_phandle_with_args dt_parse_phandle_with_args
>> +
>> +/* Xen: Helpers to get device MMIO and IRQs */
>> +struct resource {
>> +    u64 addr;
>> +    u64 size;
>> +    unsigned int type;
>> +};
>> +
>> +#define resource_size(res) ((res)->size)
>> +
>> +#define platform_device device
>> +
>> +#define IORESOURCE_MEM 0
>> +#define IORESOURCE_IRQ 1
>> +
>> +static struct resource *platform_get_resource(struct platform_device 
>> *pdev,
>> +                          unsigned int type,
>> +                          unsigned int num)
>> +{
>> +    /*
>> +     * The resource is only used between 2 calls of 
>> platform_get_resource.
>> +     * It's quite ugly but it's avoid to add too much code in the part
>> +     * imported from Linux
>> +     */
>> +    static struct resource res;
>> +    struct acpi_iort_node *iort_node;
>> +    struct acpi_iort_smmu_v3 *node_smmu_data;
>> +    int ret = 0;
>> +
>> +    res.type = type;
>> +
>> +    switch (type) {
>> +    case IORESOURCE_MEM:
>> +        if (pdev->type == DEV_ACPI) {
>> +            ret = 1;
>> +            iort_node = pdev->acpi_node;
>> +            node_smmu_data =
>> +                (struct acpi_iort_smmu_v3 *)iort_node->node_data;
>> +
>> +            if (node_smmu_data != NULL) {
>> +                res.addr = node_smmu_data->base_address;
>> +                res.size = SZ_128K;
>> +                ret = 0;
>> +            }
>> +        } else {
>> +            ret = dt_device_get_address(dev_to_dt(pdev), num,
>> +                            &res.addr, &res.size);
>> +        }
>> +
>> +        return ((ret) ? NULL : &res);
>> +
>> +    case IORESOURCE_IRQ:
>> +        /* ACPI case not implemented as there is no use case for it */
>> +        ret = platform_get_irq(dev_to_dt(pdev), num);
>> +
>> +        if (ret < 0)
>> +            return NULL;
>> +
>> +        res.addr = ret;
>> +        res.size = 1;
>> +
>> +        return &res;
>> +
>> +    default:
>> +        return NULL;
>> +    }
>> +}
>> +
>> +static int platform_get_irq_byname(struct platform_device *pdev, 
>> const char *name)
>> +{
>> +    const struct dt_property *dtprop;
>> +    struct acpi_iort_node *iort_node;
>> +    struct acpi_iort_smmu_v3 *node_smmu_data;
>> +    int ret = 0;
>> +
>> +    if (pdev->type == DEV_ACPI) {
>> +        iort_node = pdev->acpi_node;
>> +        node_smmu_data = (struct acpi_iort_smmu_v3 
>> *)iort_node->node_data;
>> +
>> +        if (node_smmu_data != NULL) {
>> +            if (!strcmp(name, "eventq"))
>> +                ret = node_smmu_data->event_gsiv;
>> +            else if (!strcmp(name, "priq"))
>> +                ret = node_smmu_data->pri_gsiv;
>> +            else if (!strcmp(name, "cmdq-sync"))
>> +                ret = node_smmu_data->sync_gsiv;
>> +            else if (!strcmp(name, "gerror"))
>> +                ret = node_smmu_data->gerr_gsiv;
>> +            else
>> +                ret = -EINVAL;
>> +        }
>> +    } else {
>> +        dtprop = dt_find_property(dev_to_dt(pdev), 
>> "interrupt-names", NULL);
>> +        if (!dtprop)
>> +            return -EINVAL;
>> +
>> +        if (!dtprop->value)
>> +            return -ENODATA;
>> +    }
>> +
>> +    return ret;
>> +}
>> +
>> +/*
>> + * Xen: Helpers for DMA allocation. Just the function name is reused 
>> for
>> + * porting code these allocation are not managed allocations
>>    */
>>   -#include <linux/acpi.h>
>> -#include <linux/acpi_iort.h>
>> -#include <linux/delay.h>
>> -#include <linux/dma-iommu.h>
>> -#include <linux/err.h>
>> -#include <linux/interrupt.h>
>> -#include <linux/iommu.h>
>> -#include <linux/iopoll.h>
>> -#include <linux/module.h>
>> -#include <linux/msi.h>
>> -#include <linux/of.h>
>> -#include <linux/of_address.h>
>> -#include <linux/of_iommu.h>
>> -#include <linux/of_platform.h>
>> -#include <linux/pci.h>
>> -#include <linux/platform_device.h>
>> -
>> -#include <linux/amba/bus.h>
>> -
>> -#include "io-pgtable.h"
>> +static void *dmam_alloc_coherent(struct device *dev, size_t size,
>> +               dma_addr_t *dma_handle, gfp_t gfp)
>> +{
>> +    void *vaddr;
>> +    unsigned long alignment = size;
>> +
>> +    /*
>> +     * _xzalloc requires that the (align & (align -1)) = 0. Most of the
>> +     * allocations in SMMU code should send the right value for 
>> size. In
>> +     * case this is not true print a warning and align to the size of a
>> +     * (void *)
>> +     */
>> +    if (size & (size - 1)) {
>> +        dev_warn(dev, "Fixing alignment for the DMA buffer\n");
>> +        alignment = sizeof(void *);
>> +    }
>> +
>> +    vaddr = _xzalloc(size, alignment);
>> +    if (!vaddr) {
>> +        dev_err(dev, "DMA allocation failed\n");
>> +        return NULL;
>> +    }
>> +
>> +    *dma_handle = virt_to_maddr(vaddr);
>> +
>> +    return vaddr;
>> +}
>> +
>> +
>> +static void dmam_free_coherent(struct device *dev, size_t size, void 
>> *vaddr,
>> +            dma_addr_t dma_handle)
>> +{
>> +    xfree(vaddr);
>> +}
>> +
>> +/* Xen: Stub out DMA domain related functions */
>> +#define iommu_get_dma_cookie(dom) 0
>> +#define iommu_put_dma_cookie(dom)
>> +
>> +/* Xen: Stub out module param related function */
>> +#define module_param_named(a, b, c, d)
>> +#define MODULE_PARM_DESC(a, b)
>> +
>> +#define dma_set_mask_and_coherent(d, b) 0
>> +
>> +#define of_dma_is_coherent(n) 0
>> +
>> +#define MODULE_DEVICE_TABLE(type, name)
>> +
>> +static void __iomem *devm_ioremap_resource(struct device *dev,
>> +                       struct resource *res)
>> +{
>> +    void __iomem *ptr;
>> +
>> +    if (!res || res->type != IORESOURCE_MEM) {
>> +        dev_err(dev, "Invalid resource\n");
>> +        return ERR_PTR(-EINVAL);
>> +    }
>> +
>> +    ptr = ioremap_nocache(res->addr, res->size);
>> +    if (!ptr) {
>> +        dev_err(dev,
>> +            "ioremap failed (addr 0x%"PRIx64" size 0x%"PRIx64")\n",
>> +            res->addr, res->size);
>> +        return ERR_PTR(-ENOMEM);
>> +    }
>> +
>> +    return ptr;
>> +}
>> +
>> +/* Xen: Compatibility define for iommu_domain_geometry.*/
>> +struct iommu_domain_geometry {
>> +    dma_addr_t aperture_start; /* First address that can be 
>> mapped    */
>> +    dma_addr_t aperture_end;   /* Last address that can be 
>> mapped     */
>> +    bool force_aperture;       /* DMA only allowed in mappable 
>> range? */
>> +};
>> +
>> +
>> +/* Xen: Type definitions for iommu_domain */
>> +#define IOMMU_DOMAIN_UNMANAGED 0
>> +#define IOMMU_DOMAIN_DMA 1
>> +#define IOMMU_DOMAIN_IDENTITY 2
>> +
>> +/* Xen: Dummy iommu_domain */
>> +struct iommu_domain {
>> +    /* Runtime SMMU configuration for this iommu_domain */
>> +    struct arm_smmu_domain        *priv;
>> +    unsigned int type;
>> +
>> +    /* Dummy compatibility defines */
>> +    unsigned long pgsize_bitmap;
>> +    struct iommu_domain_geometry geometry;
>> +
>> +    atomic_t ref;
>> +    /*
>> +     * Used to link iommu_domain contexts for a same domain.
>> +     * There is at least one per-SMMU to used by the domain.
>> +     */
>> +    struct list_head        list;
>> +};
>> +
>> +/* Xen: Describes information required for a Xen domain */
>> +struct arm_smmu_xen_domain {
>> +    spinlock_t            lock;
>> +    /* List of iommu domains associated to this domain */
>> +    struct list_head        contexts;
>> +};
>> +
>> +/*
>> + * Xen: Information about each device stored in dev->archdata.iommu
>> + *
>> + * The dev->archdata.iommu stores the iommu_domain (runtime 
>> configuration of
>> + * the SMMU).
>> + */
>> +struct arm_smmu_xen_device {
>> +    struct iommu_domain *domain;
>> +};
>> +
>> +/*
>> + * Xen: io_pgtable compatibility defines.
>> + * Most of these are to port in the S1 translation code as is.
>> + */
>> +struct io_pgtable_ops {
>> +};
>> +
>> +struct iommu_gather_ops {
>> +    void (*tlb_flush_all)(void *cookie);
>> +    void (*tlb_add_flush)(unsigned long iova, size_t size, size_t 
>> granule,
>> +                  bool leaf, void *cookie);
>> +    void (*tlb_sync)(void *cookie);
>> +};
>> +
>> +struct io_pgtable_cfg {
>> +    /*
>> +     * IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE 
>> bits in
>> +     *    stage 1 PTEs, for hardware which insists on validating them
>> +     *    even in    non-secure state where they should normally be 
>> ignored.
>> +     *
>> +     * IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE 
>> and
>> +     *    IOMMU_NOEXEC flags and map everything with full access, for
>> +     *    hardware which does not implement the permissions of a given
>> +     *    format, and/or requires some format-specific default value.
>> +     *
>> +     * IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching 
>> invalid
>> +     *    (unmapped) entries but the hardware might do so anyway, 
>> perform
>> +     *    TLB maintenance when mapping as well as when unmapping.
>> +     *
>> +     * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
>> +     *    PTEs, for Mediatek IOMMUs which treat it as a 33rd address 
>> bit
>> +     *    when the SoC is in "4GB mode" and they can only access the 
>> high
>> +     *    remap of DRAM (0x1_00000000 to 0x1_ffffffff).
>> +     *
>> +     * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only 
>> ever
>> +     *    be accessed by a fully cache-coherent IOMMU or CPU (e.g. 
>> for a
>> +     *    software-emulated IOMMU), such that pagetable updates need 
>> not
>> +     *    be treated as explicit DMA data.
>> +     */
>> +    #define IO_PGTABLE_QUIRK_ARM_NS        BIT(0)
>> +    #define IO_PGTABLE_QUIRK_NO_PERMS    BIT(1)
>> +    #define IO_PGTABLE_QUIRK_TLBI_ON_MAP    BIT(2)
>> +    #define IO_PGTABLE_QUIRK_ARM_MTK_4GB    BIT(3)
>> +    #define IO_PGTABLE_QUIRK_NO_DMA        BIT(4)
>> +    unsigned long            quirks;
>> +    unsigned long            pgsize_bitmap;
>> +    unsigned int            ias;
>> +    unsigned int            oas;
>> +    const struct iommu_gather_ops    *tlb;
>> +    struct device            *iommu_dev;
>> +
>> +    /* Low-level data specific to the table format */
>> +    union {
>> +        struct {
>> +            u64    ttbr[2];
>> +            u64    tcr;
>> +            u64    mair[2];
>> +        } arm_lpae_s1_cfg;
>> +
>> +        struct {
>> +            u64    vttbr;
>> +            u64    vtcr;
>> +        } arm_lpae_s2_cfg;
>> +
>> +        struct {
>> +            u32    ttbr[2];
>> +            u32    tcr;
>> +            u32    nmrr;
>> +            u32    prrr;
>> +        } arm_v7s_cfg;
>> +    };
>> +};
>> +
>> +enum io_pgtable_fmt {
>> +    ARM_32_LPAE_S1,
>> +    ARM_32_LPAE_S2,
>> +    ARM_64_LPAE_S1,
>> +    ARM_64_LPAE_S2,
>> +    ARM_V7S,
>> +    IO_PGTABLE_NUM_FMTS,
>> +};
>> +
>> +/*
>> + * Xen: The pgtable_ops are used by the S1 translations, so return 
>> the dummy
>> + * address.
>> + */
>> +#define alloc_io_pgtable_ops(f, c, o) ((struct io_pgtable_ops *)0x0)
> Is this correct? it will make the caller null check fail
>> +#define free_io_pgtable_ops(o)
>> +
>> +/* Xen: Define wrapper for requesting IRQs */
>> +#define IRQF_ONESHOT 0
>> +
>> +typedef void (*irq_handler_t)(int, void *, struct cpu_user_regs *);
>> +
>> +static inline int devm_request_irq(struct device *dev, unsigned int 
>> irq,
>> +                   irq_handler_t handler, unsigned long irqflags,
>> +                   const char *devname, void *dev_id)
>> +{
>> +    /*
>> +     * SMMUv3 implementation can support wired interrupt outputs 
>> that are
>> +     * edge-triggered. Set the irq type as per the spec.
>> +     */
>> +    irq_set_type(irq, IRQ_TYPE_EDGE_BOTH);
>> +    return request_irq(irq, irqflags, handler, devname, dev_id);
>> +}
>> +
>> +/*
>> + * Xen does not have a concept of threaded irq, but eventually we 
>> can use
>> + * tasklets to optimize the following function.
>> + */
>> +int devm_request_threaded_irq(struct device *dev, unsigned int irq, 
>> irq_handler_t handler,
>> +                  irq_handler_t thread_fn, unsigned long irqflags,
>> +                  const char *devname, void *dev_id)
>> +{
>> +    return devm_request_irq(dev, irq, thread_fn, irqflags, devname, 
>> dev_id);
>> +}
>> +
>> +/* Xen: The mutex is used only during initialization so the typecast 
>> is safe */
>> +#define mutex spinlock
>> +#define mutex_init spin_lock_init
>> +#define mutex_lock spin_lock
>> +#define mutex_unlock spin_unlock
>> +
>> +#define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \
>> +({ \
>> +    s_time_t deadline = NOW() + MICROSECS(timeout_us); \
>> +    for (;;) { \
>> +        (val) = op(addr); \
>> +        if (cond) \
>> +            break; \
>> +        if (NOW() > deadline) { \
>> +            (val) = op(addr); \
>> +            break; \
>> +        } \
>> +    udelay(sleep_us); \
>> +    } \
>> +    (cond) ? 0 : -ETIMEDOUT; \
>> +})
>> +
>> +#define readl_relaxed_poll_timeout(addr, val, cond, delay_us, 
>> timeout_us) \
>> +    readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, 
>> timeout_us)
>> +
>> +#define VA_BITS 0 /* Only needed for S1 translations */
>>     /* MMIO registers */
>>   #define ARM_SMMU_IDR0            0x0
>> @@ -433,6 +819,7 @@ enum pri_resp {
>>       PRI_RESP_SUCC,
>>   };
>>   +#if 0 /* Xen: No MSI support in this iteration */
>>   enum arm_smmu_msi_index {
>>       EVTQ_MSI_INDEX,
>>       GERROR_MSI_INDEX,
>> @@ -457,6 +844,7 @@ static phys_addr_t 
>> arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
>>           ARM_SMMU_PRIQ_IRQ_CFG2,
>>       },
>>   };
>> +#endif
>>     struct arm_smmu_cmdq_ent {
>>       /* Common fields */
>> @@ -561,6 +949,8 @@ struct arm_smmu_s2_cfg {
>>       u16                vmid;
>>       u64                vttbr;
>>       u64                vtcr;
>> +    /* Xen: Domain associated to this configuration */
>> +    struct domain            *domain;
>>   };
>>     struct arm_smmu_strtab_ent {
>> @@ -635,9 +1025,21 @@ struct arm_smmu_device {
>>       struct arm_smmu_strtab_cfg    strtab_cfg;
>>         /* IOMMU core code handle */
>> +#if 0 /*Xen: Generic iommu_device ref not needed here */
>>       struct iommu_device        iommu;
>> +#endif
>> +    /* Xen: Need to keep a list of SMMU devices */
>> +    struct list_head                devices;
>>   };
>>   +/* Xen: Keep a list of devices associated with this driver */
>> +static DEFINE_SPINLOCK(arm_smmu_devices_lock);
>> +static LIST_HEAD(arm_smmu_devices);
>> +/* Xen: Helper for finding a device using fwnode */
>> +static
>> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle 
>> *fwnode);
>> +
>> +
>>   /* SMMU private data for each master */
>>   struct arm_smmu_master_data {
>>       struct arm_smmu_device        *smmu;
>> @@ -1232,7 +1634,7 @@ static void arm_smmu_handle_ppr(struct 
>> arm_smmu_device *smmu, u64 *evt)
>>         dev_info(smmu->dev, "unexpected PRI request received:\n");
>>       dev_info(smmu->dev,
>> -         "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at 
>> iova 0x%016llx\n",
>> +         "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at 
>> iova %#" PRIx64 "\n",
>>            sid, ssid, grpid, last ? "L" : "",
>>            evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",
>>            evt[0] & PRIQ_0_PERM_READ ? "R" : "",
>> @@ -1346,6 +1748,8 @@ static irqreturn_t 
>> arm_smmu_combined_irq_handler(int irq, void *dev)
>>   {
>>       arm_smmu_gerror_handler(irq, dev);
>>       arm_smmu_cmdq_sync_handler(irq, dev);
>> +    /*Xen: No threaded irq. So call the required function from here */
>> +    arm_smmu_combined_irq_thread(irq, dev);
>>       return IRQ_WAKE_THREAD;
>>   }
>>   @@ -1358,6 +1762,46 @@ static void __arm_smmu_tlb_sync(struct 
>> arm_smmu_device *smmu)
>>       arm_smmu_cmdq_issue_cmd(smmu, &cmd);
>>   }
>>   +/*
>> + * Xen: Define the IRQ handlers for xen. The linux functions would be
>> + * modified to use the functions defined in the following code.
>> + */
>> +static void arm_smmu_evtq_thread_xen(int irq, void *dev,
>> +                       struct cpu_user_regs *regs)
>> +{
>> +    arm_smmu_evtq_thread(irq, dev);
>> +}
>> +
>> +static void arm_smmu_priq_thread_xen(int irq, void *dev,
>> +                       struct cpu_user_regs *regs)
>> +{
>> +    arm_smmu_priq_thread(irq, dev);
>> +}
>> +
>> +static void arm_smmu_cmdq_sync_handler_xen(int irq, void *dev,
>> +                       struct cpu_user_regs *regs)
>> +{
>> +    arm_smmu_cmdq_sync_handler(irq, dev);
>> +}
>> +
>> +static void arm_smmu_gerror_handler_xen(int irq, void *dev,
>> +                       struct cpu_user_regs *regs)
>> +{
>> +    arm_smmu_gerror_handler(irq, dev);
>> +}
>> +
>> +static void arm_smmu_combined_irq_handler_xen(int irq, void *dev,
>> +                       struct cpu_user_regs *regs)
>> +{
>> +    arm_smmu_combined_irq_handler(irq, dev);
>> +}
>> +
>> +#define arm_smmu_evtq_thread arm_smmu_evtq_thread_xen
>> +#define arm_smmu_priq_thread arm_smmu_priq_thread_xen
>> +#define arm_smmu_cmdq_sync_handler arm_smmu_cmdq_sync_handler_xen
>> +#define arm_smmu_gerror_handler arm_smmu_gerror_handler_xen
>> +#define arm_smmu_combined_irq_handler arm_smmu_combined_irq_handler_xen
>> +
>>   static void arm_smmu_tlb_sync(void *cookie)
>>   {
>>       struct arm_smmu_domain *smmu_domain = cookie;
>> @@ -1415,6 +1859,7 @@ static const struct iommu_gather_ops 
>> arm_smmu_gather_ops = {
>>       .tlb_sync    = arm_smmu_tlb_sync,
>>   };
>>   +#if 0 /*Xen: Unused functionality */
>>   /* IOMMU API */
>>   static bool arm_smmu_capable(enum iommu_cap cap)
>>   {
>> @@ -1427,6 +1872,7 @@ static bool arm_smmu_capable(enum iommu_cap cap)
>>           return false;
>>       }
>>   }
>> +#endif
>>     static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
>>   {
>> @@ -1546,9 +1992,16 @@ static int arm_smmu_domain_finalise_s2(struct 
>> arm_smmu_domain *smmu_domain,
>>       if (vmid < 0)
>>           return vmid;
>>   -    cfg->vmid    = (u16)vmid;
>> -    cfg->vttbr    = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
>> -    cfg->vtcr    = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
>> +    /*
>> +     * Xen: Get the ttbr and vtcr values
>> +     * vttbr: This is a shared value with the domain page table
>> +     * vtcr: The TCR settings are the same as CPU since the page
>> +     * tables are shared
>> +     */
>> +
>> +    cfg->vmid    = vmid;
>> +    cfg->vttbr    = page_to_maddr(cfg->domain->arch.p2m.root);
>> +    cfg->vtcr    = READ_SYSREG32(VTCR_EL2) & STRTAB_STE_2_VTCR_MASK;
>>       return 0;
>>   }
>>   @@ -1604,6 +2057,7 @@ static int arm_smmu_domain_finalise(struct 
>> iommu_domain *domain)
>>       if (smmu->features & ARM_SMMU_FEAT_COHERENCY)
>>           pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_NO_DMA;
>>   +    /* Xen: pgtbl_ops gets an invalid address */
>>       pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
>>       if (!pgtbl_ops)
>>           return -ENOMEM;
> Will this not fail ?
>> @@ -1721,6 +2175,7 @@ out_unlock:
>>       return ret;
>>   }
>>   +#if 0 /* Xen: Unused functionality */
>>   static int arm_smmu_map(struct iommu_domain *domain, unsigned long 
>> iova,
>>               phys_addr_t paddr, size_t size, int prot)
>>   {
>> @@ -1772,6 +2227,7 @@ struct arm_smmu_device 
>> *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
>>       put_device(dev);
>>       return dev ? dev_get_drvdata(dev) : NULL;
>>   }
>> +#endif
>>     static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, 
>> u32 sid)
>>   {
>> @@ -1783,7 +2239,14 @@ static bool arm_smmu_sid_in_range(struct 
>> arm_smmu_device *smmu, u32 sid)
>>       return sid < limit;
>>   }
>>   +/* Xen: Unused */
>> +#if 0
>>   static struct iommu_ops arm_smmu_ops;
>> +#endif
>> +
>> +/* Xen: Redefine arm_smmu_ops to what fwspec should evaluate */
>> +static const struct iommu_ops arm_smmu_iommu_ops;
>> +#define arm_smmu_ops arm_smmu_iommu_ops
>>     static int arm_smmu_add_device(struct device *dev)
>>   {
>> @@ -1791,8 +2254,11 @@ static int arm_smmu_add_device(struct device 
>> *dev)
>>       struct arm_smmu_device *smmu;
>>       struct arm_smmu_master_data *master;
>>       struct iommu_fwspec *fwspec = dev->iommu_fwspec;
>> +#if 0 /*Xen: iommu_group is not needed */
>>       struct iommu_group *group;
>> +#endif
>>   +    /* Xen: fwspec->ops are not needed */
>>       if (!fwspec || fwspec->ops != &arm_smmu_ops)
>>           return -ENODEV;
>>       /*
>> @@ -1830,6 +2296,11 @@ static int arm_smmu_add_device(struct device 
>> *dev)
>>           }
>>       }
>>   +/*
>> + * Xen: Do not need an iommu group as the stream data is carried by 
>> the SMMU
>> + * master device object
>> + */
>> +#if 0
>>       group = iommu_group_get_for_dev(dev);
>>       if (!IS_ERR(group)) {
>>           iommu_group_put(group);
>> @@ -1837,8 +2308,16 @@ static int arm_smmu_add_device(struct device 
>> *dev)
>>       }
>>         return PTR_ERR_OR_ZERO(group);
>> +#endif
>> +    return 0;
>>   }
>>   +/*
>> + * Xen: We can potentially support this function and destroy a 
>> device. This
>> + * will be relevant for PCI hotplug. So, will be implemented as 
>> needed after
>> + * passthrough support is available.
>> + */
>> +#if 0
>>   static void arm_smmu_remove_device(struct device *dev)
>>   {
>>       struct iommu_fwspec *fwspec = dev->iommu_fwspec;
>> @@ -1974,6 +2453,7 @@ static struct iommu_ops arm_smmu_ops = {
>>       .put_resv_regions    = arm_smmu_put_resv_regions,
>>       .pgsize_bitmap        = -1UL, /* Restricted during device 
>> attach */
>>   };
>> +#endif
>>     /* Probing and initialisation functions */
>>   static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
>> @@ -2182,6 +2662,7 @@ static int arm_smmu_update_gbpa(struct 
>> arm_smmu_device *smmu, u32 set, u32 clr)
>>                         1, ARM_SMMU_POLL_TIMEOUT_US);
>>   }
>>   +#if 0 /* Xen: There is no MSI support as yet */
>>   static void arm_smmu_free_msis(void *data)
>>   {
>>       struct device *dev = data;
>> @@ -2247,12 +2728,15 @@ static void arm_smmu_setup_msis(struct 
>> arm_smmu_device *smmu)
>>       /* Add callback to free MSIs on teardown */
>>       devm_add_action(dev, arm_smmu_free_msis, dev);
>>   }
>> +#endif
>>     static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
>>   {
>>       int irq, ret;
>>   +#if 0 /*Xen: Cannot setup msis for now */
>>       arm_smmu_setup_msis(smmu);
>> +#endif
>>         /* Request interrupt lines */
>>       irq = smmu->evtq.q.irq;
>> @@ -2316,9 +2800,13 @@ static int arm_smmu_setup_irqs(struct 
>> arm_smmu_device *smmu)
>>            * Cavium ThunderX2 implementation doesn't not support unique
>>            * irq lines. Use single irq line for all the SMMUv3 
>> interrupts.
>>            */
>> -        ret = devm_request_threaded_irq(smmu->dev, irq,
>> +        /*
>> +         * Xen: Does not support threaded irqs, so serialise the setup.
>> +         * This is the same for pris and event interrupt lines on other
>> +         * systems
>> +         */
>> +        ret = devm_request_irq(smmu->dev, irq,
>>                       arm_smmu_combined_irq_handler,
>> -                    arm_smmu_combined_irq_thread,
>>                       IRQF_ONESHOT,
>>                       "arm-smmu-v3-combined-irq", smmu);
>>           if (ret < 0)
>> @@ -2542,8 +3030,14 @@ static int arm_smmu_device_hw_probe(struct 
>> arm_smmu_device *smmu)
>>           smmu->features |= ARM_SMMU_FEAT_STALLS;
>>       }
>>   +/*
>> + * Xen: Block stage 1 translations. By doing this here we do not 
>> need to set the
>> + * domain->stage explicitly.
>> + */
>> +#if 0
>>       if (reg & IDR0_S1P)
>>           smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
>> +#endif
>>         if (reg & IDR0_S2P)
>>           smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
>> @@ -2616,10 +3110,12 @@ static int arm_smmu_device_hw_probe(struct 
>> arm_smmu_device *smmu)
>>       if (reg & IDR5_GRAN4K)
>>           smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
>>   +#if 0 /* Xen: SMMU ops do not have a pgsize_bitmap member for Xen */
>>       if (arm_smmu_ops.pgsize_bitmap == -1UL)
>>           arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
>>       else
>>           arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
>> +#endif
>>         /* Output address size */
>>       switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) {
>> @@ -2680,7 +3176,8 @@ static int arm_smmu_device_acpi_probe(struct 
>> platform_device *pdev,
>>       struct device *dev = smmu->dev;
>>       struct acpi_iort_node *node;
>>   -    node = *(struct acpi_iort_node **)dev_get_platdata(dev);
>> +    /* Xen: Modification to get iort_node */
>> +    node = (struct acpi_iort_node *)dev->acpi_node;
>>         /* Retrieve SMMUv3 specific data */
>>       iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>> @@ -2703,7 +3200,7 @@ static inline int 
>> arm_smmu_device_acpi_probe(struct platform_device *pdev,
>>   static int arm_smmu_device_dt_probe(struct platform_device *pdev,
>>                       struct arm_smmu_device *smmu)
>>   {
>> -    struct device *dev = &pdev->dev;
>> +    struct device *dev = pdev;
>>       u32 cells;
>>       int ret = -EINVAL;
>>   @@ -2716,6 +3213,7 @@ static int arm_smmu_device_dt_probe(struct 
>> platform_device *pdev,
>>         parse_driver_options(smmu);
>>   +    /* Xen: of_dma_is_coherent is a stub till dt support is 
>> introduced */
>>       if (of_dma_is_coherent(dev->of_node))
>>           smmu->features |= ARM_SMMU_FEAT_COHERENCY;
>>   @@ -2734,9 +3232,11 @@ static int arm_smmu_device_probe(struct 
>> platform_device *pdev)
>>   {
>>       int irq, ret;
>>       struct resource *res;
>> +#if 0 /*Xen: Do not need to setup sysfs */
>>       resource_size_t ioaddr;
>> +#endif
>>       struct arm_smmu_device *smmu;
>> -    struct device *dev = &pdev->dev;
>> +    struct device *dev = pdev;/* Xen: dev is ignored */
>>       bool bypass;
>>         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
>> @@ -2763,7 +3263,9 @@ static int arm_smmu_device_probe(struct 
>> platform_device *pdev)
>>           dev_err(dev, "MMIO region too small (%pr)\n", res);
>>           return -EINVAL;
>>       }
>> +#if 0 /*Xen: Do not need to setup sysfs */
>>       ioaddr = res->start;
>> +#endif
>>         smmu->base = devm_ioremap_resource(dev, res);
>>       if (IS_ERR(smmu->base))
>> @@ -2802,13 +3304,18 @@ static int arm_smmu_device_probe(struct 
>> platform_device *pdev)
>>           return ret;
>>         /* Record our private device structure */
>> +    /* Xen: SMMU is not treated a a platform device*/
>> +#if 0
>>       platform_set_drvdata(pdev, smmu);
>> +#endif
>>         /* Reset the device */
>>       ret = arm_smmu_device_reset(smmu, bypass);
>>       if (ret)
>>           return ret;
>>   +/* Xen: Not creating an IOMMU device list for Xen */
>> +#if 0
>>       /* And we're up. Go go go! */
>>       ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL,
>>                        "smmu3.%pa", &ioaddr);
>> @@ -2844,9 +3351,20 @@ static int arm_smmu_device_probe(struct 
>> platform_device *pdev)
>>           if (ret)
>>               return ret;
>>       }
>> +#endif
>> +    /*
>> +     * Xen: Keep a list of all probed devices. This will be used to 
>> query
>> +     * the smmu devices based on the fwnode.
>> +     */
>> +    INIT_LIST_HEAD(&smmu->devices);
>> +    spin_lock(&arm_smmu_devices_lock);
>> +    list_add(&smmu->devices, &arm_smmu_devices);
>> +    spin_unlock(&arm_smmu_devices_lock);
>>       return 0;
>>   }
>>   +/* Xen: Unused function */
>> +#if 0
>>   static int arm_smmu_device_remove(struct platform_device *pdev)
>>   {
>>       struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
>> @@ -2860,6 +3378,8 @@ static void arm_smmu_device_shutdown(struct 
>> platform_device *pdev)
>>   {
>>       arm_smmu_device_remove(pdev);
>>   }
>> +#endif
>> +
>>     static const struct of_device_id arm_smmu_of_match[] = {
>>       { .compatible = "arm,smmu-v3", },
>> @@ -2867,6 +3387,7 @@ static const struct of_device_id 
>> arm_smmu_of_match[] = {
>>   };
>>   MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
>>   +#if 0
>>   static struct platform_driver arm_smmu_driver = {
>>       .driver    = {
>>           .name        = "arm-smmu-v3",
>> @@ -2883,3 +3404,316 @@ IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3", 
>> NULL);
>>   MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 
>> implementations");
>>   MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
>>   MODULE_LICENSE("GPL v2");
>> +#endif
>> +
>> +/***** Start of Xen specific code *****/
>> +
>> +static int __must_check arm_smmu_iotlb_flush_all(struct domain *d)
>> +{
>> +    struct arm_smmu_xen_domain *smmu_domain = dom_iommu(d)->arch.priv;
>> +    struct iommu_domain *cfg;
>> +
>> +    spin_lock(&smmu_domain->lock);
>> +    list_for_each_entry(cfg, &smmu_domain->contexts, list) {
>> +        /*
>> +         * Only invalidate the context when SMMU is present.
>> +         * This is because the context initialization is delayed
>> +         * until a master has been added.
>> +         */
>> +        if (unlikely(!ACCESS_ONCE(cfg->priv->smmu)))
>> +            continue;
>> +        arm_smmu_tlb_inv_context(cfg->priv);
>> +    }
>> +    spin_unlock(&smmu_domain->lock);
>> +    return 0;
>> +}
>> +
>> +static int __must_check arm_smmu_iotlb_flush(struct domain *d,
>> +                         unsigned long gfn,
>> +                         unsigned int page_count)
>> +{
>> +    return arm_smmu_iotlb_flush_all(d);
>> +}
>> +
>> +static struct iommu_domain *arm_smmu_get_domain(struct domain *d,
>> +                        struct device *dev)
>> +{
>> +    struct iommu_domain *domain;
>> +    struct arm_smmu_xen_domain *xen_domain;
>> +    struct arm_smmu_device *smmu;
>> +    struct arm_smmu_domain *smmu_domain;
>> +
>> +    xen_domain = dom_iommu(d)->arch.priv;
>> +
>> +    smmu = arm_smmu_get_by_fwnode(dev->iommu_fwspec->iommu_fwnode);
>> +    if (!smmu)
>> +        return NULL;
>> +
>> +    /*
>> +     * Loop through the &xen_domain->contexts to locate a context
>> +     * assigned to this SMMU
>> +     */
>> +    list_for_each_entry(domain, &xen_domain->contexts, list) {
>> +        smmu_domain = to_smmu_domain(domain);
>> +        if (smmu_domain->smmu == smmu)
>> +            return domain;
>> +    }
>> +
>> +    return NULL;
>> +}
>> +
>> +static void arm_smmu_destroy_iommu_domain(struct iommu_domain *domain)
>> +{
>> +    list_del(&domain->list);
>> +    arm_smmu_domain_free(domain);
>> +}
>> +
>> +static int arm_smmu_assign_dev(struct domain *d, u8 devfn,
>> +                   struct device *dev, u32 flag)
>> +{
>> +    int ret = 0;
>> +    struct iommu_domain *domain;
>> +    struct arm_smmu_xen_domain *xen_domain;
>> +    struct arm_smmu_domain *arm_smmu;
>> +
>> +    xen_domain = dom_iommu(d)->arch.priv;
>> +
>> +    if (!dev->archdata.iommu) {
>> +        dev->archdata.iommu = xzalloc(struct arm_smmu_xen_device);
>> +        if (!dev->archdata.iommu)
>> +            return -ENOMEM;
>> +    }
>> +
>> +    ret = arm_smmu_add_device(dev);
>> +    if (ret)
>> +        return ret;
>> +
>> +    spin_lock(&xen_domain->lock);
>> +
>> +    /*
>> +     * Check to see if an iommu_domain already exists for this xen 
>> domain
>> +     * under the same SMMU
>> +     */
>> +    domain = arm_smmu_get_domain(d, dev);
>> +    if (!domain) {
>> +
>> +        domain = arm_smmu_domain_alloc(IOMMU_DOMAIN_DMA);
>> +        if (!domain) {
>> +            ret = -ENOMEM;
>> +            goto out;
>> +        }
>> +
>> +        arm_smmu = to_smmu_domain(domain);
>> +        arm_smmu->s2_cfg.domain = d;
>> +
>> +        /* Chain the new context to the domain */
>> +        list_add(&domain->list, &xen_domain->contexts);
>> +
>> +    }
>> +
>> +    ret = arm_smmu_attach_dev(domain, dev);
>> +    if (ret) {
>> +        if (domain->ref.counter == 0)
>> +            arm_smmu_destroy_iommu_domain(domain);
>> +    } else {
>> +        atomic_inc(&domain->ref);
>> +    }
>> +
>> +out:
>> +    spin_unlock(&xen_domain->lock);
>> +    return ret;
>> +}
>> +
>> +static int arm_smmu_deassign_dev(struct domain *d, struct device *dev)
>> +{
>> +    struct iommu_domain *domain = arm_smmu_get_domain(d, dev);
>> +    struct arm_smmu_xen_domain *xen_domain;
>> +    struct arm_smmu_domain *arm_smmu = to_smmu_domain(domain);
>> +
>> +    xen_domain = dom_iommu(d)->arch.priv;
>> +
>> +    if (!arm_smmu || arm_smmu->s2_cfg.domain != d) {
>> +        dev_err(dev, " not attached to domain %d\n", d->domain_id);
>> +        return -ESRCH;
>> +    }
>> +
>> +    spin_lock(&xen_domain->lock);
>> +
>> +    arm_smmu_detach_dev(dev);
>> +    atomic_dec(&domain->ref);
>> +
>> +    if (domain->ref.counter == 0)
>> +        arm_smmu_destroy_iommu_domain(domain);
>> +
>> +    spin_unlock(&xen_domain->lock);
>> +
>> +    return 0;
>> +}
>> +
>> +static int arm_smmu_reassign_dev(struct domain *s, struct domain *t,
>> +                 u8 devfn,  struct device *dev)
>> +{
>> +    int ret = 0;
>> +
>> +    /* Don't allow remapping on other domain than hwdom */
>> +    if (t && t != hardware_domain)
>> +        return -EPERM;
>> +
>> +    if (t == s)
>> +        return 0;
>> +
>> +    ret = arm_smmu_deassign_dev(s, dev);
>> +    if (ret)
>> +        return ret;
>> +
>> +    if (t) {
>> +        /* No flags are defined for ARM. */
>> +        ret = arm_smmu_assign_dev(t, devfn, dev, 0);
>> +        if (ret)
>> +            return ret;
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static int arm_smmu_iommu_domain_init(struct domain *d)
>> +{
>> +    struct arm_smmu_xen_domain *xen_domain;
>> +
>> +    xen_domain = xzalloc(struct arm_smmu_xen_domain);
>> +    if (!xen_domain)
>> +        return -ENOMEM;
>> +
>> +    spin_lock_init(&xen_domain->lock);
>> +    INIT_LIST_HEAD(&xen_domain->contexts);
>> +
>> +    dom_iommu(d)->arch.priv = xen_domain;
>> +
>> +    return 0;
>> +}
>> +
>> +static void __hwdom_init arm_smmu_iommu_hwdom_init(struct domain *d)
>> +{
>> +}
>> +
>> +static void arm_smmu_iommu_domain_teardown(struct domain *d)
>> +{
>> +    struct arm_smmu_xen_domain *xen_domain = dom_iommu(d)->arch.priv;
>> +
>> +    ASSERT(list_empty(&xen_domain->contexts));
>> +    xfree(xen_domain);
>> +}
>> +
>> +static int __must_check arm_smmu_map_page(struct domain *d, unsigned 
>> long gfn,
>> +            unsigned long mfn, unsigned int flags)
>> +{
>> +    p2m_type_t t;
>> +
>> +    /*
>> +     * Grant mappings can be used for DMA requests. The dev_bus_addr
>> +     * returned by the hypercall is the MFN (not the IPA). For device
>> +     * protected by an IOMMU, Xen needs to add a 1:1 mapping in the 
>> domain
>> +     * p2m to allow DMA request to work.
>> +     * This is only valid when the domain is directed mapped. Hence 
>> this
>> +     * function should only be used by gnttab code with gfn == mfn.
>> +     */
>> +    BUG_ON(!is_domain_direct_mapped(d));
>> +    BUG_ON(mfn != gfn);
>> +
>> +    /* We only support readable and writable flags */
>> +    if (!(flags & (IOMMUF_readable | IOMMUF_writable)))
>> +        return -EINVAL;
>> +
>> +    t = (flags & IOMMUF_writable) ? p2m_iommu_map_rw : 
>> p2m_iommu_map_ro;
>> +
>> +    /*
>> +     * The function guest_physmap_add_entry replaces the current 
>> mapping
>> +     * if there is already one...
>> +     */
>> +    return guest_physmap_add_entry(d, _gfn(gfn), _mfn(mfn), 0, t);
>> +}
>> +
>> +static int __must_check arm_smmu_unmap_page(struct domain *d, 
>> unsigned long gfn)
>> +{
>> +    /*
>> +     * This function should only be used by gnttab code when the domain
>> +     * is direct mapped
>> +     */
>> +    if (!is_domain_direct_mapped(d))
>> +        return -EINVAL;
>> +
>> +    return guest_physmap_remove_page(d, _gfn(gfn), _mfn(gfn), 0);
>> +}
>> +
>> +static const struct iommu_ops arm_smmu_iommu_ops = {
>> +    .init = arm_smmu_iommu_domain_init,
>> +    .hwdom_init = arm_smmu_iommu_hwdom_init,
>> +    .teardown = arm_smmu_iommu_domain_teardown,
>> +    .iotlb_flush = arm_smmu_iotlb_flush,
>> +    .iotlb_flush_all = arm_smmu_iotlb_flush_all,
>> +    .assign_device = arm_smmu_assign_dev,
>> +    .reassign_device = arm_smmu_reassign_dev,
>> +    .map_page = arm_smmu_map_page,
>> +    .unmap_page = arm_smmu_unmap_page,
>> +};
>> +
>> +static
>> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle 
>> *fwnode)
>> +{
>> +    struct arm_smmu_device *smmu = NULL;
>> +
>> +    spin_lock(&arm_smmu_devices_lock);
>> +    list_for_each_entry(smmu, &arm_smmu_devices, devices) {
>> +        if (smmu->dev->fwnode == fwnode)
>> +            break;
>> +    }
>> +    spin_unlock(&arm_smmu_devices_lock);
>> +
>> +    return smmu;
>> +}
>> +
>> +static __init int arm_smmu_dt_init(struct dt_device_node *dev,
>> +                   const void *data)
>> +{
>> +    int rc;
>> +
>> +    /*
>> +     * Even if the device can't be initialized, we don't want to
>> +     * give the SMMU device to dom0.
>> +     */
>> +    dt_device_set_used_by(dev, DOMID_XEN);
>> +
>> +    rc = arm_smmu_device_probe(dt_to_dev(dev));
>> +    if (rc)
>> +        return rc;
>> +
>> +    iommu_set_ops(&arm_smmu_iommu_ops);
>> +
>> +    return 0;
>> +}
>> +
>> +DT_DEVICE_START(smmuv3, "ARM SMMU V3", DEVICE_IOMMU)
>> +    .dt_match = arm_smmu_of_match,
>> +    .init = arm_smmu_dt_init,
>> +DT_DEVICE_END
>> +
>> +#ifdef CONFIG_ACPI
>> +/* Set up the IOMMU */
>> +static int __init arm_smmu_acpi_init(const void *data)
>> +{
>> +    int rc;
>> +
>> +    rc = arm_smmu_device_probe((struct device *)data);
>> +    if (rc)
>> +        return rc;
>> +
>> +    iommu_set_ops(&arm_smmu_iommu_ops);
>> +    return 0;
>> +}
>> +
>> +ACPI_DEVICE_START(asmmuv3, "ARM SMMU V3", DEVICE_IOMMU)
>> +    .class_type = ACPI_IORT_NODE_SMMU_V3,
>> +    .init = arm_smmu_acpi_init,
>> +ACPI_DEVICE_END
>> +
>> +#endif
>> diff --git a/xen/include/xen/linux_compat.h 
>> b/xen/include/xen/linux_compat.h
>> new file mode 100644
>> index 0000000000..8037be0a3e
>> --- /dev/null
>> +++ b/xen/include/xen/linux_compat.h
>> @@ -0,0 +1,84 @@
>> +/****************************************************************************** 
>>
>> + * include/xen/linux_compat.h
>> + *
>> + * Compatibility defines for porting code from Linux to Xen
>> + *
>> + * Copyright (c) 2017 Linaro Limited
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#ifndef __XEN_LINUX_COMPAT_H__
>> +#define __XEN_LINUX_COMPAT_H__
>> +
>> +#include <asm/types.h>
>> +
>> +typedef paddr_t phys_addr_t;
>> +typedef paddr_t dma_addr_t;
>> +
>> +typedef unsigned int gfp_t;
>> +#define GFP_KERNEL 0
>> +#define __GFP_ZERO 0x01U
>> +
>> +/* Helpers for IRQ functions */
>> +#define free_irq release_irq
>> +
>> +enum irqreturn {
>> +    IRQ_NONE,
>> +    IRQ_HANDLED,
>> +    IRQ_WAKE_THREAD,
>> +};
>> +
>> +typedef enum irqreturn irqreturn_t;
>> +
>> +/* Device logger functions */
>> +#define dev_dbg(dev, fmt, ...) printk(XENLOG_DEBUG fmt, ## __VA_ARGS__)
>> +#define dev_notice(dev, fmt, ...) printk(XENLOG_INFO fmt, ## 
>> __VA_ARGS__)
>> +#define dev_warn(dev, fmt, ...) printk(XENLOG_WARNING fmt, ## 
>> __VA_ARGS__)
>> +#define dev_err(dev, fmt, ...) printk(XENLOG_ERR fmt, ## __VA_ARGS__)
>> +#define dev_info(dev, fmt, ...) printk(XENLOG_INFO fmt, ## __VA_ARGS__)
>> +
>> +#define dev_err_ratelimited(dev, fmt, ...)                  \
>> +     printk(XENLOG_ERR fmt, ## __VA_ARGS__)
>> +
>> +#define dev_name(dev) dt_node_full_name(dev_to_dt(dev))
>> +
>> +/* Alias to Xen allocation helpers */
>> +#define kfree xfree
>> +#define kmalloc(size, flags) ({\
>> +    void *__ret_alloc = NULL; \
>> +    if (flags & __GFP_ZERO) \
>> +        __ret_alloc = _xzalloc(size, sizeof(void *)); \
>> +    else \
>> +        __ret_alloc = _xmalloc(size, sizeof(void *)); \
>> +    __ret_alloc; \
>> +})
>> +#define kzalloc(size, flags)        _xzalloc(size, sizeof(void *))
>> +#define devm_kzalloc(dev, size, flags)  _xzalloc(size, sizeof(void *))
>> +#define kmalloc_array(size, n, flags) ({\
>> +    void *__ret_alloc = NULL; \
>> +    if (flags & __GFP_ZERO) \
>> +        __ret_alloc = _xzalloc_array(size, sizeof(void *), n); \
>> +    else \
>> +        __ret_alloc = _xmalloc_array(size, sizeof(void *), n); \
>> +    __ret_alloc; \
>> +})
>> +
>> +/* Alias to Xen time functions */
>> +#define ktime_t s_time_t
>> +#define ktime_get()             (NOW())
>> +#define ktime_add_us(t,i)       (t + MICROSECS(i))
>> +#define ktime_compare(t,i)      (t > (i))
>> +
>> +#endif /* __XEN_LINUX_COMPAT_H__ */
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xenproject.org
> https://lists.xenproject.org/mailman/listinfo/xen-devel

On 04/19/2018 04:24 PM, Manish Jaggi wrote:
> Sorry for top posting,
>
> is someone working on the comments on this patch?
>
> -Manish
>
If no one is working this code anymore, I would like to pick it up and 
continue maintaining it.
Is it fine with all?

-Regards
Manish
>
> On 03/10/2018 11:23 PM, Manish Jaggi wrote:
>> Hi Sameer,
>>
>>
>> On 02/09/2018 08:40 AM, Sameer Goel wrote:
>>> This driver follows an approach similar to smmu driver. The intent here
>>> is to reuse as much Linux code as possible.
>>> - Glue code has been introduced to bridge the API calls.
>>> - Called Linux functions from the Xen IOMMU function calls.
>>> - Xen modifications are preceded by /*Xen: comment */
>>> - xen/linux_compat: Add a Linux compat header
>>>    For porting files directly from Linux it is useful to have a 
>>> function mapping
>>>    definitions from Linux to Xen. This file adds common API 
>>> functions and
>>>    other defines that are needed for porting arm SMMU drivers.
>>>
>>> Signed-off-by: Sameer Goel <sameer.goel@linaro.org>
>>> ---
>>>   xen/arch/arm/p2m.c                    |   1 +
>>>   xen/drivers/Kconfig                   |   2 +
>>>   xen/drivers/passthrough/arm/Kconfig   |   8 +
>>>   xen/drivers/passthrough/arm/Makefile  |   1 +
>>>   xen/drivers/passthrough/arm/smmu-v3.c | 892 
>>> ++++++++++++++++++++++++++++++++--
>>>   xen/include/xen/linux_compat.h        |  84 ++++
>>>   6 files changed, 959 insertions(+), 29 deletions(-)
>>>   create mode 100644 xen/drivers/passthrough/arm/Kconfig
>>>   create mode 100644 xen/include/xen/linux_compat.h
>>>
>>> diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
>>> index 65e8b9c6ea..fef7605fd6 100644
>>> --- a/xen/arch/arm/p2m.c
>>> +++ b/xen/arch/arm/p2m.c
>>> @@ -1460,6 +1460,7 @@ err:
>>>   static void __init setup_virt_paging_one(void *data)
>>>   {
>>>       unsigned long val = (unsigned long)data;
>>> +    /* SMMUv3 S2 cfg vtcr reuses the following value */
>>>       WRITE_SYSREG32(val, VTCR_EL2);
>>>       isb();
>>>   }
>>> diff --git a/xen/drivers/Kconfig b/xen/drivers/Kconfig
>>> index bc3a54f0ea..612655386d 100644
>>> --- a/xen/drivers/Kconfig
>>> +++ b/xen/drivers/Kconfig
>>> @@ -12,4 +12,6 @@ source "drivers/pci/Kconfig"
>>>     source "drivers/video/Kconfig"
>>>   +source "drivers/passthrough/arm/Kconfig"
>>> +
>>>   endmenu
>>> diff --git a/xen/drivers/passthrough/arm/Kconfig 
>>> b/xen/drivers/passthrough/arm/Kconfig
>>> new file mode 100644
>>> index 0000000000..cda899f608
>>> --- /dev/null
>>> +++ b/xen/drivers/passthrough/arm/Kconfig
>>> @@ -0,0 +1,8 @@
>>> +
>>> +config ARM_SMMU_v3
>>> +    bool "ARM SMMUv3 Support"
>>> +    depends on ARM_64
>>> +    help
>>> +     Support for implementations of the ARM System MMU architecture
>>> +     version 3.
>>> +
>>> diff --git a/xen/drivers/passthrough/arm/Makefile 
>>> b/xen/drivers/passthrough/arm/Makefile
>>> index f4cd26e15d..e14732b55c 100644
>>> --- a/xen/drivers/passthrough/arm/Makefile
>>> +++ b/xen/drivers/passthrough/arm/Makefile
>>> @@ -1,2 +1,3 @@
>>>   obj-y += iommu.o
>>>   obj-y += smmu.o
>>> +obj-$(CONFIG_ARM_SMMU_v3) += smmu-v3.o
>>> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c 
>>> b/xen/drivers/passthrough/arm/smmu-v3.c
>>> index e67ba6c40f..f43485fe6e 100644
>>> --- a/xen/drivers/passthrough/arm/smmu-v3.c
>>> +++ b/xen/drivers/passthrough/arm/smmu-v3.c
>>> @@ -18,28 +18,414 @@
>>>    * Author: Will Deacon <will.deacon@arm.com>
>>>    *
>>>    * This driver is powered by bad coffee and bombay mix.
>>> + *
>>> + *
>>> + * Based on Linux drivers/iommu/arm-smmu-v3.c
>>> + * => commit 7aa8619a66aea52b145e04cbab4f8d6a4e5f3f3b
>>> + *
>>> + * Xen modifications:
>>> + * Sameer Goel <sameer.goel@linaro.org>
>>> + * Copyright (C) 2017, The Linux Foundation, All rights reserved.
>>> + *
>>> + */
>>> +
>>> +#include <xen/acpi.h>
>>> +#include <xen/config.h>
>>> +#include <xen/delay.h>
>>> +#include <xen/errno.h>
>>> +#include <xen/err.h>
>>> +#include <xen/irq.h>
>>> +#include <xen/lib.h>
>>> +#include <xen/linux_compat.h>
>>> +#include <xen/list.h>
>>> +#include <xen/mm.h>
>>> +#include <xen/rbtree.h>
>>> +#include <xen/sched.h>
>>> +#include <xen/sizes.h>
>>> +#include <xen/vmap.h>
>>> +#include <acpi/acpi_iort.h>
>>> +#include <asm/atomic.h>
>>> +#include <asm/device.h>
>>> +#include <asm/io.h>
>>> +#include <asm/platform.h>
>>> +
>>> +/* Alias to Xen device tree helpers */
>>> +#define device_node dt_device_node
>>> +#define of_phandle_args dt_phandle_args
>>> +#define of_device_id dt_device_match
>>> +#define of_match_node dt_match_node
>>> +#define of_property_read_u32(np, pname, out) 
>>> (!dt_property_read_u32(np, pname, out))
>>> +#define of_property_read_bool dt_property_read_bool
>>> +#define of_parse_phandle_with_args dt_parse_phandle_with_args
>>> +
>>> +/* Xen: Helpers to get device MMIO and IRQs */
>>> +struct resource {
>>> +    u64 addr;
>>> +    u64 size;
>>> +    unsigned int type;
>>> +};
>>> +
>>> +#define resource_size(res) ((res)->size)
>>> +
>>> +#define platform_device device
>>> +
>>> +#define IORESOURCE_MEM 0
>>> +#define IORESOURCE_IRQ 1
>>> +
>>> +static struct resource *platform_get_resource(struct 
>>> platform_device *pdev,
>>> +                          unsigned int type,
>>> +                          unsigned int num)
>>> +{
>>> +    /*
>>> +     * The resource is only used between 2 calls of 
>>> platform_get_resource.
>>> +     * It's quite ugly but it's avoid to add too much code in the part
>>> +     * imported from Linux
>>> +     */
>>> +    static struct resource res;
>>> +    struct acpi_iort_node *iort_node;
>>> +    struct acpi_iort_smmu_v3 *node_smmu_data;
>>> +    int ret = 0;
>>> +
>>> +    res.type = type;
>>> +
>>> +    switch (type) {
>>> +    case IORESOURCE_MEM:
>>> +        if (pdev->type == DEV_ACPI) {
>>> +            ret = 1;
>>> +            iort_node = pdev->acpi_node;
>>> +            node_smmu_data =
>>> +                (struct acpi_iort_smmu_v3 *)iort_node->node_data;
>>> +
>>> +            if (node_smmu_data != NULL) {
>>> +                res.addr = node_smmu_data->base_address;
>>> +                res.size = SZ_128K;
>>> +                ret = 0;
>>> +            }
>>> +        } else {
>>> +            ret = dt_device_get_address(dev_to_dt(pdev), num,
>>> +                            &res.addr, &res.size);
>>> +        }
>>> +
>>> +        return ((ret) ? NULL : &res);
>>> +
>>> +    case IORESOURCE_IRQ:
>>> +        /* ACPI case not implemented as there is no use case for it */
>>> +        ret = platform_get_irq(dev_to_dt(pdev), num);
>>> +
>>> +        if (ret < 0)
>>> +            return NULL;
>>> +
>>> +        res.addr = ret;
>>> +        res.size = 1;
>>> +
>>> +        return &res;
>>> +
>>> +    default:
>>> +        return NULL;
>>> +    }
>>> +}
>>> +
>>> +static int platform_get_irq_byname(struct platform_device *pdev, 
>>> const char *name)
>>> +{
>>> +    const struct dt_property *dtprop;
>>> +    struct acpi_iort_node *iort_node;
>>> +    struct acpi_iort_smmu_v3 *node_smmu_data;
>>> +    int ret = 0;
>>> +
>>> +    if (pdev->type == DEV_ACPI) {
>>> +        iort_node = pdev->acpi_node;
>>> +        node_smmu_data = (struct acpi_iort_smmu_v3 
>>> *)iort_node->node_data;
>>> +
>>> +        if (node_smmu_data != NULL) {
>>> +            if (!strcmp(name, "eventq"))
>>> +                ret = node_smmu_data->event_gsiv;
>>> +            else if (!strcmp(name, "priq"))
>>> +                ret = node_smmu_data->pri_gsiv;
>>> +            else if (!strcmp(name, "cmdq-sync"))
>>> +                ret = node_smmu_data->sync_gsiv;
>>> +            else if (!strcmp(name, "gerror"))
>>> +                ret = node_smmu_data->gerr_gsiv;
>>> +            else
>>> +                ret = -EINVAL;
>>> +        }
>>> +    } else {
>>> +        dtprop = dt_find_property(dev_to_dt(pdev), 
>>> "interrupt-names", NULL);
>>> +        if (!dtprop)
>>> +            return -EINVAL;
>>> +
>>> +        if (!dtprop->value)
>>> +            return -ENODATA;
>>> +    }
>>> +
>>> +    return ret;
>>> +}
>>> +
>>> +/*
>>> + * Xen: Helpers for DMA allocation. Just the function name is 
>>> reused for
>>> + * porting code these allocation are not managed allocations
>>>    */
>>>   -#include <linux/acpi.h>
>>> -#include <linux/acpi_iort.h>
>>> -#include <linux/delay.h>
>>> -#include <linux/dma-iommu.h>
>>> -#include <linux/err.h>
>>> -#include <linux/interrupt.h>
>>> -#include <linux/iommu.h>
>>> -#include <linux/iopoll.h>
>>> -#include <linux/module.h>
>>> -#include <linux/msi.h>
>>> -#include <linux/of.h>
>>> -#include <linux/of_address.h>
>>> -#include <linux/of_iommu.h>
>>> -#include <linux/of_platform.h>
>>> -#include <linux/pci.h>
>>> -#include <linux/platform_device.h>
>>> -
>>> -#include <linux/amba/bus.h>
>>> -
>>> -#include "io-pgtable.h"
>>> +static void *dmam_alloc_coherent(struct device *dev, size_t size,
>>> +               dma_addr_t *dma_handle, gfp_t gfp)
>>> +{
>>> +    void *vaddr;
>>> +    unsigned long alignment = size;
>>> +
>>> +    /*
>>> +     * _xzalloc requires that the (align & (align -1)) = 0. Most of 
>>> the
>>> +     * allocations in SMMU code should send the right value for 
>>> size. In
>>> +     * case this is not true print a warning and align to the size 
>>> of a
>>> +     * (void *)
>>> +     */
>>> +    if (size & (size - 1)) {
>>> +        dev_warn(dev, "Fixing alignment for the DMA buffer\n");
>>> +        alignment = sizeof(void *);
>>> +    }
>>> +
>>> +    vaddr = _xzalloc(size, alignment);
>>> +    if (!vaddr) {
>>> +        dev_err(dev, "DMA allocation failed\n");
>>> +        return NULL;
>>> +    }
>>> +
>>> +    *dma_handle = virt_to_maddr(vaddr);
>>> +
>>> +    return vaddr;
>>> +}
>>> +
>>> +
>>> +static void dmam_free_coherent(struct device *dev, size_t size, 
>>> void *vaddr,
>>> +            dma_addr_t dma_handle)
>>> +{
>>> +    xfree(vaddr);
>>> +}
>>> +
>>> +/* Xen: Stub out DMA domain related functions */
>>> +#define iommu_get_dma_cookie(dom) 0
>>> +#define iommu_put_dma_cookie(dom)
>>> +
>>> +/* Xen: Stub out module param related function */
>>> +#define module_param_named(a, b, c, d)
>>> +#define MODULE_PARM_DESC(a, b)
>>> +
>>> +#define dma_set_mask_and_coherent(d, b) 0
>>> +
>>> +#define of_dma_is_coherent(n) 0
>>> +
>>> +#define MODULE_DEVICE_TABLE(type, name)
>>> +
>>> +static void __iomem *devm_ioremap_resource(struct device *dev,
>>> +                       struct resource *res)
>>> +{
>>> +    void __iomem *ptr;
>>> +
>>> +    if (!res || res->type != IORESOURCE_MEM) {
>>> +        dev_err(dev, "Invalid resource\n");
>>> +        return ERR_PTR(-EINVAL);
>>> +    }
>>> +
>>> +    ptr = ioremap_nocache(res->addr, res->size);
>>> +    if (!ptr) {
>>> +        dev_err(dev,
>>> +            "ioremap failed (addr 0x%"PRIx64" size 0x%"PRIx64")\n",
>>> +            res->addr, res->size);
>>> +        return ERR_PTR(-ENOMEM);
>>> +    }
>>> +
>>> +    return ptr;
>>> +}
>>> +
>>> +/* Xen: Compatibility define for iommu_domain_geometry.*/
>>> +struct iommu_domain_geometry {
>>> +    dma_addr_t aperture_start; /* First address that can be 
>>> mapped    */
>>> +    dma_addr_t aperture_end;   /* Last address that can be 
>>> mapped     */
>>> +    bool force_aperture;       /* DMA only allowed in mappable 
>>> range? */
>>> +};
>>> +
>>> +
>>> +/* Xen: Type definitions for iommu_domain */
>>> +#define IOMMU_DOMAIN_UNMANAGED 0
>>> +#define IOMMU_DOMAIN_DMA 1
>>> +#define IOMMU_DOMAIN_IDENTITY 2
>>> +
>>> +/* Xen: Dummy iommu_domain */
>>> +struct iommu_domain {
>>> +    /* Runtime SMMU configuration for this iommu_domain */
>>> +    struct arm_smmu_domain        *priv;
>>> +    unsigned int type;
>>> +
>>> +    /* Dummy compatibility defines */
>>> +    unsigned long pgsize_bitmap;
>>> +    struct iommu_domain_geometry geometry;
>>> +
>>> +    atomic_t ref;
>>> +    /*
>>> +     * Used to link iommu_domain contexts for a same domain.
>>> +     * There is at least one per-SMMU to used by the domain.
>>> +     */
>>> +    struct list_head        list;
>>> +};
>>> +
>>> +/* Xen: Describes information required for a Xen domain */
>>> +struct arm_smmu_xen_domain {
>>> +    spinlock_t            lock;
>>> +    /* List of iommu domains associated to this domain */
>>> +    struct list_head        contexts;
>>> +};
>>> +
>>> +/*
>>> + * Xen: Information about each device stored in dev->archdata.iommu
>>> + *
>>> + * The dev->archdata.iommu stores the iommu_domain (runtime 
>>> configuration of
>>> + * the SMMU).
>>> + */
>>> +struct arm_smmu_xen_device {
>>> +    struct iommu_domain *domain;
>>> +};
>>> +
>>> +/*
>>> + * Xen: io_pgtable compatibility defines.
>>> + * Most of these are to port in the S1 translation code as is.
>>> + */
>>> +struct io_pgtable_ops {
>>> +};
>>> +
>>> +struct iommu_gather_ops {
>>> +    void (*tlb_flush_all)(void *cookie);
>>> +    void (*tlb_add_flush)(unsigned long iova, size_t size, size_t 
>>> granule,
>>> +                  bool leaf, void *cookie);
>>> +    void (*tlb_sync)(void *cookie);
>>> +};
>>> +
>>> +struct io_pgtable_cfg {
>>> +    /*
>>> +     * IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE 
>>> bits in
>>> +     *    stage 1 PTEs, for hardware which insists on validating them
>>> +     *    even in    non-secure state where they should normally be 
>>> ignored.
>>> +     *
>>> +     * IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, 
>>> IOMMU_WRITE and
>>> +     *    IOMMU_NOEXEC flags and map everything with full access, for
>>> +     *    hardware which does not implement the permissions of a given
>>> +     *    format, and/or requires some format-specific default value.
>>> +     *
>>> +     * IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching 
>>> invalid
>>> +     *    (unmapped) entries but the hardware might do so anyway, 
>>> perform
>>> +     *    TLB maintenance when mapping as well as when unmapping.
>>> +     *
>>> +     * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
>>> +     *    PTEs, for Mediatek IOMMUs which treat it as a 33rd 
>>> address bit
>>> +     *    when the SoC is in "4GB mode" and they can only access 
>>> the high
>>> +     *    remap of DRAM (0x1_00000000 to 0x1_ffffffff).
>>> +     *
>>> +     * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will 
>>> only ever
>>> +     *    be accessed by a fully cache-coherent IOMMU or CPU (e.g. 
>>> for a
>>> +     *    software-emulated IOMMU), such that pagetable updates 
>>> need not
>>> +     *    be treated as explicit DMA data.
>>> +     */
>>> +    #define IO_PGTABLE_QUIRK_ARM_NS        BIT(0)
>>> +    #define IO_PGTABLE_QUIRK_NO_PERMS    BIT(1)
>>> +    #define IO_PGTABLE_QUIRK_TLBI_ON_MAP    BIT(2)
>>> +    #define IO_PGTABLE_QUIRK_ARM_MTK_4GB    BIT(3)
>>> +    #define IO_PGTABLE_QUIRK_NO_DMA        BIT(4)
>>> +    unsigned long            quirks;
>>> +    unsigned long            pgsize_bitmap;
>>> +    unsigned int            ias;
>>> +    unsigned int            oas;
>>> +    const struct iommu_gather_ops    *tlb;
>>> +    struct device            *iommu_dev;
>>> +
>>> +    /* Low-level data specific to the table format */
>>> +    union {
>>> +        struct {
>>> +            u64    ttbr[2];
>>> +            u64    tcr;
>>> +            u64    mair[2];
>>> +        } arm_lpae_s1_cfg;
>>> +
>>> +        struct {
>>> +            u64    vttbr;
>>> +            u64    vtcr;
>>> +        } arm_lpae_s2_cfg;
>>> +
>>> +        struct {
>>> +            u32    ttbr[2];
>>> +            u32    tcr;
>>> +            u32    nmrr;
>>> +            u32    prrr;
>>> +        } arm_v7s_cfg;
>>> +    };
>>> +};
>>> +
>>> +enum io_pgtable_fmt {
>>> +    ARM_32_LPAE_S1,
>>> +    ARM_32_LPAE_S2,
>>> +    ARM_64_LPAE_S1,
>>> +    ARM_64_LPAE_S2,
>>> +    ARM_V7S,
>>> +    IO_PGTABLE_NUM_FMTS,
>>> +};
>>> +
>>> +/*
>>> + * Xen: The pgtable_ops are used by the S1 translations, so return 
>>> the dummy
>>> + * address.
>>> + */
>>> +#define alloc_io_pgtable_ops(f, c, o) ((struct io_pgtable_ops *)0x0)
>> Is this correct? it will make the caller null check fail
>>> +#define free_io_pgtable_ops(o)
>>> +
>>> +/* Xen: Define wrapper for requesting IRQs */
>>> +#define IRQF_ONESHOT 0
>>> +
>>> +typedef void (*irq_handler_t)(int, void *, struct cpu_user_regs *);
>>> +
>>> +static inline int devm_request_irq(struct device *dev, unsigned int 
>>> irq,
>>> +                   irq_handler_t handler, unsigned long irqflags,
>>> +                   const char *devname, void *dev_id)
>>> +{
>>> +    /*
>>> +     * SMMUv3 implementation can support wired interrupt outputs 
>>> that are
>>> +     * edge-triggered. Set the irq type as per the spec.
>>> +     */
>>> +    irq_set_type(irq, IRQ_TYPE_EDGE_BOTH);
>>> +    return request_irq(irq, irqflags, handler, devname, dev_id);
>>> +}
>>> +
>>> +/*
>>> + * Xen does not have a concept of threaded irq, but eventually we 
>>> can use
>>> + * tasklets to optimize the following function.
>>> + */
>>> +int devm_request_threaded_irq(struct device *dev, unsigned int irq, 
>>> irq_handler_t handler,
>>> +                  irq_handler_t thread_fn, unsigned long irqflags,
>>> +                  const char *devname, void *dev_id)
>>> +{
>>> +    return devm_request_irq(dev, irq, thread_fn, irqflags, devname, 
>>> dev_id);
>>> +}
>>> +
>>> +/* Xen: The mutex is used only during initialization so the 
>>> typecast is safe */
>>> +#define mutex spinlock
>>> +#define mutex_init spin_lock_init
>>> +#define mutex_lock spin_lock
>>> +#define mutex_unlock spin_unlock
>>> +
>>> +#define readx_poll_timeout(op, addr, val, cond, sleep_us, 
>>> timeout_us) \
>>> +({ \
>>> +    s_time_t deadline = NOW() + MICROSECS(timeout_us); \
>>> +    for (;;) { \
>>> +        (val) = op(addr); \
>>> +        if (cond) \
>>> +            break; \
>>> +        if (NOW() > deadline) { \
>>> +            (val) = op(addr); \
>>> +            break; \
>>> +        } \
>>> +    udelay(sleep_us); \
>>> +    } \
>>> +    (cond) ? 0 : -ETIMEDOUT; \
>>> +})
>>> +
>>> +#define readl_relaxed_poll_timeout(addr, val, cond, delay_us, 
>>> timeout_us) \
>>> +    readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, 
>>> timeout_us)
>>> +
>>> +#define VA_BITS 0 /* Only needed for S1 translations */
>>>     /* MMIO registers */
>>>   #define ARM_SMMU_IDR0            0x0
>>> @@ -433,6 +819,7 @@ enum pri_resp {
>>>       PRI_RESP_SUCC,
>>>   };
>>>   +#if 0 /* Xen: No MSI support in this iteration */
>>>   enum arm_smmu_msi_index {
>>>       EVTQ_MSI_INDEX,
>>>       GERROR_MSI_INDEX,
>>> @@ -457,6 +844,7 @@ static phys_addr_t 
>>> arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
>>>           ARM_SMMU_PRIQ_IRQ_CFG2,
>>>       },
>>>   };
>>> +#endif
>>>     struct arm_smmu_cmdq_ent {
>>>       /* Common fields */
>>> @@ -561,6 +949,8 @@ struct arm_smmu_s2_cfg {
>>>       u16                vmid;
>>>       u64                vttbr;
>>>       u64                vtcr;
>>> +    /* Xen: Domain associated to this configuration */
>>> +    struct domain            *domain;
>>>   };
>>>     struct arm_smmu_strtab_ent {
>>> @@ -635,9 +1025,21 @@ struct arm_smmu_device {
>>>       struct arm_smmu_strtab_cfg    strtab_cfg;
>>>         /* IOMMU core code handle */
>>> +#if 0 /*Xen: Generic iommu_device ref not needed here */
>>>       struct iommu_device        iommu;
>>> +#endif
>>> +    /* Xen: Need to keep a list of SMMU devices */
>>> +    struct list_head                devices;
>>>   };
>>>   +/* Xen: Keep a list of devices associated with this driver */
>>> +static DEFINE_SPINLOCK(arm_smmu_devices_lock);
>>> +static LIST_HEAD(arm_smmu_devices);
>>> +/* Xen: Helper for finding a device using fwnode */
>>> +static
>>> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle 
>>> *fwnode);
>>> +
>>> +
>>>   /* SMMU private data for each master */
>>>   struct arm_smmu_master_data {
>>>       struct arm_smmu_device        *smmu;
>>> @@ -1232,7 +1634,7 @@ static void arm_smmu_handle_ppr(struct 
>>> arm_smmu_device *smmu, u64 *evt)
>>>         dev_info(smmu->dev, "unexpected PRI request received:\n");
>>>       dev_info(smmu->dev,
>>> -         "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at 
>>> iova 0x%016llx\n",
>>> +         "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at 
>>> iova %#" PRIx64 "\n",
>>>            sid, ssid, grpid, last ? "L" : "",
>>>            evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",
>>>            evt[0] & PRIQ_0_PERM_READ ? "R" : "",
>>> @@ -1346,6 +1748,8 @@ static irqreturn_t 
>>> arm_smmu_combined_irq_handler(int irq, void *dev)
>>>   {
>>>       arm_smmu_gerror_handler(irq, dev);
>>>       arm_smmu_cmdq_sync_handler(irq, dev);
>>> +    /*Xen: No threaded irq. So call the required function from here */
>>> +    arm_smmu_combined_irq_thread(irq, dev);
>>>       return IRQ_WAKE_THREAD;
>>>   }
>>>   @@ -1358,6 +1762,46 @@ static void __arm_smmu_tlb_sync(struct 
>>> arm_smmu_device *smmu)
>>>       arm_smmu_cmdq_issue_cmd(smmu, &cmd);
>>>   }
>>>   +/*
>>> + * Xen: Define the IRQ handlers for xen. The linux functions would be
>>> + * modified to use the functions defined in the following code.
>>> + */
>>> +static void arm_smmu_evtq_thread_xen(int irq, void *dev,
>>> +                       struct cpu_user_regs *regs)
>>> +{
>>> +    arm_smmu_evtq_thread(irq, dev);
>>> +}
>>> +
>>> +static void arm_smmu_priq_thread_xen(int irq, void *dev,
>>> +                       struct cpu_user_regs *regs)
>>> +{
>>> +    arm_smmu_priq_thread(irq, dev);
>>> +}
>>> +
>>> +static void arm_smmu_cmdq_sync_handler_xen(int irq, void *dev,
>>> +                       struct cpu_user_regs *regs)
>>> +{
>>> +    arm_smmu_cmdq_sync_handler(irq, dev);
>>> +}
>>> +
>>> +static void arm_smmu_gerror_handler_xen(int irq, void *dev,
>>> +                       struct cpu_user_regs *regs)
>>> +{
>>> +    arm_smmu_gerror_handler(irq, dev);
>>> +}
>>> +
>>> +static void arm_smmu_combined_irq_handler_xen(int irq, void *dev,
>>> +                       struct cpu_user_regs *regs)
>>> +{
>>> +    arm_smmu_combined_irq_handler(irq, dev);
>>> +}
>>> +
>>> +#define arm_smmu_evtq_thread arm_smmu_evtq_thread_xen
>>> +#define arm_smmu_priq_thread arm_smmu_priq_thread_xen
>>> +#define arm_smmu_cmdq_sync_handler arm_smmu_cmdq_sync_handler_xen
>>> +#define arm_smmu_gerror_handler arm_smmu_gerror_handler_xen
>>> +#define arm_smmu_combined_irq_handler 
>>> arm_smmu_combined_irq_handler_xen
>>> +
>>>   static void arm_smmu_tlb_sync(void *cookie)
>>>   {
>>>       struct arm_smmu_domain *smmu_domain = cookie;
>>> @@ -1415,6 +1859,7 @@ static const struct iommu_gather_ops 
>>> arm_smmu_gather_ops = {
>>>       .tlb_sync    = arm_smmu_tlb_sync,
>>>   };
>>>   +#if 0 /*Xen: Unused functionality */
>>>   /* IOMMU API */
>>>   static bool arm_smmu_capable(enum iommu_cap cap)
>>>   {
>>> @@ -1427,6 +1872,7 @@ static bool arm_smmu_capable(enum iommu_cap cap)
>>>           return false;
>>>       }
>>>   }
>>> +#endif
>>>     static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
>>>   {
>>> @@ -1546,9 +1992,16 @@ static int arm_smmu_domain_finalise_s2(struct 
>>> arm_smmu_domain *smmu_domain,
>>>       if (vmid < 0)
>>>           return vmid;
>>>   -    cfg->vmid    = (u16)vmid;
>>> -    cfg->vttbr    = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
>>> -    cfg->vtcr    = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
>>> +    /*
>>> +     * Xen: Get the ttbr and vtcr values
>>> +     * vttbr: This is a shared value with the domain page table
>>> +     * vtcr: The TCR settings are the same as CPU since the page
>>> +     * tables are shared
>>> +     */
>>> +
>>> +    cfg->vmid    = vmid;
>>> +    cfg->vttbr    = page_to_maddr(cfg->domain->arch.p2m.root);
>>> +    cfg->vtcr    = READ_SYSREG32(VTCR_EL2) & STRTAB_STE_2_VTCR_MASK;
>>>       return 0;
>>>   }
>>>   @@ -1604,6 +2057,7 @@ static int arm_smmu_domain_finalise(struct 
>>> iommu_domain *domain)
>>>       if (smmu->features & ARM_SMMU_FEAT_COHERENCY)
>>>           pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_NO_DMA;
>>>   +    /* Xen: pgtbl_ops gets an invalid address */
>>>       pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
>>>       if (!pgtbl_ops)
>>>           return -ENOMEM;
>> Will this not fail ?
>>> @@ -1721,6 +2175,7 @@ out_unlock:
>>>       return ret;
>>>   }
>>>   +#if 0 /* Xen: Unused functionality */
>>>   static int arm_smmu_map(struct iommu_domain *domain, unsigned long 
>>> iova,
>>>               phys_addr_t paddr, size_t size, int prot)
>>>   {
>>> @@ -1772,6 +2227,7 @@ struct arm_smmu_device 
>>> *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
>>>       put_device(dev);
>>>       return dev ? dev_get_drvdata(dev) : NULL;
>>>   }
>>> +#endif
>>>     static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, 
>>> u32 sid)
>>>   {
>>> @@ -1783,7 +2239,14 @@ static bool arm_smmu_sid_in_range(struct 
>>> arm_smmu_device *smmu, u32 sid)
>>>       return sid < limit;
>>>   }
>>>   +/* Xen: Unused */
>>> +#if 0
>>>   static struct iommu_ops arm_smmu_ops;
>>> +#endif
>>> +
>>> +/* Xen: Redefine arm_smmu_ops to what fwspec should evaluate */
>>> +static const struct iommu_ops arm_smmu_iommu_ops;
>>> +#define arm_smmu_ops arm_smmu_iommu_ops
>>>     static int arm_smmu_add_device(struct device *dev)
>>>   {
>>> @@ -1791,8 +2254,11 @@ static int arm_smmu_add_device(struct device 
>>> *dev)
>>>       struct arm_smmu_device *smmu;
>>>       struct arm_smmu_master_data *master;
>>>       struct iommu_fwspec *fwspec = dev->iommu_fwspec;
>>> +#if 0 /*Xen: iommu_group is not needed */
>>>       struct iommu_group *group;
>>> +#endif
>>>   +    /* Xen: fwspec->ops are not needed */
>>>       if (!fwspec || fwspec->ops != &arm_smmu_ops)
>>>           return -ENODEV;
>>>       /*
>>> @@ -1830,6 +2296,11 @@ static int arm_smmu_add_device(struct device 
>>> *dev)
>>>           }
>>>       }
>>>   +/*
>>> + * Xen: Do not need an iommu group as the stream data is carried by 
>>> the SMMU
>>> + * master device object
>>> + */
>>> +#if 0
>>>       group = iommu_group_get_for_dev(dev);
>>>       if (!IS_ERR(group)) {
>>>           iommu_group_put(group);
>>> @@ -1837,8 +2308,16 @@ static int arm_smmu_add_device(struct device 
>>> *dev)
>>>       }
>>>         return PTR_ERR_OR_ZERO(group);
>>> +#endif
>>> +    return 0;
>>>   }
>>>   +/*
>>> + * Xen: We can potentially support this function and destroy a 
>>> device. This
>>> + * will be relevant for PCI hotplug. So, will be implemented as 
>>> needed after
>>> + * passthrough support is available.
>>> + */
>>> +#if 0
>>>   static void arm_smmu_remove_device(struct device *dev)
>>>   {
>>>       struct iommu_fwspec *fwspec = dev->iommu_fwspec;
>>> @@ -1974,6 +2453,7 @@ static struct iommu_ops arm_smmu_ops = {
>>>       .put_resv_regions    = arm_smmu_put_resv_regions,
>>>       .pgsize_bitmap        = -1UL, /* Restricted during device 
>>> attach */
>>>   };
>>> +#endif
>>>     /* Probing and initialisation functions */
>>>   static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
>>> @@ -2182,6 +2662,7 @@ static int arm_smmu_update_gbpa(struct 
>>> arm_smmu_device *smmu, u32 set, u32 clr)
>>>                         1, ARM_SMMU_POLL_TIMEOUT_US);
>>>   }
>>>   +#if 0 /* Xen: There is no MSI support as yet */
>>>   static void arm_smmu_free_msis(void *data)
>>>   {
>>>       struct device *dev = data;
>>> @@ -2247,12 +2728,15 @@ static void arm_smmu_setup_msis(struct 
>>> arm_smmu_device *smmu)
>>>       /* Add callback to free MSIs on teardown */
>>>       devm_add_action(dev, arm_smmu_free_msis, dev);
>>>   }
>>> +#endif
>>>     static void arm_smmu_setup_unique_irqs(struct arm_smmu_device 
>>> *smmu)
>>>   {
>>>       int irq, ret;
>>>   +#if 0 /*Xen: Cannot setup msis for now */
>>>       arm_smmu_setup_msis(smmu);
>>> +#endif
>>>         /* Request interrupt lines */
>>>       irq = smmu->evtq.q.irq;
>>> @@ -2316,9 +2800,13 @@ static int arm_smmu_setup_irqs(struct 
>>> arm_smmu_device *smmu)
>>>            * Cavium ThunderX2 implementation doesn't not support unique
>>>            * irq lines. Use single irq line for all the SMMUv3 
>>> interrupts.
>>>            */
>>> -        ret = devm_request_threaded_irq(smmu->dev, irq,
>>> +        /*
>>> +         * Xen: Does not support threaded irqs, so serialise the 
>>> setup.
>>> +         * This is the same for pris and event interrupt lines on 
>>> other
>>> +         * systems
>>> +         */
>>> +        ret = devm_request_irq(smmu->dev, irq,
>>>                       arm_smmu_combined_irq_handler,
>>> -                    arm_smmu_combined_irq_thread,
>>>                       IRQF_ONESHOT,
>>>                       "arm-smmu-v3-combined-irq", smmu);
>>>           if (ret < 0)
>>> @@ -2542,8 +3030,14 @@ static int arm_smmu_device_hw_probe(struct 
>>> arm_smmu_device *smmu)
>>>           smmu->features |= ARM_SMMU_FEAT_STALLS;
>>>       }
>>>   +/*
>>> + * Xen: Block stage 1 translations. By doing this here we do not 
>>> need to set the
>>> + * domain->stage explicitly.
>>> + */
>>> +#if 0
>>>       if (reg & IDR0_S1P)
>>>           smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
>>> +#endif
>>>         if (reg & IDR0_S2P)
>>>           smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
>>> @@ -2616,10 +3110,12 @@ static int arm_smmu_device_hw_probe(struct 
>>> arm_smmu_device *smmu)
>>>       if (reg & IDR5_GRAN4K)
>>>           smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
>>>   +#if 0 /* Xen: SMMU ops do not have a pgsize_bitmap member for Xen */
>>>       if (arm_smmu_ops.pgsize_bitmap == -1UL)
>>>           arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
>>>       else
>>>           arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
>>> +#endif
>>>         /* Output address size */
>>>       switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) {
>>> @@ -2680,7 +3176,8 @@ static int arm_smmu_device_acpi_probe(struct 
>>> platform_device *pdev,
>>>       struct device *dev = smmu->dev;
>>>       struct acpi_iort_node *node;
>>>   -    node = *(struct acpi_iort_node **)dev_get_platdata(dev);
>>> +    /* Xen: Modification to get iort_node */
>>> +    node = (struct acpi_iort_node *)dev->acpi_node;
>>>         /* Retrieve SMMUv3 specific data */
>>>       iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>>> @@ -2703,7 +3200,7 @@ static inline int 
>>> arm_smmu_device_acpi_probe(struct platform_device *pdev,
>>>   static int arm_smmu_device_dt_probe(struct platform_device *pdev,
>>>                       struct arm_smmu_device *smmu)
>>>   {
>>> -    struct device *dev = &pdev->dev;
>>> +    struct device *dev = pdev;
>>>       u32 cells;
>>>       int ret = -EINVAL;
>>>   @@ -2716,6 +3213,7 @@ static int arm_smmu_device_dt_probe(struct 
>>> platform_device *pdev,
>>>         parse_driver_options(smmu);
>>>   +    /* Xen: of_dma_is_coherent is a stub till dt support is 
>>> introduced */
>>>       if (of_dma_is_coherent(dev->of_node))
>>>           smmu->features |= ARM_SMMU_FEAT_COHERENCY;
>>>   @@ -2734,9 +3232,11 @@ static int arm_smmu_device_probe(struct 
>>> platform_device *pdev)
>>>   {
>>>       int irq, ret;
>>>       struct resource *res;
>>> +#if 0 /*Xen: Do not need to setup sysfs */
>>>       resource_size_t ioaddr;
>>> +#endif
>>>       struct arm_smmu_device *smmu;
>>> -    struct device *dev = &pdev->dev;
>>> +    struct device *dev = pdev;/* Xen: dev is ignored */
>>>       bool bypass;
>>>         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
>>> @@ -2763,7 +3263,9 @@ static int arm_smmu_device_probe(struct 
>>> platform_device *pdev)
>>>           dev_err(dev, "MMIO region too small (%pr)\n", res);
>>>           return -EINVAL;
>>>       }
>>> +#if 0 /*Xen: Do not need to setup sysfs */
>>>       ioaddr = res->start;
>>> +#endif
>>>         smmu->base = devm_ioremap_resource(dev, res);
>>>       if (IS_ERR(smmu->base))
>>> @@ -2802,13 +3304,18 @@ static int arm_smmu_device_probe(struct 
>>> platform_device *pdev)
>>>           return ret;
>>>         /* Record our private device structure */
>>> +    /* Xen: SMMU is not treated a a platform device*/
>>> +#if 0
>>>       platform_set_drvdata(pdev, smmu);
>>> +#endif
>>>         /* Reset the device */
>>>       ret = arm_smmu_device_reset(smmu, bypass);
>>>       if (ret)
>>>           return ret;
>>>   +/* Xen: Not creating an IOMMU device list for Xen */
>>> +#if 0
>>>       /* And we're up. Go go go! */
>>>       ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL,
>>>                        "smmu3.%pa", &ioaddr);
>>> @@ -2844,9 +3351,20 @@ static int arm_smmu_device_probe(struct 
>>> platform_device *pdev)
>>>           if (ret)
>>>               return ret;
>>>       }
>>> +#endif
>>> +    /*
>>> +     * Xen: Keep a list of all probed devices. This will be used to 
>>> query
>>> +     * the smmu devices based on the fwnode.
>>> +     */
>>> +    INIT_LIST_HEAD(&smmu->devices);
>>> +    spin_lock(&arm_smmu_devices_lock);
>>> +    list_add(&smmu->devices, &arm_smmu_devices);
>>> +    spin_unlock(&arm_smmu_devices_lock);
>>>       return 0;
>>>   }
>>>   +/* Xen: Unused function */
>>> +#if 0
>>>   static int arm_smmu_device_remove(struct platform_device *pdev)
>>>   {
>>>       struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
>>> @@ -2860,6 +3378,8 @@ static void arm_smmu_device_shutdown(struct 
>>> platform_device *pdev)
>>>   {
>>>       arm_smmu_device_remove(pdev);
>>>   }
>>> +#endif
>>> +
>>>     static const struct of_device_id arm_smmu_of_match[] = {
>>>       { .compatible = "arm,smmu-v3", },
>>> @@ -2867,6 +3387,7 @@ static const struct of_device_id 
>>> arm_smmu_of_match[] = {
>>>   };
>>>   MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
>>>   +#if 0
>>>   static struct platform_driver arm_smmu_driver = {
>>>       .driver    = {
>>>           .name        = "arm-smmu-v3",
>>> @@ -2883,3 +3404,316 @@ IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3", 
>>> NULL);
>>>   MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 
>>> implementations");
>>>   MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
>>>   MODULE_LICENSE("GPL v2");
>>> +#endif
>>> +
>>> +/***** Start of Xen specific code *****/
>>> +
>>> +static int __must_check arm_smmu_iotlb_flush_all(struct domain *d)
>>> +{
>>> +    struct arm_smmu_xen_domain *smmu_domain = dom_iommu(d)->arch.priv;
>>> +    struct iommu_domain *cfg;
>>> +
>>> +    spin_lock(&smmu_domain->lock);
>>> +    list_for_each_entry(cfg, &smmu_domain->contexts, list) {
>>> +        /*
>>> +         * Only invalidate the context when SMMU is present.
>>> +         * This is because the context initialization is delayed
>>> +         * until a master has been added.
>>> +         */
>>> +        if (unlikely(!ACCESS_ONCE(cfg->priv->smmu)))
>>> +            continue;
>>> +        arm_smmu_tlb_inv_context(cfg->priv);
>>> +    }
>>> +    spin_unlock(&smmu_domain->lock);
>>> +    return 0;
>>> +}
>>> +
>>> +static int __must_check arm_smmu_iotlb_flush(struct domain *d,
>>> +                         unsigned long gfn,
>>> +                         unsigned int page_count)
>>> +{
>>> +    return arm_smmu_iotlb_flush_all(d);
>>> +}
>>> +
>>> +static struct iommu_domain *arm_smmu_get_domain(struct domain *d,
>>> +                        struct device *dev)
>>> +{
>>> +    struct iommu_domain *domain;
>>> +    struct arm_smmu_xen_domain *xen_domain;
>>> +    struct arm_smmu_device *smmu;
>>> +    struct arm_smmu_domain *smmu_domain;
>>> +
>>> +    xen_domain = dom_iommu(d)->arch.priv;
>>> +
>>> +    smmu = arm_smmu_get_by_fwnode(dev->iommu_fwspec->iommu_fwnode);
>>> +    if (!smmu)
>>> +        return NULL;
>>> +
>>> +    /*
>>> +     * Loop through the &xen_domain->contexts to locate a context
>>> +     * assigned to this SMMU
>>> +     */
>>> +    list_for_each_entry(domain, &xen_domain->contexts, list) {
>>> +        smmu_domain = to_smmu_domain(domain);
>>> +        if (smmu_domain->smmu == smmu)
>>> +            return domain;
>>> +    }
>>> +
>>> +    return NULL;
>>> +}
>>> +
>>> +static void arm_smmu_destroy_iommu_domain(struct iommu_domain *domain)
>>> +{
>>> +    list_del(&domain->list);
>>> +    arm_smmu_domain_free(domain);
>>> +}
>>> +
>>> +static int arm_smmu_assign_dev(struct domain *d, u8 devfn,
>>> +                   struct device *dev, u32 flag)
>>> +{
>>> +    int ret = 0;
>>> +    struct iommu_domain *domain;
>>> +    struct arm_smmu_xen_domain *xen_domain;
>>> +    struct arm_smmu_domain *arm_smmu;
>>> +
>>> +    xen_domain = dom_iommu(d)->arch.priv;
>>> +
>>> +    if (!dev->archdata.iommu) {
>>> +        dev->archdata.iommu = xzalloc(struct arm_smmu_xen_device);
>>> +        if (!dev->archdata.iommu)
>>> +            return -ENOMEM;
>>> +    }
>>> +
>>> +    ret = arm_smmu_add_device(dev);
>>> +    if (ret)
>>> +        return ret;
>>> +
>>> +    spin_lock(&xen_domain->lock);
>>> +
>>> +    /*
>>> +     * Check to see if an iommu_domain already exists for this xen 
>>> domain
>>> +     * under the same SMMU
>>> +     */
>>> +    domain = arm_smmu_get_domain(d, dev);
>>> +    if (!domain) {
>>> +
>>> +        domain = arm_smmu_domain_alloc(IOMMU_DOMAIN_DMA);
>>> +        if (!domain) {
>>> +            ret = -ENOMEM;
>>> +            goto out;
>>> +        }
>>> +
>>> +        arm_smmu = to_smmu_domain(domain);
>>> +        arm_smmu->s2_cfg.domain = d;
>>> +
>>> +        /* Chain the new context to the domain */
>>> +        list_add(&domain->list, &xen_domain->contexts);
>>> +
>>> +    }
>>> +
>>> +    ret = arm_smmu_attach_dev(domain, dev);
>>> +    if (ret) {
>>> +        if (domain->ref.counter == 0)
>>> +            arm_smmu_destroy_iommu_domain(domain);
>>> +    } else {
>>> +        atomic_inc(&domain->ref);
>>> +    }
>>> +
>>> +out:
>>> +    spin_unlock(&xen_domain->lock);
>>> +    return ret;
>>> +}
>>> +
>>> +static int arm_smmu_deassign_dev(struct domain *d, struct device *dev)
>>> +{
>>> +    struct iommu_domain *domain = arm_smmu_get_domain(d, dev);
>>> +    struct arm_smmu_xen_domain *xen_domain;
>>> +    struct arm_smmu_domain *arm_smmu = to_smmu_domain(domain);
>>> +
>>> +    xen_domain = dom_iommu(d)->arch.priv;
>>> +
>>> +    if (!arm_smmu || arm_smmu->s2_cfg.domain != d) {
>>> +        dev_err(dev, " not attached to domain %d\n", d->domain_id);
>>> +        return -ESRCH;
>>> +    }
>>> +
>>> +    spin_lock(&xen_domain->lock);
>>> +
>>> +    arm_smmu_detach_dev(dev);
>>> +    atomic_dec(&domain->ref);
>>> +
>>> +    if (domain->ref.counter == 0)
>>> +        arm_smmu_destroy_iommu_domain(domain);
>>> +
>>> +    spin_unlock(&xen_domain->lock);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static int arm_smmu_reassign_dev(struct domain *s, struct domain *t,
>>> +                 u8 devfn,  struct device *dev)
>>> +{
>>> +    int ret = 0;
>>> +
>>> +    /* Don't allow remapping on other domain than hwdom */
>>> +    if (t && t != hardware_domain)
>>> +        return -EPERM;
>>> +
>>> +    if (t == s)
>>> +        return 0;
>>> +
>>> +    ret = arm_smmu_deassign_dev(s, dev);
>>> +    if (ret)
>>> +        return ret;
>>> +
>>> +    if (t) {
>>> +        /* No flags are defined for ARM. */
>>> +        ret = arm_smmu_assign_dev(t, devfn, dev, 0);
>>> +        if (ret)
>>> +            return ret;
>>> +    }
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static int arm_smmu_iommu_domain_init(struct domain *d)
>>> +{
>>> +    struct arm_smmu_xen_domain *xen_domain;
>>> +
>>> +    xen_domain = xzalloc(struct arm_smmu_xen_domain);
>>> +    if (!xen_domain)
>>> +        return -ENOMEM;
>>> +
>>> +    spin_lock_init(&xen_domain->lock);
>>> +    INIT_LIST_HEAD(&xen_domain->contexts);
>>> +
>>> +    dom_iommu(d)->arch.priv = xen_domain;
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static void __hwdom_init arm_smmu_iommu_hwdom_init(struct domain *d)
>>> +{
>>> +}
>>> +
>>> +static void arm_smmu_iommu_domain_teardown(struct domain *d)
>>> +{
>>> +    struct arm_smmu_xen_domain *xen_domain = dom_iommu(d)->arch.priv;
>>> +
>>> +    ASSERT(list_empty(&xen_domain->contexts));
>>> +    xfree(xen_domain);
>>> +}
>>> +
>>> +static int __must_check arm_smmu_map_page(struct domain *d, 
>>> unsigned long gfn,
>>> +            unsigned long mfn, unsigned int flags)
>>> +{
>>> +    p2m_type_t t;
>>> +
>>> +    /*
>>> +     * Grant mappings can be used for DMA requests. The dev_bus_addr
>>> +     * returned by the hypercall is the MFN (not the IPA). For device
>>> +     * protected by an IOMMU, Xen needs to add a 1:1 mapping in the 
>>> domain
>>> +     * p2m to allow DMA request to work.
>>> +     * This is only valid when the domain is directed mapped. Hence 
>>> this
>>> +     * function should only be used by gnttab code with gfn == mfn.
>>> +     */
>>> +    BUG_ON(!is_domain_direct_mapped(d));
>>> +    BUG_ON(mfn != gfn);
>>> +
>>> +    /* We only support readable and writable flags */
>>> +    if (!(flags & (IOMMUF_readable | IOMMUF_writable)))
>>> +        return -EINVAL;
>>> +
>>> +    t = (flags & IOMMUF_writable) ? p2m_iommu_map_rw : 
>>> p2m_iommu_map_ro;
>>> +
>>> +    /*
>>> +     * The function guest_physmap_add_entry replaces the current 
>>> mapping
>>> +     * if there is already one...
>>> +     */
>>> +    return guest_physmap_add_entry(d, _gfn(gfn), _mfn(mfn), 0, t);
>>> +}
>>> +
>>> +static int __must_check arm_smmu_unmap_page(struct domain *d, 
>>> unsigned long gfn)
>>> +{
>>> +    /*
>>> +     * This function should only be used by gnttab code when the 
>>> domain
>>> +     * is direct mapped
>>> +     */
>>> +    if (!is_domain_direct_mapped(d))
>>> +        return -EINVAL;
>>> +
>>> +    return guest_physmap_remove_page(d, _gfn(gfn), _mfn(gfn), 0);
>>> +}
>>> +
>>> +static const struct iommu_ops arm_smmu_iommu_ops = {
>>> +    .init = arm_smmu_iommu_domain_init,
>>> +    .hwdom_init = arm_smmu_iommu_hwdom_init,
>>> +    .teardown = arm_smmu_iommu_domain_teardown,
>>> +    .iotlb_flush = arm_smmu_iotlb_flush,
>>> +    .iotlb_flush_all = arm_smmu_iotlb_flush_all,
>>> +    .assign_device = arm_smmu_assign_dev,
>>> +    .reassign_device = arm_smmu_reassign_dev,
>>> +    .map_page = arm_smmu_map_page,
>>> +    .unmap_page = arm_smmu_unmap_page,
>>> +};
>>> +
>>> +static
>>> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle 
>>> *fwnode)
>>> +{
>>> +    struct arm_smmu_device *smmu = NULL;
>>> +
>>> +    spin_lock(&arm_smmu_devices_lock);
>>> +    list_for_each_entry(smmu, &arm_smmu_devices, devices) {
>>> +        if (smmu->dev->fwnode == fwnode)
>>> +            break;
>>> +    }
>>> +    spin_unlock(&arm_smmu_devices_lock);
>>> +
>>> +    return smmu;
>>> +}
>>> +
>>> +static __init int arm_smmu_dt_init(struct dt_device_node *dev,
>>> +                   const void *data)
>>> +{
>>> +    int rc;
>>> +
>>> +    /*
>>> +     * Even if the device can't be initialized, we don't want to
>>> +     * give the SMMU device to dom0.
>>> +     */
>>> +    dt_device_set_used_by(dev, DOMID_XEN);
>>> +
>>> +    rc = arm_smmu_device_probe(dt_to_dev(dev));
>>> +    if (rc)
>>> +        return rc;
>>> +
>>> +    iommu_set_ops(&arm_smmu_iommu_ops);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +DT_DEVICE_START(smmuv3, "ARM SMMU V3", DEVICE_IOMMU)
>>> +    .dt_match = arm_smmu_of_match,
>>> +    .init = arm_smmu_dt_init,
>>> +DT_DEVICE_END
>>> +
>>> +#ifdef CONFIG_ACPI
>>> +/* Set up the IOMMU */
>>> +static int __init arm_smmu_acpi_init(const void *data)
>>> +{
>>> +    int rc;
>>> +
>>> +    rc = arm_smmu_device_probe((struct device *)data);
>>> +    if (rc)
>>> +        return rc;
>>> +
>>> +    iommu_set_ops(&arm_smmu_iommu_ops);
>>> +    return 0;
>>> +}
>>> +
>>> +ACPI_DEVICE_START(asmmuv3, "ARM SMMU V3", DEVICE_IOMMU)
>>> +    .class_type = ACPI_IORT_NODE_SMMU_V3,
>>> +    .init = arm_smmu_acpi_init,
>>> +ACPI_DEVICE_END
>>> +
>>> +#endif
>>> diff --git a/xen/include/xen/linux_compat.h 
>>> b/xen/include/xen/linux_compat.h
>>> new file mode 100644
>>> index 0000000000..8037be0a3e
>>> --- /dev/null
>>> +++ b/xen/include/xen/linux_compat.h
>>> @@ -0,0 +1,84 @@
>>> +/****************************************************************************** 
>>>
>>> + * include/xen/linux_compat.h
>>> + *
>>> + * Compatibility defines for porting code from Linux to Xen
>>> + *
>>> + * Copyright (c) 2017 Linaro Limited
>>> + *
>>> + * This program is free software; you can redistribute it and/or 
>>> modify
>>> + * it under the terms of the GNU General Public License as 
>>> published by
>>> + * the Free Software Foundation; either version 2 of the License, or
>>> + * (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; If not, see 
>>> <http://www.gnu.org/licenses/>.
>>> + */
>>> +
>>> +#ifndef __XEN_LINUX_COMPAT_H__
>>> +#define __XEN_LINUX_COMPAT_H__
>>> +
>>> +#include <asm/types.h>
>>> +
>>> +typedef paddr_t phys_addr_t;
>>> +typedef paddr_t dma_addr_t;
>>> +
>>> +typedef unsigned int gfp_t;
>>> +#define GFP_KERNEL 0
>>> +#define __GFP_ZERO 0x01U
>>> +
>>> +/* Helpers for IRQ functions */
>>> +#define free_irq release_irq
>>> +
>>> +enum irqreturn {
>>> +    IRQ_NONE,
>>> +    IRQ_HANDLED,
>>> +    IRQ_WAKE_THREAD,
>>> +};
>>> +
>>> +typedef enum irqreturn irqreturn_t;
>>> +
>>> +/* Device logger functions */
>>> +#define dev_dbg(dev, fmt, ...) printk(XENLOG_DEBUG fmt, ## 
>>> __VA_ARGS__)
>>> +#define dev_notice(dev, fmt, ...) printk(XENLOG_INFO fmt, ## 
>>> __VA_ARGS__)
>>> +#define dev_warn(dev, fmt, ...) printk(XENLOG_WARNING fmt, ## 
>>> __VA_ARGS__)
>>> +#define dev_err(dev, fmt, ...) printk(XENLOG_ERR fmt, ## __VA_ARGS__)
>>> +#define dev_info(dev, fmt, ...) printk(XENLOG_INFO fmt, ## 
>>> __VA_ARGS__)
>>> +
>>> +#define dev_err_ratelimited(dev, fmt, ...)                  \
>>> +     printk(XENLOG_ERR fmt, ## __VA_ARGS__)
>>> +
>>> +#define dev_name(dev) dt_node_full_name(dev_to_dt(dev))
>>> +
>>> +/* Alias to Xen allocation helpers */
>>> +#define kfree xfree
>>> +#define kmalloc(size, flags) ({\
>>> +    void *__ret_alloc = NULL; \
>>> +    if (flags & __GFP_ZERO) \
>>> +        __ret_alloc = _xzalloc(size, sizeof(void *)); \
>>> +    else \
>>> +        __ret_alloc = _xmalloc(size, sizeof(void *)); \
>>> +    __ret_alloc; \
>>> +})
>>> +#define kzalloc(size, flags)        _xzalloc(size, sizeof(void *))
>>> +#define devm_kzalloc(dev, size, flags)  _xzalloc(size, sizeof(void *))
>>> +#define kmalloc_array(size, n, flags) ({\
>>> +    void *__ret_alloc = NULL; \
>>> +    if (flags & __GFP_ZERO) \
>>> +        __ret_alloc = _xzalloc_array(size, sizeof(void *), n); \
>>> +    else \
>>> +        __ret_alloc = _xmalloc_array(size, sizeof(void *), n); \
>>> +    __ret_alloc; \
>>> +})
>>> +
>>> +/* Alias to Xen time functions */
>>> +#define ktime_t s_time_t
>>> +#define ktime_get()             (NOW())
>>> +#define ktime_add_us(t,i)       (t + MICROSECS(i))
>>> +#define ktime_compare(t,i)      (t > (i))
>>> +
>>> +#endif /* __XEN_LINUX_COMPAT_H__ */
>>
>>
>> _______________________________________________
>> Xen-devel mailing list
>> Xen-devel@lists.xenproject.org
>> https://lists.xenproject.org/mailman/listinfo/xen-devel
>

On 09/05/2018 09:30, Manish Jaggi wrote:
> 
> 
> On 04/19/2018 04:24 PM, Manish Jaggi wrote:
>> Sorry for top posting,
>>
>> is someone working on the comments on this patch?
>>
>> -Manish
>>
> If no one is working this code anymore, I would like to pick it up and 
> continue maintaining it.
> Is it fine with all?

Last time I spoke with Sameer he was planning to resend a series. And I 
would prefer if he continue to lead the series unless stated otherwise.

Cheers,

> 
> -Regards
> Manish
>>
>> On 03/10/2018 11:23 PM, Manish Jaggi wrote:
>>> Hi Sameer,
>>>
>>>
>>> On 02/09/2018 08:40 AM, Sameer Goel wrote:
>>>> This driver follows an approach similar to smmu driver. The intent here
>>>> is to reuse as much Linux code as possible.
>>>> - Glue code has been introduced to bridge the API calls.
>>>> - Called Linux functions from the Xen IOMMU function calls.
>>>> - Xen modifications are preceded by /*Xen: comment */
>>>> - xen/linux_compat: Add a Linux compat header
>>>>    For porting files directly from Linux it is useful to have a 
>>>> function mapping
>>>>    definitions from Linux to Xen. This file adds common API 
>>>> functions and
>>>>    other defines that are needed for porting arm SMMU drivers.
>>>>
>>>> Signed-off-by: Sameer Goel <sameer.goel@linaro.org>
>>>> ---
>>>>   xen/arch/arm/p2m.c                    |   1 +
>>>>   xen/drivers/Kconfig                   |   2 +
>>>>   xen/drivers/passthrough/arm/Kconfig   |   8 +
>>>>   xen/drivers/passthrough/arm/Makefile  |   1 +
>>>>   xen/drivers/passthrough/arm/smmu-v3.c | 892 
>>>> ++++++++++++++++++++++++++++++++--
>>>>   xen/include/xen/linux_compat.h        |  84 ++++
>>>>   6 files changed, 959 insertions(+), 29 deletions(-)
>>>>   create mode 100644 xen/drivers/passthrough/arm/Kconfig
>>>>   create mode 100644 xen/include/xen/linux_compat.h
>>>>
>>>> diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
>>>> index 65e8b9c6ea..fef7605fd6 100644
>>>> --- a/xen/arch/arm/p2m.c
>>>> +++ b/xen/arch/arm/p2m.c
>>>> @@ -1460,6 +1460,7 @@ err:
>>>>   static void __init setup_virt_paging_one(void *data)
>>>>   {
>>>>       unsigned long val = (unsigned long)data;
>>>> +    /* SMMUv3 S2 cfg vtcr reuses the following value */
>>>>       WRITE_SYSREG32(val, VTCR_EL2);
>>>>       isb();
>>>>   }
>>>> diff --git a/xen/drivers/Kconfig b/xen/drivers/Kconfig
>>>> index bc3a54f0ea..612655386d 100644
>>>> --- a/xen/drivers/Kconfig
>>>> +++ b/xen/drivers/Kconfig
>>>> @@ -12,4 +12,6 @@ source "drivers/pci/Kconfig"
>>>>     source "drivers/video/Kconfig"
>>>>   +source "drivers/passthrough/arm/Kconfig"
>>>> +
>>>>   endmenu
>>>> diff --git a/xen/drivers/passthrough/arm/Kconfig 
>>>> b/xen/drivers/passthrough/arm/Kconfig
>>>> new file mode 100644
>>>> index 0000000000..cda899f608
>>>> --- /dev/null
>>>> +++ b/xen/drivers/passthrough/arm/Kconfig
>>>> @@ -0,0 +1,8 @@
>>>> +
>>>> +config ARM_SMMU_v3
>>>> +    bool "ARM SMMUv3 Support"
>>>> +    depends on ARM_64
>>>> +    help
>>>> +     Support for implementations of the ARM System MMU architecture
>>>> +     version 3.
>>>> +
>>>> diff --git a/xen/drivers/passthrough/arm/Makefile 
>>>> b/xen/drivers/passthrough/arm/Makefile
>>>> index f4cd26e15d..e14732b55c 100644
>>>> --- a/xen/drivers/passthrough/arm/Makefile
>>>> +++ b/xen/drivers/passthrough/arm/Makefile
>>>> @@ -1,2 +1,3 @@
>>>>   obj-y += iommu.o
>>>>   obj-y += smmu.o
>>>> +obj-$(CONFIG_ARM_SMMU_v3) += smmu-v3.o
>>>> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c 
>>>> b/xen/drivers/passthrough/arm/smmu-v3.c
>>>> index e67ba6c40f..f43485fe6e 100644
>>>> --- a/xen/drivers/passthrough/arm/smmu-v3.c
>>>> +++ b/xen/drivers/passthrough/arm/smmu-v3.c
>>>> @@ -18,28 +18,414 @@
>>>>    * Author: Will Deacon <will.deacon@arm.com>
>>>>    *
>>>>    * This driver is powered by bad coffee and bombay mix.
>>>> + *
>>>> + *
>>>> + * Based on Linux drivers/iommu/arm-smmu-v3.c
>>>> + * => commit 7aa8619a66aea52b145e04cbab4f8d6a4e5f3f3b
>>>> + *
>>>> + * Xen modifications:
>>>> + * Sameer Goel <sameer.goel@linaro.org>
>>>> + * Copyright (C) 2017, The Linux Foundation, All rights reserved.
>>>> + *
>>>> + */
>>>> +
>>>> +#include <xen/acpi.h>
>>>> +#include <xen/config.h>
>>>> +#include <xen/delay.h>
>>>> +#include <xen/errno.h>
>>>> +#include <xen/err.h>
>>>> +#include <xen/irq.h>
>>>> +#include <xen/lib.h>
>>>> +#include <xen/linux_compat.h>
>>>> +#include <xen/list.h>
>>>> +#include <xen/mm.h>
>>>> +#include <xen/rbtree.h>
>>>> +#include <xen/sched.h>
>>>> +#include <xen/sizes.h>
>>>> +#include <xen/vmap.h>
>>>> +#include <acpi/acpi_iort.h>
>>>> +#include <asm/atomic.h>
>>>> +#include <asm/device.h>
>>>> +#include <asm/io.h>
>>>> +#include <asm/platform.h>
>>>> +
>>>> +/* Alias to Xen device tree helpers */
>>>> +#define device_node dt_device_node
>>>> +#define of_phandle_args dt_phandle_args
>>>> +#define of_device_id dt_device_match
>>>> +#define of_match_node dt_match_node
>>>> +#define of_property_read_u32(np, pname, out) 
>>>> (!dt_property_read_u32(np, pname, out))
>>>> +#define of_property_read_bool dt_property_read_bool
>>>> +#define of_parse_phandle_with_args dt_parse_phandle_with_args
>>>> +
>>>> +/* Xen: Helpers to get device MMIO and IRQs */
>>>> +struct resource {
>>>> +    u64 addr;
>>>> +    u64 size;
>>>> +    unsigned int type;
>>>> +};
>>>> +
>>>> +#define resource_size(res) ((res)->size)
>>>> +
>>>> +#define platform_device device
>>>> +
>>>> +#define IORESOURCE_MEM 0
>>>> +#define IORESOURCE_IRQ 1
>>>> +
>>>> +static struct resource *platform_get_resource(struct 
>>>> platform_device *pdev,
>>>> +                          unsigned int type,
>>>> +                          unsigned int num)
>>>> +{
>>>> +    /*
>>>> +     * The resource is only used between 2 calls of 
>>>> platform_get_resource.
>>>> +     * It's quite ugly but it's avoid to add too much code in the part
>>>> +     * imported from Linux
>>>> +     */
>>>> +    static struct resource res;
>>>> +    struct acpi_iort_node *iort_node;
>>>> +    struct acpi_iort_smmu_v3 *node_smmu_data;
>>>> +    int ret = 0;
>>>> +
>>>> +    res.type = type;
>>>> +
>>>> +    switch (type) {
>>>> +    case IORESOURCE_MEM:
>>>> +        if (pdev->type == DEV_ACPI) {
>>>> +            ret = 1;
>>>> +            iort_node = pdev->acpi_node;
>>>> +            node_smmu_data =
>>>> +                (struct acpi_iort_smmu_v3 *)iort_node->node_data;
>>>> +
>>>> +            if (node_smmu_data != NULL) {
>>>> +                res.addr = node_smmu_data->base_address;
>>>> +                res.size = SZ_128K;
>>>> +                ret = 0;
>>>> +            }
>>>> +        } else {
>>>> +            ret = dt_device_get_address(dev_to_dt(pdev), num,
>>>> +                            &res.addr, &res.size);
>>>> +        }
>>>> +
>>>> +        return ((ret) ? NULL : &res);
>>>> +
>>>> +    case IORESOURCE_IRQ:
>>>> +        /* ACPI case not implemented as there is no use case for it */
>>>> +        ret = platform_get_irq(dev_to_dt(pdev), num);
>>>> +
>>>> +        if (ret < 0)
>>>> +            return NULL;
>>>> +
>>>> +        res.addr = ret;
>>>> +        res.size = 1;
>>>> +
>>>> +        return &res;
>>>> +
>>>> +    default:
>>>> +        return NULL;
>>>> +    }
>>>> +}
>>>> +
>>>> +static int platform_get_irq_byname(struct platform_device *pdev, 
>>>> const char *name)
>>>> +{
>>>> +    const struct dt_property *dtprop;
>>>> +    struct acpi_iort_node *iort_node;
>>>> +    struct acpi_iort_smmu_v3 *node_smmu_data;
>>>> +    int ret = 0;
>>>> +
>>>> +    if (pdev->type == DEV_ACPI) {
>>>> +        iort_node = pdev->acpi_node;
>>>> +        node_smmu_data = (struct acpi_iort_smmu_v3 
>>>> *)iort_node->node_data;
>>>> +
>>>> +        if (node_smmu_data != NULL) {
>>>> +            if (!strcmp(name, "eventq"))
>>>> +                ret = node_smmu_data->event_gsiv;
>>>> +            else if (!strcmp(name, "priq"))
>>>> +                ret = node_smmu_data->pri_gsiv;
>>>> +            else if (!strcmp(name, "cmdq-sync"))
>>>> +                ret = node_smmu_data->sync_gsiv;
>>>> +            else if (!strcmp(name, "gerror"))
>>>> +                ret = node_smmu_data->gerr_gsiv;
>>>> +            else
>>>> +                ret = -EINVAL;
>>>> +        }
>>>> +    } else {
>>>> +        dtprop = dt_find_property(dev_to_dt(pdev), 
>>>> "interrupt-names", NULL);
>>>> +        if (!dtprop)
>>>> +            return -EINVAL;
>>>> +
>>>> +        if (!dtprop->value)
>>>> +            return -ENODATA;
>>>> +    }
>>>> +
>>>> +    return ret;
>>>> +}
>>>> +
>>>> +/*
>>>> + * Xen: Helpers for DMA allocation. Just the function name is 
>>>> reused for
>>>> + * porting code these allocation are not managed allocations
>>>>    */
>>>>   -#include <linux/acpi.h>
>>>> -#include <linux/acpi_iort.h>
>>>> -#include <linux/delay.h>
>>>> -#include <linux/dma-iommu.h>
>>>> -#include <linux/err.h>
>>>> -#include <linux/interrupt.h>
>>>> -#include <linux/iommu.h>
>>>> -#include <linux/iopoll.h>
>>>> -#include <linux/module.h>
>>>> -#include <linux/msi.h>
>>>> -#include <linux/of.h>
>>>> -#include <linux/of_address.h>
>>>> -#include <linux/of_iommu.h>
>>>> -#include <linux/of_platform.h>
>>>> -#include <linux/pci.h>
>>>> -#include <linux/platform_device.h>
>>>> -
>>>> -#include <linux/amba/bus.h>
>>>> -
>>>> -#include "io-pgtable.h"
>>>> +static void *dmam_alloc_coherent(struct device *dev, size_t size,
>>>> +               dma_addr_t *dma_handle, gfp_t gfp)
>>>> +{
>>>> +    void *vaddr;
>>>> +    unsigned long alignment = size;
>>>> +
>>>> +    /*
>>>> +     * _xzalloc requires that the (align & (align -1)) = 0. Most of 
>>>> the
>>>> +     * allocations in SMMU code should send the right value for 
>>>> size. In
>>>> +     * case this is not true print a warning and align to the size 
>>>> of a
>>>> +     * (void *)
>>>> +     */
>>>> +    if (size & (size - 1)) {
>>>> +        dev_warn(dev, "Fixing alignment for the DMA buffer\n");
>>>> +        alignment = sizeof(void *);
>>>> +    }
>>>> +
>>>> +    vaddr = _xzalloc(size, alignment);
>>>> +    if (!vaddr) {
>>>> +        dev_err(dev, "DMA allocation failed\n");
>>>> +        return NULL;
>>>> +    }
>>>> +
>>>> +    *dma_handle = virt_to_maddr(vaddr);
>>>> +
>>>> +    return vaddr;
>>>> +}
>>>> +
>>>> +
>>>> +static void dmam_free_coherent(struct device *dev, size_t size, 
>>>> void *vaddr,
>>>> +            dma_addr_t dma_handle)
>>>> +{
>>>> +    xfree(vaddr);
>>>> +}
>>>> +
>>>> +/* Xen: Stub out DMA domain related functions */
>>>> +#define iommu_get_dma_cookie(dom) 0
>>>> +#define iommu_put_dma_cookie(dom)
>>>> +
>>>> +/* Xen: Stub out module param related function */
>>>> +#define module_param_named(a, b, c, d)
>>>> +#define MODULE_PARM_DESC(a, b)
>>>> +
>>>> +#define dma_set_mask_and_coherent(d, b) 0
>>>> +
>>>> +#define of_dma_is_coherent(n) 0
>>>> +
>>>> +#define MODULE_DEVICE_TABLE(type, name)
>>>> +
>>>> +static void __iomem *devm_ioremap_resource(struct device *dev,
>>>> +                       struct resource *res)
>>>> +{
>>>> +    void __iomem *ptr;
>>>> +
>>>> +    if (!res || res->type != IORESOURCE_MEM) {
>>>> +        dev_err(dev, "Invalid resource\n");
>>>> +        return ERR_PTR(-EINVAL);
>>>> +    }
>>>> +
>>>> +    ptr = ioremap_nocache(res->addr, res->size);
>>>> +    if (!ptr) {
>>>> +        dev_err(dev,
>>>> +            "ioremap failed (addr 0x%"PRIx64" size 0x%"PRIx64")\n",
>>>> +            res->addr, res->size);
>>>> +        return ERR_PTR(-ENOMEM);
>>>> +    }
>>>> +
>>>> +    return ptr;
>>>> +}
>>>> +
>>>> +/* Xen: Compatibility define for iommu_domain_geometry.*/
>>>> +struct iommu_domain_geometry {
>>>> +    dma_addr_t aperture_start; /* First address that can be 
>>>> mapped    */
>>>> +    dma_addr_t aperture_end;   /* Last address that can be 
>>>> mapped     */
>>>> +    bool force_aperture;       /* DMA only allowed in mappable 
>>>> range? */
>>>> +};
>>>> +
>>>> +
>>>> +/* Xen: Type definitions for iommu_domain */
>>>> +#define IOMMU_DOMAIN_UNMANAGED 0
>>>> +#define IOMMU_DOMAIN_DMA 1
>>>> +#define IOMMU_DOMAIN_IDENTITY 2
>>>> +
>>>> +/* Xen: Dummy iommu_domain */
>>>> +struct iommu_domain {
>>>> +    /* Runtime SMMU configuration for this iommu_domain */
>>>> +    struct arm_smmu_domain        *priv;
>>>> +    unsigned int type;
>>>> +
>>>> +    /* Dummy compatibility defines */
>>>> +    unsigned long pgsize_bitmap;
>>>> +    struct iommu_domain_geometry geometry;
>>>> +
>>>> +    atomic_t ref;
>>>> +    /*
>>>> +     * Used to link iommu_domain contexts for a same domain.
>>>> +     * There is at least one per-SMMU to used by the domain.
>>>> +     */
>>>> +    struct list_head        list;
>>>> +};
>>>> +
>>>> +/* Xen: Describes information required for a Xen domain */
>>>> +struct arm_smmu_xen_domain {
>>>> +    spinlock_t            lock;
>>>> +    /* List of iommu domains associated to this domain */
>>>> +    struct list_head        contexts;
>>>> +};
>>>> +
>>>> +/*
>>>> + * Xen: Information about each device stored in dev->archdata.iommu
>>>> + *
>>>> + * The dev->archdata.iommu stores the iommu_domain (runtime 
>>>> configuration of
>>>> + * the SMMU).
>>>> + */
>>>> +struct arm_smmu_xen_device {
>>>> +    struct iommu_domain *domain;
>>>> +};
>>>> +
>>>> +/*
>>>> + * Xen: io_pgtable compatibility defines.
>>>> + * Most of these are to port in the S1 translation code as is.
>>>> + */
>>>> +struct io_pgtable_ops {
>>>> +};
>>>> +
>>>> +struct iommu_gather_ops {
>>>> +    void (*tlb_flush_all)(void *cookie);
>>>> +    void (*tlb_add_flush)(unsigned long iova, size_t size, size_t 
>>>> granule,
>>>> +                  bool leaf, void *cookie);
>>>> +    void (*tlb_sync)(void *cookie);
>>>> +};
>>>> +
>>>> +struct io_pgtable_cfg {
>>>> +    /*
>>>> +     * IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE 
>>>> bits in
>>>> +     *    stage 1 PTEs, for hardware which insists on validating them
>>>> +     *    even in    non-secure state where they should normally be 
>>>> ignored.
>>>> +     *
>>>> +     * IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, 
>>>> IOMMU_WRITE and
>>>> +     *    IOMMU_NOEXEC flags and map everything with full access, for
>>>> +     *    hardware which does not implement the permissions of a given
>>>> +     *    format, and/or requires some format-specific default value.
>>>> +     *
>>>> +     * IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching 
>>>> invalid
>>>> +     *    (unmapped) entries but the hardware might do so anyway, 
>>>> perform
>>>> +     *    TLB maintenance when mapping as well as when unmapping.
>>>> +     *
>>>> +     * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
>>>> +     *    PTEs, for Mediatek IOMMUs which treat it as a 33rd 
>>>> address bit
>>>> +     *    when the SoC is in "4GB mode" and they can only access 
>>>> the high
>>>> +     *    remap of DRAM (0x1_00000000 to 0x1_ffffffff).
>>>> +     *
>>>> +     * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will 
>>>> only ever
>>>> +     *    be accessed by a fully cache-coherent IOMMU or CPU (e.g. 
>>>> for a
>>>> +     *    software-emulated IOMMU), such that pagetable updates 
>>>> need not
>>>> +     *    be treated as explicit DMA data.
>>>> +     */
>>>> +    #define IO_PGTABLE_QUIRK_ARM_NS        BIT(0)
>>>> +    #define IO_PGTABLE_QUIRK_NO_PERMS    BIT(1)
>>>> +    #define IO_PGTABLE_QUIRK_TLBI_ON_MAP    BIT(2)
>>>> +    #define IO_PGTABLE_QUIRK_ARM_MTK_4GB    BIT(3)
>>>> +    #define IO_PGTABLE_QUIRK_NO_DMA        BIT(4)
>>>> +    unsigned long            quirks;
>>>> +    unsigned long            pgsize_bitmap;
>>>> +    unsigned int            ias;
>>>> +    unsigned int            oas;
>>>> +    const struct iommu_gather_ops    *tlb;
>>>> +    struct device            *iommu_dev;
>>>> +
>>>> +    /* Low-level data specific to the table format */
>>>> +    union {
>>>> +        struct {
>>>> +            u64    ttbr[2];
>>>> +            u64    tcr;
>>>> +            u64    mair[2];
>>>> +        } arm_lpae_s1_cfg;
>>>> +
>>>> +        struct {
>>>> +            u64    vttbr;
>>>> +            u64    vtcr;
>>>> +        } arm_lpae_s2_cfg;
>>>> +
>>>> +        struct {
>>>> +            u32    ttbr[2];
>>>> +            u32    tcr;
>>>> +            u32    nmrr;
>>>> +            u32    prrr;
>>>> +        } arm_v7s_cfg;
>>>> +    };
>>>> +};
>>>> +
>>>> +enum io_pgtable_fmt {
>>>> +    ARM_32_LPAE_S1,
>>>> +    ARM_32_LPAE_S2,
>>>> +    ARM_64_LPAE_S1,
>>>> +    ARM_64_LPAE_S2,
>>>> +    ARM_V7S,
>>>> +    IO_PGTABLE_NUM_FMTS,
>>>> +};
>>>> +
>>>> +/*
>>>> + * Xen: The pgtable_ops are used by the S1 translations, so return 
>>>> the dummy
>>>> + * address.
>>>> + */
>>>> +#define alloc_io_pgtable_ops(f, c, o) ((struct io_pgtable_ops *)0x0)
>>> Is this correct? it will make the caller null check fail
>>>> +#define free_io_pgtable_ops(o)
>>>> +
>>>> +/* Xen: Define wrapper for requesting IRQs */
>>>> +#define IRQF_ONESHOT 0
>>>> +
>>>> +typedef void (*irq_handler_t)(int, void *, struct cpu_user_regs *);
>>>> +
>>>> +static inline int devm_request_irq(struct device *dev, unsigned int 
>>>> irq,
>>>> +                   irq_handler_t handler, unsigned long irqflags,
>>>> +                   const char *devname, void *dev_id)
>>>> +{
>>>> +    /*
>>>> +     * SMMUv3 implementation can support wired interrupt outputs 
>>>> that are
>>>> +     * edge-triggered. Set the irq type as per the spec.
>>>> +     */
>>>> +    irq_set_type(irq, IRQ_TYPE_EDGE_BOTH);
>>>> +    return request_irq(irq, irqflags, handler, devname, dev_id);
>>>> +}
>>>> +
>>>> +/*
>>>> + * Xen does not have a concept of threaded irq, but eventually we 
>>>> can use
>>>> + * tasklets to optimize the following function.
>>>> + */
>>>> +int devm_request_threaded_irq(struct device *dev, unsigned int irq, 
>>>> irq_handler_t handler,
>>>> +                  irq_handler_t thread_fn, unsigned long irqflags,
>>>> +                  const char *devname, void *dev_id)
>>>> +{
>>>> +    return devm_request_irq(dev, irq, thread_fn, irqflags, devname, 
>>>> dev_id);
>>>> +}
>>>> +
>>>> +/* Xen: The mutex is used only during initialization so the 
>>>> typecast is safe */
>>>> +#define mutex spinlock
>>>> +#define mutex_init spin_lock_init
>>>> +#define mutex_lock spin_lock
>>>> +#define mutex_unlock spin_unlock
>>>> +
>>>> +#define readx_poll_timeout(op, addr, val, cond, sleep_us, 
>>>> timeout_us) \
>>>> +({ \
>>>> +    s_time_t deadline = NOW() + MICROSECS(timeout_us); \
>>>> +    for (;;) { \
>>>> +        (val) = op(addr); \
>>>> +        if (cond) \
>>>> +            break; \
>>>> +        if (NOW() > deadline) { \
>>>> +            (val) = op(addr); \
>>>> +            break; \
>>>> +        } \
>>>> +    udelay(sleep_us); \
>>>> +    } \
>>>> +    (cond) ? 0 : -ETIMEDOUT; \
>>>> +})
>>>> +
>>>> +#define readl_relaxed_poll_timeout(addr, val, cond, delay_us, 
>>>> timeout_us) \
>>>> +    readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, 
>>>> timeout_us)
>>>> +
>>>> +#define VA_BITS 0 /* Only needed for S1 translations */
>>>>     /* MMIO registers */
>>>>   #define ARM_SMMU_IDR0            0x0
>>>> @@ -433,6 +819,7 @@ enum pri_resp {
>>>>       PRI_RESP_SUCC,
>>>>   };
>>>>   +#if 0 /* Xen: No MSI support in this iteration */
>>>>   enum arm_smmu_msi_index {
>>>>       EVTQ_MSI_INDEX,
>>>>       GERROR_MSI_INDEX,
>>>> @@ -457,6 +844,7 @@ static phys_addr_t 
>>>> arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
>>>>           ARM_SMMU_PRIQ_IRQ_CFG2,
>>>>       },
>>>>   };
>>>> +#endif
>>>>     struct arm_smmu_cmdq_ent {
>>>>       /* Common fields */
>>>> @@ -561,6 +949,8 @@ struct arm_smmu_s2_cfg {
>>>>       u16                vmid;
>>>>       u64                vttbr;
>>>>       u64                vtcr;
>>>> +    /* Xen: Domain associated to this configuration */
>>>> +    struct domain            *domain;
>>>>   };
>>>>     struct arm_smmu_strtab_ent {
>>>> @@ -635,9 +1025,21 @@ struct arm_smmu_device {
>>>>       struct arm_smmu_strtab_cfg    strtab_cfg;
>>>>         /* IOMMU core code handle */
>>>> +#if 0 /*Xen: Generic iommu_device ref not needed here */
>>>>       struct iommu_device        iommu;
>>>> +#endif
>>>> +    /* Xen: Need to keep a list of SMMU devices */
>>>> +    struct list_head                devices;
>>>>   };
>>>>   +/* Xen: Keep a list of devices associated with this driver */
>>>> +static DEFINE_SPINLOCK(arm_smmu_devices_lock);
>>>> +static LIST_HEAD(arm_smmu_devices);
>>>> +/* Xen: Helper for finding a device using fwnode */
>>>> +static
>>>> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle 
>>>> *fwnode);
>>>> +
>>>> +
>>>>   /* SMMU private data for each master */
>>>>   struct arm_smmu_master_data {
>>>>       struct arm_smmu_device        *smmu;
>>>> @@ -1232,7 +1634,7 @@ static void arm_smmu_handle_ppr(struct 
>>>> arm_smmu_device *smmu, u64 *evt)
>>>>         dev_info(smmu->dev, "unexpected PRI request received:\n");
>>>>       dev_info(smmu->dev,
>>>> -         "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at 
>>>> iova 0x%016llx\n",
>>>> +         "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at 
>>>> iova %#" PRIx64 "\n",
>>>>            sid, ssid, grpid, last ? "L" : "",
>>>>            evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",
>>>>            evt[0] & PRIQ_0_PERM_READ ? "R" : "",
>>>> @@ -1346,6 +1748,8 @@ static irqreturn_t 
>>>> arm_smmu_combined_irq_handler(int irq, void *dev)
>>>>   {
>>>>       arm_smmu_gerror_handler(irq, dev);
>>>>       arm_smmu_cmdq_sync_handler(irq, dev);
>>>> +    /*Xen: No threaded irq. So call the required function from here */
>>>> +    arm_smmu_combined_irq_thread(irq, dev);
>>>>       return IRQ_WAKE_THREAD;
>>>>   }
>>>>   @@ -1358,6 +1762,46 @@ static void __arm_smmu_tlb_sync(struct 
>>>> arm_smmu_device *smmu)
>>>>       arm_smmu_cmdq_issue_cmd(smmu, &cmd);
>>>>   }
>>>>   +/*
>>>> + * Xen: Define the IRQ handlers for xen. The linux functions would be
>>>> + * modified to use the functions defined in the following code.
>>>> + */
>>>> +static void arm_smmu_evtq_thread_xen(int irq, void *dev,
>>>> +                       struct cpu_user_regs *regs)
>>>> +{
>>>> +    arm_smmu_evtq_thread(irq, dev);
>>>> +}
>>>> +
>>>> +static void arm_smmu_priq_thread_xen(int irq, void *dev,
>>>> +                       struct cpu_user_regs *regs)
>>>> +{
>>>> +    arm_smmu_priq_thread(irq, dev);
>>>> +}
>>>> +
>>>> +static void arm_smmu_cmdq_sync_handler_xen(int irq, void *dev,
>>>> +                       struct cpu_user_regs *regs)
>>>> +{
>>>> +    arm_smmu_cmdq_sync_handler(irq, dev);
>>>> +}
>>>> +
>>>> +static void arm_smmu_gerror_handler_xen(int irq, void *dev,
>>>> +                       struct cpu_user_regs *regs)
>>>> +{
>>>> +    arm_smmu_gerror_handler(irq, dev);
>>>> +}
>>>> +
>>>> +static void arm_smmu_combined_irq_handler_xen(int irq, void *dev,
>>>> +                       struct cpu_user_regs *regs)
>>>> +{
>>>> +    arm_smmu_combined_irq_handler(irq, dev);
>>>> +}
>>>> +
>>>> +#define arm_smmu_evtq_thread arm_smmu_evtq_thread_xen
>>>> +#define arm_smmu_priq_thread arm_smmu_priq_thread_xen
>>>> +#define arm_smmu_cmdq_sync_handler arm_smmu_cmdq_sync_handler_xen
>>>> +#define arm_smmu_gerror_handler arm_smmu_gerror_handler_xen
>>>> +#define arm_smmu_combined_irq_handler 
>>>> arm_smmu_combined_irq_handler_xen
>>>> +
>>>>   static void arm_smmu_tlb_sync(void *cookie)
>>>>   {
>>>>       struct arm_smmu_domain *smmu_domain = cookie;
>>>> @@ -1415,6 +1859,7 @@ static const struct iommu_gather_ops 
>>>> arm_smmu_gather_ops = {
>>>>       .tlb_sync    = arm_smmu_tlb_sync,
>>>>   };
>>>>   +#if 0 /*Xen: Unused functionality */
>>>>   /* IOMMU API */
>>>>   static bool arm_smmu_capable(enum iommu_cap cap)
>>>>   {
>>>> @@ -1427,6 +1872,7 @@ static bool arm_smmu_capable(enum iommu_cap cap)
>>>>           return false;
>>>>       }
>>>>   }
>>>> +#endif
>>>>     static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
>>>>   {
>>>> @@ -1546,9 +1992,16 @@ static int arm_smmu_domain_finalise_s2(struct 
>>>> arm_smmu_domain *smmu_domain,
>>>>       if (vmid < 0)
>>>>           return vmid;
>>>>   -    cfg->vmid    = (u16)vmid;
>>>> -    cfg->vttbr    = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
>>>> -    cfg->vtcr    = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
>>>> +    /*
>>>> +     * Xen: Get the ttbr and vtcr values
>>>> +     * vttbr: This is a shared value with the domain page table
>>>> +     * vtcr: The TCR settings are the same as CPU since the page
>>>> +     * tables are shared
>>>> +     */
>>>> +
>>>> +    cfg->vmid    = vmid;
>>>> +    cfg->vttbr    = page_to_maddr(cfg->domain->arch.p2m.root);
>>>> +    cfg->vtcr    = READ_SYSREG32(VTCR_EL2) & STRTAB_STE_2_VTCR_MASK;
>>>>       return 0;
>>>>   }
>>>>   @@ -1604,6 +2057,7 @@ static int arm_smmu_domain_finalise(struct 
>>>> iommu_domain *domain)
>>>>       if (smmu->features & ARM_SMMU_FEAT_COHERENCY)
>>>>           pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_NO_DMA;
>>>>   +    /* Xen: pgtbl_ops gets an invalid address */
>>>>       pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
>>>>       if (!pgtbl_ops)
>>>>           return -ENOMEM;
>>> Will this not fail ?
>>>> @@ -1721,6 +2175,7 @@ out_unlock:
>>>>       return ret;
>>>>   }
>>>>   +#if 0 /* Xen: Unused functionality */
>>>>   static int arm_smmu_map(struct iommu_domain *domain, unsigned long 
>>>> iova,
>>>>               phys_addr_t paddr, size_t size, int prot)
>>>>   {
>>>> @@ -1772,6 +2227,7 @@ struct arm_smmu_device 
>>>> *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
>>>>       put_device(dev);
>>>>       return dev ? dev_get_drvdata(dev) : NULL;
>>>>   }
>>>> +#endif
>>>>     static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, 
>>>> u32 sid)
>>>>   {
>>>> @@ -1783,7 +2239,14 @@ static bool arm_smmu_sid_in_range(struct 
>>>> arm_smmu_device *smmu, u32 sid)
>>>>       return sid < limit;
>>>>   }
>>>>   +/* Xen: Unused */
>>>> +#if 0
>>>>   static struct iommu_ops arm_smmu_ops;
>>>> +#endif
>>>> +
>>>> +/* Xen: Redefine arm_smmu_ops to what fwspec should evaluate */
>>>> +static const struct iommu_ops arm_smmu_iommu_ops;
>>>> +#define arm_smmu_ops arm_smmu_iommu_ops
>>>>     static int arm_smmu_add_device(struct device *dev)
>>>>   {
>>>> @@ -1791,8 +2254,11 @@ static int arm_smmu_add_device(struct device 
>>>> *dev)
>>>>       struct arm_smmu_device *smmu;
>>>>       struct arm_smmu_master_data *master;
>>>>       struct iommu_fwspec *fwspec = dev->iommu_fwspec;
>>>> +#if 0 /*Xen: iommu_group is not needed */
>>>>       struct iommu_group *group;
>>>> +#endif
>>>>   +    /* Xen: fwspec->ops are not needed */
>>>>       if (!fwspec || fwspec->ops != &arm_smmu_ops)
>>>>           return -ENODEV;
>>>>       /*
>>>> @@ -1830,6 +2296,11 @@ static int arm_smmu_add_device(struct device 
>>>> *dev)
>>>>           }
>>>>       }
>>>>   +/*
>>>> + * Xen: Do not need an iommu group as the stream data is carried by 
>>>> the SMMU
>>>> + * master device object
>>>> + */
>>>> +#if 0
>>>>       group = iommu_group_get_for_dev(dev);
>>>>       if (!IS_ERR(group)) {
>>>>           iommu_group_put(group);
>>>> @@ -1837,8 +2308,16 @@ static int arm_smmu_add_device(struct device 
>>>> *dev)
>>>>       }
>>>>         return PTR_ERR_OR_ZERO(group);
>>>> +#endif
>>>> +    return 0;
>>>>   }
>>>>   +/*
>>>> + * Xen: We can potentially support this function and destroy a 
>>>> device. This
>>>> + * will be relevant for PCI hotplug. So, will be implemented as 
>>>> needed after
>>>> + * passthrough support is available.
>>>> + */
>>>> +#if 0
>>>>   static void arm_smmu_remove_device(struct device *dev)
>>>>   {
>>>>       struct iommu_fwspec *fwspec = dev->iommu_fwspec;
>>>> @@ -1974,6 +2453,7 @@ static struct iommu_ops arm_smmu_ops = {
>>>>       .put_resv_regions    = arm_smmu_put_resv_regions,
>>>>       .pgsize_bitmap        = -1UL, /* Restricted during device 
>>>> attach */
>>>>   };
>>>> +#endif
>>>>     /* Probing and initialisation functions */
>>>>   static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
>>>> @@ -2182,6 +2662,7 @@ static int arm_smmu_update_gbpa(struct 
>>>> arm_smmu_device *smmu, u32 set, u32 clr)
>>>>                         1, ARM_SMMU_POLL_TIMEOUT_US);
>>>>   }
>>>>   +#if 0 /* Xen: There is no MSI support as yet */
>>>>   static void arm_smmu_free_msis(void *data)
>>>>   {
>>>>       struct device *dev = data;
>>>> @@ -2247,12 +2728,15 @@ static void arm_smmu_setup_msis(struct 
>>>> arm_smmu_device *smmu)
>>>>       /* Add callback to free MSIs on teardown */
>>>>       devm_add_action(dev, arm_smmu_free_msis, dev);
>>>>   }
>>>> +#endif
>>>>     static void arm_smmu_setup_unique_irqs(struct arm_smmu_device 
>>>> *smmu)
>>>>   {
>>>>       int irq, ret;
>>>>   +#if 0 /*Xen: Cannot setup msis for now */
>>>>       arm_smmu_setup_msis(smmu);
>>>> +#endif
>>>>         /* Request interrupt lines */
>>>>       irq = smmu->evtq.q.irq;
>>>> @@ -2316,9 +2800,13 @@ static int arm_smmu_setup_irqs(struct 
>>>> arm_smmu_device *smmu)
>>>>            * Cavium ThunderX2 implementation doesn't not support unique
>>>>            * irq lines. Use single irq line for all the SMMUv3 
>>>> interrupts.
>>>>            */
>>>> -        ret = devm_request_threaded_irq(smmu->dev, irq,
>>>> +        /*
>>>> +         * Xen: Does not support threaded irqs, so serialise the 
>>>> setup.
>>>> +         * This is the same for pris and event interrupt lines on 
>>>> other
>>>> +         * systems
>>>> +         */
>>>> +        ret = devm_request_irq(smmu->dev, irq,
>>>>                       arm_smmu_combined_irq_handler,
>>>> -                    arm_smmu_combined_irq_thread,
>>>>                       IRQF_ONESHOT,
>>>>                       "arm-smmu-v3-combined-irq", smmu);
>>>>           if (ret < 0)
>>>> @@ -2542,8 +3030,14 @@ static int arm_smmu_device_hw_probe(struct 
>>>> arm_smmu_device *smmu)
>>>>           smmu->features |= ARM_SMMU_FEAT_STALLS;
>>>>       }
>>>>   +/*
>>>> + * Xen: Block stage 1 translations. By doing this here we do not 
>>>> need to set the
>>>> + * domain->stage explicitly.
>>>> + */
>>>> +#if 0
>>>>       if (reg & IDR0_S1P)
>>>>           smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
>>>> +#endif
>>>>         if (reg & IDR0_S2P)
>>>>           smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
>>>> @@ -2616,10 +3110,12 @@ static int arm_smmu_device_hw_probe(struct 
>>>> arm_smmu_device *smmu)
>>>>       if (reg & IDR5_GRAN4K)
>>>>           smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
>>>>   +#if 0 /* Xen: SMMU ops do not have a pgsize_bitmap member for Xen */
>>>>       if (arm_smmu_ops.pgsize_bitmap == -1UL)
>>>>           arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
>>>>       else
>>>>           arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
>>>> +#endif
>>>>         /* Output address size */
>>>>       switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) {
>>>> @@ -2680,7 +3176,8 @@ static int arm_smmu_device_acpi_probe(struct 
>>>> platform_device *pdev,
>>>>       struct device *dev = smmu->dev;
>>>>       struct acpi_iort_node *node;
>>>>   -    node = *(struct acpi_iort_node **)dev_get_platdata(dev);
>>>> +    /* Xen: Modification to get iort_node */
>>>> +    node = (struct acpi_iort_node *)dev->acpi_node;
>>>>         /* Retrieve SMMUv3 specific data */
>>>>       iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>>>> @@ -2703,7 +3200,7 @@ static inline int 
>>>> arm_smmu_device_acpi_probe(struct platform_device *pdev,
>>>>   static int arm_smmu_device_dt_probe(struct platform_device *pdev,
>>>>                       struct arm_smmu_device *smmu)
>>>>   {
>>>> -    struct device *dev = &pdev->dev;
>>>> +    struct device *dev = pdev;
>>>>       u32 cells;
>>>>       int ret = -EINVAL;
>>>>   @@ -2716,6 +3213,7 @@ static int arm_smmu_device_dt_probe(struct 
>>>> platform_device *pdev,
>>>>         parse_driver_options(smmu);
>>>>   +    /* Xen: of_dma_is_coherent is a stub till dt support is 
>>>> introduced */
>>>>       if (of_dma_is_coherent(dev->of_node))
>>>>           smmu->features |= ARM_SMMU_FEAT_COHERENCY;
>>>>   @@ -2734,9 +3232,11 @@ static int arm_smmu_device_probe(struct 
>>>> platform_device *pdev)
>>>>   {
>>>>       int irq, ret;
>>>>       struct resource *res;
>>>> +#if 0 /*Xen: Do not need to setup sysfs */
>>>>       resource_size_t ioaddr;
>>>> +#endif
>>>>       struct arm_smmu_device *smmu;
>>>> -    struct device *dev = &pdev->dev;
>>>> +    struct device *dev = pdev;/* Xen: dev is ignored */
>>>>       bool bypass;
>>>>         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
>>>> @@ -2763,7 +3263,9 @@ static int arm_smmu_device_probe(struct 
>>>> platform_device *pdev)
>>>>           dev_err(dev, "MMIO region too small (%pr)\n", res);
>>>>           return -EINVAL;
>>>>       }
>>>> +#if 0 /*Xen: Do not need to setup sysfs */
>>>>       ioaddr = res->start;
>>>> +#endif
>>>>         smmu->base = devm_ioremap_resource(dev, res);
>>>>       if (IS_ERR(smmu->base))
>>>> @@ -2802,13 +3304,18 @@ static int arm_smmu_device_probe(struct 
>>>> platform_device *pdev)
>>>>           return ret;
>>>>         /* Record our private device structure */
>>>> +    /* Xen: SMMU is not treated a a platform device*/
>>>> +#if 0
>>>>       platform_set_drvdata(pdev, smmu);
>>>> +#endif
>>>>         /* Reset the device */
>>>>       ret = arm_smmu_device_reset(smmu, bypass);
>>>>       if (ret)
>>>>           return ret;
>>>>   +/* Xen: Not creating an IOMMU device list for Xen */
>>>> +#if 0
>>>>       /* And we're up. Go go go! */
>>>>       ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL,
>>>>                        "smmu3.%pa", &ioaddr);
>>>> @@ -2844,9 +3351,20 @@ static int arm_smmu_device_probe(struct 
>>>> platform_device *pdev)
>>>>           if (ret)
>>>>               return ret;
>>>>       }
>>>> +#endif
>>>> +    /*
>>>> +     * Xen: Keep a list of all probed devices. This will be used to 
>>>> query
>>>> +     * the smmu devices based on the fwnode.
>>>> +     */
>>>> +    INIT_LIST_HEAD(&smmu->devices);
>>>> +    spin_lock(&arm_smmu_devices_lock);
>>>> +    list_add(&smmu->devices, &arm_smmu_devices);
>>>> +    spin_unlock(&arm_smmu_devices_lock);
>>>>       return 0;
>>>>   }
>>>>   +/* Xen: Unused function */
>>>> +#if 0
>>>>   static int arm_smmu_device_remove(struct platform_device *pdev)
>>>>   {
>>>>       struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
>>>> @@ -2860,6 +3378,8 @@ static void arm_smmu_device_shutdown(struct 
>>>> platform_device *pdev)
>>>>   {
>>>>       arm_smmu_device_remove(pdev);
>>>>   }
>>>> +#endif
>>>> +
>>>>     static const struct of_device_id arm_smmu_of_match[] = {
>>>>       { .compatible = "arm,smmu-v3", },
>>>> @@ -2867,6 +3387,7 @@ static const struct of_device_id 
>>>> arm_smmu_of_match[] = {
>>>>   };
>>>>   MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
>>>>   +#if 0
>>>>   static struct platform_driver arm_smmu_driver = {
>>>>       .driver    = {
>>>>           .name        = "arm-smmu-v3",
>>>> @@ -2883,3 +3404,316 @@ IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3", 
>>>> NULL);
>>>>   MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 
>>>> implementations");
>>>>   MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
>>>>   MODULE_LICENSE("GPL v2");
>>>> +#endif
>>>> +
>>>> +/***** Start of Xen specific code *****/
>>>> +
>>>> +static int __must_check arm_smmu_iotlb_flush_all(struct domain *d)
>>>> +{
>>>> +    struct arm_smmu_xen_domain *smmu_domain = dom_iommu(d)->arch.priv;
>>>> +    struct iommu_domain *cfg;
>>>> +
>>>> +    spin_lock(&smmu_domain->lock);
>>>> +    list_for_each_entry(cfg, &smmu_domain->contexts, list) {
>>>> +        /*
>>>> +         * Only invalidate the context when SMMU is present.
>>>> +         * This is because the context initialization is delayed
>>>> +         * until a master has been added.
>>>> +         */
>>>> +        if (unlikely(!ACCESS_ONCE(cfg->priv->smmu)))
>>>> +            continue;
>>>> +        arm_smmu_tlb_inv_context(cfg->priv);
>>>> +    }
>>>> +    spin_unlock(&smmu_domain->lock);
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static int __must_check arm_smmu_iotlb_flush(struct domain *d,
>>>> +                         unsigned long gfn,
>>>> +                         unsigned int page_count)
>>>> +{
>>>> +    return arm_smmu_iotlb_flush_all(d);
>>>> +}
>>>> +
>>>> +static struct iommu_domain *arm_smmu_get_domain(struct domain *d,
>>>> +                        struct device *dev)
>>>> +{
>>>> +    struct iommu_domain *domain;
>>>> +    struct arm_smmu_xen_domain *xen_domain;
>>>> +    struct arm_smmu_device *smmu;
>>>> +    struct arm_smmu_domain *smmu_domain;
>>>> +
>>>> +    xen_domain = dom_iommu(d)->arch.priv;
>>>> +
>>>> +    smmu = arm_smmu_get_by_fwnode(dev->iommu_fwspec->iommu_fwnode);
>>>> +    if (!smmu)
>>>> +        return NULL;
>>>> +
>>>> +    /*
>>>> +     * Loop through the &xen_domain->contexts to locate a context
>>>> +     * assigned to this SMMU
>>>> +     */
>>>> +    list_for_each_entry(domain, &xen_domain->contexts, list) {
>>>> +        smmu_domain = to_smmu_domain(domain);
>>>> +        if (smmu_domain->smmu == smmu)
>>>> +            return domain;
>>>> +    }
>>>> +
>>>> +    return NULL;
>>>> +}
>>>> +
>>>> +static void arm_smmu_destroy_iommu_domain(struct iommu_domain *domain)
>>>> +{
>>>> +    list_del(&domain->list);
>>>> +    arm_smmu_domain_free(domain);
>>>> +}
>>>> +
>>>> +static int arm_smmu_assign_dev(struct domain *d, u8 devfn,
>>>> +                   struct device *dev, u32 flag)
>>>> +{
>>>> +    int ret = 0;
>>>> +    struct iommu_domain *domain;
>>>> +    struct arm_smmu_xen_domain *xen_domain;
>>>> +    struct arm_smmu_domain *arm_smmu;
>>>> +
>>>> +    xen_domain = dom_iommu(d)->arch.priv;
>>>> +
>>>> +    if (!dev->archdata.iommu) {
>>>> +        dev->archdata.iommu = xzalloc(struct arm_smmu_xen_device);
>>>> +        if (!dev->archdata.iommu)
>>>> +            return -ENOMEM;
>>>> +    }
>>>> +
>>>> +    ret = arm_smmu_add_device(dev);
>>>> +    if (ret)
>>>> +        return ret;
>>>> +
>>>> +    spin_lock(&xen_domain->lock);
>>>> +
>>>> +    /*
>>>> +     * Check to see if an iommu_domain already exists for this xen 
>>>> domain
>>>> +     * under the same SMMU
>>>> +     */
>>>> +    domain = arm_smmu_get_domain(d, dev);
>>>> +    if (!domain) {
>>>> +
>>>> +        domain = arm_smmu_domain_alloc(IOMMU_DOMAIN_DMA);
>>>> +        if (!domain) {
>>>> +            ret = -ENOMEM;
>>>> +            goto out;
>>>> +        }
>>>> +
>>>> +        arm_smmu = to_smmu_domain(domain);
>>>> +        arm_smmu->s2_cfg.domain = d;
>>>> +
>>>> +        /* Chain the new context to the domain */
>>>> +        list_add(&domain->list, &xen_domain->contexts);
>>>> +
>>>> +    }
>>>> +
>>>> +    ret = arm_smmu_attach_dev(domain, dev);
>>>> +    if (ret) {
>>>> +        if (domain->ref.counter == 0)
>>>> +            arm_smmu_destroy_iommu_domain(domain);
>>>> +    } else {
>>>> +        atomic_inc(&domain->ref);
>>>> +    }
>>>> +
>>>> +out:
>>>> +    spin_unlock(&xen_domain->lock);
>>>> +    return ret;
>>>> +}
>>>> +
>>>> +static int arm_smmu_deassign_dev(struct domain *d, struct device *dev)
>>>> +{
>>>> +    struct iommu_domain *domain = arm_smmu_get_domain(d, dev);
>>>> +    struct arm_smmu_xen_domain *xen_domain;
>>>> +    struct arm_smmu_domain *arm_smmu = to_smmu_domain(domain);
>>>> +
>>>> +    xen_domain = dom_iommu(d)->arch.priv;
>>>> +
>>>> +    if (!arm_smmu || arm_smmu->s2_cfg.domain != d) {
>>>> +        dev_err(dev, " not attached to domain %d\n", d->domain_id);
>>>> +        return -ESRCH;
>>>> +    }
>>>> +
>>>> +    spin_lock(&xen_domain->lock);
>>>> +
>>>> +    arm_smmu_detach_dev(dev);
>>>> +    atomic_dec(&domain->ref);
>>>> +
>>>> +    if (domain->ref.counter == 0)
>>>> +        arm_smmu_destroy_iommu_domain(domain);
>>>> +
>>>> +    spin_unlock(&xen_domain->lock);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static int arm_smmu_reassign_dev(struct domain *s, struct domain *t,
>>>> +                 u8 devfn,  struct device *dev)
>>>> +{
>>>> +    int ret = 0;
>>>> +
>>>> +    /* Don't allow remapping on other domain than hwdom */
>>>> +    if (t && t != hardware_domain)
>>>> +        return -EPERM;
>>>> +
>>>> +    if (t == s)
>>>> +        return 0;
>>>> +
>>>> +    ret = arm_smmu_deassign_dev(s, dev);
>>>> +    if (ret)
>>>> +        return ret;
>>>> +
>>>> +    if (t) {
>>>> +        /* No flags are defined for ARM. */
>>>> +        ret = arm_smmu_assign_dev(t, devfn, dev, 0);
>>>> +        if (ret)
>>>> +            return ret;
>>>> +    }
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static int arm_smmu_iommu_domain_init(struct domain *d)
>>>> +{
>>>> +    struct arm_smmu_xen_domain *xen_domain;
>>>> +
>>>> +    xen_domain = xzalloc(struct arm_smmu_xen_domain);
>>>> +    if (!xen_domain)
>>>> +        return -ENOMEM;
>>>> +
>>>> +    spin_lock_init(&xen_domain->lock);
>>>> +    INIT_LIST_HEAD(&xen_domain->contexts);
>>>> +
>>>> +    dom_iommu(d)->arch.priv = xen_domain;
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static void __hwdom_init arm_smmu_iommu_hwdom_init(struct domain *d)
>>>> +{
>>>> +}
>>>> +
>>>> +static void arm_smmu_iommu_domain_teardown(struct domain *d)
>>>> +{
>>>> +    struct arm_smmu_xen_domain *xen_domain = dom_iommu(d)->arch.priv;
>>>> +
>>>> +    ASSERT(list_empty(&xen_domain->contexts));
>>>> +    xfree(xen_domain);
>>>> +}
>>>> +
>>>> +static int __must_check arm_smmu_map_page(struct domain *d, 
>>>> unsigned long gfn,
>>>> +            unsigned long mfn, unsigned int flags)
>>>> +{
>>>> +    p2m_type_t t;
>>>> +
>>>> +    /*
>>>> +     * Grant mappings can be used for DMA requests. The dev_bus_addr
>>>> +     * returned by the hypercall is the MFN (not the IPA). For device
>>>> +     * protected by an IOMMU, Xen needs to add a 1:1 mapping in the 
>>>> domain
>>>> +     * p2m to allow DMA request to work.
>>>> +     * This is only valid when the domain is directed mapped. Hence 
>>>> this
>>>> +     * function should only be used by gnttab code with gfn == mfn.
>>>> +     */
>>>> +    BUG_ON(!is_domain_direct_mapped(d));
>>>> +    BUG_ON(mfn != gfn);
>>>> +
>>>> +    /* We only support readable and writable flags */
>>>> +    if (!(flags & (IOMMUF_readable | IOMMUF_writable)))
>>>> +        return -EINVAL;
>>>> +
>>>> +    t = (flags & IOMMUF_writable) ? p2m_iommu_map_rw : 
>>>> p2m_iommu_map_ro;
>>>> +
>>>> +    /*
>>>> +     * The function guest_physmap_add_entry replaces the current 
>>>> mapping
>>>> +     * if there is already one...
>>>> +     */
>>>> +    return guest_physmap_add_entry(d, _gfn(gfn), _mfn(mfn), 0, t);
>>>> +}
>>>> +
>>>> +static int __must_check arm_smmu_unmap_page(struct domain *d, 
>>>> unsigned long gfn)
>>>> +{
>>>> +    /*
>>>> +     * This function should only be used by gnttab code when the 
>>>> domain
>>>> +     * is direct mapped
>>>> +     */
>>>> +    if (!is_domain_direct_mapped(d))
>>>> +        return -EINVAL;
>>>> +
>>>> +    return guest_physmap_remove_page(d, _gfn(gfn), _mfn(gfn), 0);
>>>> +}
>>>> +
>>>> +static const struct iommu_ops arm_smmu_iommu_ops = {
>>>> +    .init = arm_smmu_iommu_domain_init,
>>>> +    .hwdom_init = arm_smmu_iommu_hwdom_init,
>>>> +    .teardown = arm_smmu_iommu_domain_teardown,
>>>> +    .iotlb_flush = arm_smmu_iotlb_flush,
>>>> +    .iotlb_flush_all = arm_smmu_iotlb_flush_all,
>>>> +    .assign_device = arm_smmu_assign_dev,
>>>> +    .reassign_device = arm_smmu_reassign_dev,
>>>> +    .map_page = arm_smmu_map_page,
>>>> +    .unmap_page = arm_smmu_unmap_page,
>>>> +};
>>>> +
>>>> +static
>>>> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle 
>>>> *fwnode)
>>>> +{
>>>> +    struct arm_smmu_device *smmu = NULL;
>>>> +
>>>> +    spin_lock(&arm_smmu_devices_lock);
>>>> +    list_for_each_entry(smmu, &arm_smmu_devices, devices) {
>>>> +        if (smmu->dev->fwnode == fwnode)
>>>> +            break;
>>>> +    }
>>>> +    spin_unlock(&arm_smmu_devices_lock);
>>>> +
>>>> +    return smmu;
>>>> +}
>>>> +
>>>> +static __init int arm_smmu_dt_init(struct dt_device_node *dev,
>>>> +                   const void *data)
>>>> +{
>>>> +    int rc;
>>>> +
>>>> +    /*
>>>> +     * Even if the device can't be initialized, we don't want to
>>>> +     * give the SMMU device to dom0.
>>>> +     */
>>>> +    dt_device_set_used_by(dev, DOMID_XEN);
>>>> +
>>>> +    rc = arm_smmu_device_probe(dt_to_dev(dev));
>>>> +    if (rc)
>>>> +        return rc;
>>>> +
>>>> +    iommu_set_ops(&arm_smmu_iommu_ops);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +DT_DEVICE_START(smmuv3, "ARM SMMU V3", DEVICE_IOMMU)
>>>> +    .dt_match = arm_smmu_of_match,
>>>> +    .init = arm_smmu_dt_init,
>>>> +DT_DEVICE_END
>>>> +
>>>> +#ifdef CONFIG_ACPI
>>>> +/* Set up the IOMMU */
>>>> +static int __init arm_smmu_acpi_init(const void *data)
>>>> +{
>>>> +    int rc;
>>>> +
>>>> +    rc = arm_smmu_device_probe((struct device *)data);
>>>> +    if (rc)
>>>> +        return rc;
>>>> +
>>>> +    iommu_set_ops(&arm_smmu_iommu_ops);
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +ACPI_DEVICE_START(asmmuv3, "ARM SMMU V3", DEVICE_IOMMU)
>>>> +    .class_type = ACPI_IORT_NODE_SMMU_V3,
>>>> +    .init = arm_smmu_acpi_init,
>>>> +ACPI_DEVICE_END
>>>> +
>>>> +#endif
>>>> diff --git a/xen/include/xen/linux_compat.h 
>>>> b/xen/include/xen/linux_compat.h
>>>> new file mode 100644
>>>> index 0000000000..8037be0a3e
>>>> --- /dev/null
>>>> +++ b/xen/include/xen/linux_compat.h
>>>> @@ -0,0 +1,84 @@
>>>> +/****************************************************************************** 
>>>>
>>>> + * include/xen/linux_compat.h
>>>> + *
>>>> + * Compatibility defines for porting code from Linux to Xen
>>>> + *
>>>> + * Copyright (c) 2017 Linaro Limited
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or 
>>>> modify
>>>> + * it under the terms of the GNU General Public License as 
>>>> published by
>>>> + * the Free Software Foundation; either version 2 of the License, or
>>>> + * (at your option) any later version.
>>>> + *
>>>> + * This program is distributed in the hope that it will be useful,
>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>> + * GNU General Public License for more details.
>>>> + *
>>>> + * You should have received a copy of the GNU General Public License
>>>> + * along with this program; If not, see 
>>>> <http://www.gnu.org/licenses/>.
>>>> + */
>>>> +
>>>> +#ifndef __XEN_LINUX_COMPAT_H__
>>>> +#define __XEN_LINUX_COMPAT_H__
>>>> +
>>>> +#include <asm/types.h>
>>>> +
>>>> +typedef paddr_t phys_addr_t;
>>>> +typedef paddr_t dma_addr_t;
>>>> +
>>>> +typedef unsigned int gfp_t;
>>>> +#define GFP_KERNEL 0
>>>> +#define __GFP_ZERO 0x01U
>>>> +
>>>> +/* Helpers for IRQ functions */
>>>> +#define free_irq release_irq
>>>> +
>>>> +enum irqreturn {
>>>> +    IRQ_NONE,
>>>> +    IRQ_HANDLED,
>>>> +    IRQ_WAKE_THREAD,
>>>> +};
>>>> +
>>>> +typedef enum irqreturn irqreturn_t;
>>>> +
>>>> +/* Device logger functions */
>>>> +#define dev_dbg(dev, fmt, ...) printk(XENLOG_DEBUG fmt, ## 
>>>> __VA_ARGS__)
>>>> +#define dev_notice(dev, fmt, ...) printk(XENLOG_INFO fmt, ## 
>>>> __VA_ARGS__)
>>>> +#define dev_warn(dev, fmt, ...) printk(XENLOG_WARNING fmt, ## 
>>>> __VA_ARGS__)
>>>> +#define dev_err(dev, fmt, ...) printk(XENLOG_ERR fmt, ## __VA_ARGS__)
>>>> +#define dev_info(dev, fmt, ...) printk(XENLOG_INFO fmt, ## 
>>>> __VA_ARGS__)
>>>> +
>>>> +#define dev_err_ratelimited(dev, fmt, ...)                  \
>>>> +     printk(XENLOG_ERR fmt, ## __VA_ARGS__)
>>>> +
>>>> +#define dev_name(dev) dt_node_full_name(dev_to_dt(dev))
>>>> +
>>>> +/* Alias to Xen allocation helpers */
>>>> +#define kfree xfree
>>>> +#define kmalloc(size, flags) ({\
>>>> +    void *__ret_alloc = NULL; \
>>>> +    if (flags & __GFP_ZERO) \
>>>> +        __ret_alloc = _xzalloc(size, sizeof(void *)); \
>>>> +    else \
>>>> +        __ret_alloc = _xmalloc(size, sizeof(void *)); \
>>>> +    __ret_alloc; \
>>>> +})
>>>> +#define kzalloc(size, flags)        _xzalloc(size, sizeof(void *))
>>>> +#define devm_kzalloc(dev, size, flags)  _xzalloc(size, sizeof(void *))
>>>> +#define kmalloc_array(size, n, flags) ({\
>>>> +    void *__ret_alloc = NULL; \
>>>> +    if (flags & __GFP_ZERO) \
>>>> +        __ret_alloc = _xzalloc_array(size, sizeof(void *), n); \
>>>> +    else \
>>>> +        __ret_alloc = _xmalloc_array(size, sizeof(void *), n); \
>>>> +    __ret_alloc; \
>>>> +})
>>>> +
>>>> +/* Alias to Xen time functions */
>>>> +#define ktime_t s_time_t
>>>> +#define ktime_get()             (NOW())
>>>> +#define ktime_add_us(t,i)       (t + MICROSECS(i))
>>>> +#define ktime_compare(t,i)      (t > (i))
>>>> +
>>>> +#endif /* __XEN_LINUX_COMPAT_H__ */
>>>
>>>
>>> _______________________________________________
>>> Xen-devel mailing list
>>> Xen-devel@lists.xenproject.org
>>> https://lists.xenproject.org/mailman/listinfo/xen-devel
>>
> 
> 
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xenproject.org
> https://lists.xenproject.org/mailman/listinfo/xen-devel

On 5/9/2018 2:58 AM, Julien Grall wrote:
>
>
> On 09/05/2018 09:30, Manish Jaggi wrote:
>>
>>
>> On 04/19/2018 04:24 PM, Manish Jaggi wrote:
>>> Sorry for top posting,
>>>
>>> is someone working on the comments on this patch?
>>>
>>> -Manish
>>>
>> If no one is working this code anymore, I would like to pick it up and continue maintaining it.
>> Is it fine with all?
>
> Last time I spoke with Sameer he was planning to resend a series. And I would prefer if he continue to lead the series unless stated otherwise.
I am working on addressing the comments in this patch set. Please expect something by end of next week.
>
> Cheers,
>
>>
>> -Regards
>> Manish
>>>
>>> On 03/10/2018 11:23 PM, Manish Jaggi wrote:
>>>> Hi Sameer,
>>>>
>>>>
>>>> On 02/09/2018 08:40 AM, Sameer Goel wrote:
>>>>> This driver follows an approach similar to smmu driver. The intent here
>>>>> is to reuse as much Linux code as possible.
>>>>> - Glue code has been introduced to bridge the API calls.
>>>>> - Called Linux functions from the Xen IOMMU function calls.
>>>>> - Xen modifications are preceded by /*Xen: comment */
>>>>> - xen/linux_compat: Add a Linux compat header
>>>>>    For porting files directly from Linux it is useful to have a function mapping
>>>>>    definitions from Linux to Xen. This file adds common API functions and
>>>>>    other defines that are needed for porting arm SMMU drivers.
>>>>>
>>>>> Signed-off-by: Sameer Goel <sameer.goel@linaro.org>
>>>>> ---
>>>>>   xen/arch/arm/p2m.c                    |   1 +
>>>>>   xen/drivers/Kconfig                   |   2 +
>>>>>   xen/drivers/passthrough/arm/Kconfig   |   8 +
>>>>>   xen/drivers/passthrough/arm/Makefile  |   1 +
>>>>>   xen/drivers/passthrough/arm/smmu-v3.c | 892 ++++++++++++++++++++++++++++++++--
>>>>>   xen/include/xen/linux_compat.h        |  84 ++++
>>>>>   6 files changed, 959 insertions(+), 29 deletions(-)
>>>>>   create mode 100644 xen/drivers/passthrough/arm/Kconfig
>>>>>   create mode 100644 xen/include/xen/linux_compat.h
>>>>>
>>>>> diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
>>>>> index 65e8b9c6ea..fef7605fd6 100644
>>>>> --- a/xen/arch/arm/p2m.c
>>>>> +++ b/xen/arch/arm/p2m.c
>>>>> @@ -1460,6 +1460,7 @@ err:
>>>>>   static void __init setup_virt_paging_one(void *data)
>>>>>   {
>>>>>       unsigned long val = (unsigned long)data;
>>>>> +    /* SMMUv3 S2 cfg vtcr reuses the following value */
>>>>>       WRITE_SYSREG32(val, VTCR_EL2);
>>>>>       isb();
>>>>>   }
>>>>> diff --git a/xen/drivers/Kconfig b/xen/drivers/Kconfig
>>>>> index bc3a54f0ea..612655386d 100644
>>>>> --- a/xen/drivers/Kconfig
>>>>> +++ b/xen/drivers/Kconfig
>>>>> @@ -12,4 +12,6 @@ source "drivers/pci/Kconfig"
>>>>>     source "drivers/video/Kconfig"
>>>>>   +source "drivers/passthrough/arm/Kconfig"
>>>>> +
>>>>>   endmenu
>>>>> diff --git a/xen/drivers/passthrough/arm/Kconfig b/xen/drivers/passthrough/arm/Kconfig
>>>>> new file mode 100644
>>>>> index 0000000000..cda899f608
>>>>> --- /dev/null
>>>>> +++ b/xen/drivers/passthrough/arm/Kconfig
>>>>> @@ -0,0 +1,8 @@
>>>>> +
>>>>> +config ARM_SMMU_v3
>>>>> +    bool "ARM SMMUv3 Support"
>>>>> +    depends on ARM_64
>>>>> +    help
>>>>> +     Support for implementations of the ARM System MMU architecture
>>>>> +     version 3.
>>>>> +
>>>>> diff --git a/xen/drivers/passthrough/arm/Makefile b/xen/drivers/passthrough/arm/Makefile
>>>>> index f4cd26e15d..e14732b55c 100644
>>>>> --- a/xen/drivers/passthrough/arm/Makefile
>>>>> +++ b/xen/drivers/passthrough/arm/Makefile
>>>>> @@ -1,2 +1,3 @@
>>>>>   obj-y += iommu.o
>>>>>   obj-y += smmu.o
>>>>> +obj-$(CONFIG_ARM_SMMU_v3) += smmu-v3.o
>>>>> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c
>>>>> index e67ba6c40f..f43485fe6e 100644
>>>>> --- a/xen/drivers/passthrough/arm/smmu-v3.c
>>>>> +++ b/xen/drivers/passthrough/arm/smmu-v3.c
>>>>> @@ -18,28 +18,414 @@
>>>>>    * Author: Will Deacon <will.deacon@arm.com>
>>>>>    *
>>>>>    * This driver is powered by bad coffee and bombay mix.
>>>>> + *
>>>>> + *
>>>>> + * Based on Linux drivers/iommu/arm-smmu-v3.c
>>>>> + * => commit 7aa8619a66aea52b145e04cbab4f8d6a4e5f3f3b
>>>>> + *
>>>>> + * Xen modifications:
>>>>> + * Sameer Goel <sameer.goel@linaro.org>
>>>>> + * Copyright (C) 2017, The Linux Foundation, All rights reserved.
>>>>> + *
>>>>> + */
>>>>> +
>>>>> +#include <xen/acpi.h>
>>>>> +#include <xen/config.h>
>>>>> +#include <xen/delay.h>
>>>>> +#include <xen/errno.h>
>>>>> +#include <xen/err.h>
>>>>> +#include <xen/irq.h>
>>>>> +#include <xen/lib.h>
>>>>> +#include <xen/linux_compat.h>
>>>>> +#include <xen/list.h>
>>>>> +#include <xen/mm.h>
>>>>> +#include <xen/rbtree.h>
>>>>> +#include <xen/sched.h>
>>>>> +#include <xen/sizes.h>
>>>>> +#include <xen/vmap.h>
>>>>> +#include <acpi/acpi_iort.h>
>>>>> +#include <asm/atomic.h>
>>>>> +#include <asm/device.h>
>>>>> +#include <asm/io.h>
>>>>> +#include <asm/platform.h>
>>>>> +
>>>>> +/* Alias to Xen device tree helpers */
>>>>> +#define device_node dt_device_node
>>>>> +#define of_phandle_args dt_phandle_args
>>>>> +#define of_device_id dt_device_match
>>>>> +#define of_match_node dt_match_node
>>>>> +#define of_property_read_u32(np, pname, out) (!dt_property_read_u32(np, pname, out))
>>>>> +#define of_property_read_bool dt_property_read_bool
>>>>> +#define of_parse_phandle_with_args dt_parse_phandle_with_args
>>>>> +
>>>>> +/* Xen: Helpers to get device MMIO and IRQs */
>>>>> +struct resource {
>>>>> +    u64 addr;
>>>>> +    u64 size;
>>>>> +    unsigned int type;
>>>>> +};
>>>>> +
>>>>> +#define resource_size(res) ((res)->size)
>>>>> +
>>>>> +#define platform_device device
>>>>> +
>>>>> +#define IORESOURCE_MEM 0
>>>>> +#define IORESOURCE_IRQ 1
>>>>> +
>>>>> +static struct resource *platform_get_resource(struct platform_device *pdev,
>>>>> +                          unsigned int type,
>>>>> +                          unsigned int num)
>>>>> +{
>>>>> +    /*
>>>>> +     * The resource is only used between 2 calls of platform_get_resource.
>>>>> +     * It's quite ugly but it's avoid to add too much code in the part
>>>>> +     * imported from Linux
>>>>> +     */
>>>>> +    static struct resource res;
>>>>> +    struct acpi_iort_node *iort_node;
>>>>> +    struct acpi_iort_smmu_v3 *node_smmu_data;
>>>>> +    int ret = 0;
>>>>> +
>>>>> +    res.type = type;
>>>>> +
>>>>> +    switch (type) {
>>>>> +    case IORESOURCE_MEM:
>>>>> +        if (pdev->type == DEV_ACPI) {
>>>>> +            ret = 1;
>>>>> +            iort_node = pdev->acpi_node;
>>>>> +            node_smmu_data =
>>>>> +                (struct acpi_iort_smmu_v3 *)iort_node->node_data;
>>>>> +
>>>>> +            if (node_smmu_data != NULL) {
>>>>> +                res.addr = node_smmu_data->base_address;
>>>>> +                res.size = SZ_128K;
>>>>> +                ret = 0;
>>>>> +            }
>>>>> +        } else {
>>>>> +            ret = dt_device_get_address(dev_to_dt(pdev), num,
>>>>> +                            &res.addr, &res.size);
>>>>> +        }
>>>>> +
>>>>> +        return ((ret) ? NULL : &res);
>>>>> +
>>>>> +    case IORESOURCE_IRQ:
>>>>> +        /* ACPI case not implemented as there is no use case for it */
>>>>> +        ret = platform_get_irq(dev_to_dt(pdev), num);
>>>>> +
>>>>> +        if (ret < 0)
>>>>> +            return NULL;
>>>>> +
>>>>> +        res.addr = ret;
>>>>> +        res.size = 1;
>>>>> +
>>>>> +        return &res;
>>>>> +
>>>>> +    default:
>>>>> +        return NULL;
>>>>> +    }
>>>>> +}
>>>>> +
>>>>> +static int platform_get_irq_byname(struct platform_device *pdev, const char *name)
>>>>> +{
>>>>> +    const struct dt_property *dtprop;
>>>>> +    struct acpi_iort_node *iort_node;
>>>>> +    struct acpi_iort_smmu_v3 *node_smmu_data;
>>>>> +    int ret = 0;
>>>>> +
>>>>> +    if (pdev->type == DEV_ACPI) {
>>>>> +        iort_node = pdev->acpi_node;
>>>>> +        node_smmu_data = (struct acpi_iort_smmu_v3 *)iort_node->node_data;
>>>>> +
>>>>> +        if (node_smmu_data != NULL) {
>>>>> +            if (!strcmp(name, "eventq"))
>>>>> +                ret = node_smmu_data->event_gsiv;
>>>>> +            else if (!strcmp(name, "priq"))
>>>>> +                ret = node_smmu_data->pri_gsiv;
>>>>> +            else if (!strcmp(name, "cmdq-sync"))
>>>>> +                ret = node_smmu_data->sync_gsiv;
>>>>> +            else if (!strcmp(name, "gerror"))
>>>>> +                ret = node_smmu_data->gerr_gsiv;
>>>>> +            else
>>>>> +                ret = -EINVAL;
>>>>> +        }
>>>>> +    } else {
>>>>> +        dtprop = dt_find_property(dev_to_dt(pdev), "interrupt-names", NULL);
>>>>> +        if (!dtprop)
>>>>> +            return -EINVAL;
>>>>> +
>>>>> +        if (!dtprop->value)
>>>>> +            return -ENODATA;
>>>>> +    }
>>>>> +
>>>>> +    return ret;
>>>>> +}
>>>>> +
>>>>> +/*
>>>>> + * Xen: Helpers for DMA allocation. Just the function name is reused for
>>>>> + * porting code these allocation are not managed allocations
>>>>>    */
>>>>>   -#include <linux/acpi.h>
>>>>> -#include <linux/acpi_iort.h>
>>>>> -#include <linux/delay.h>
>>>>> -#include <linux/dma-iommu.h>
>>>>> -#include <linux/err.h>
>>>>> -#include <linux/interrupt.h>
>>>>> -#include <linux/iommu.h>
>>>>> -#include <linux/iopoll.h>
>>>>> -#include <linux/module.h>
>>>>> -#include <linux/msi.h>
>>>>> -#include <linux/of.h>
>>>>> -#include <linux/of_address.h>
>>>>> -#include <linux/of_iommu.h>
>>>>> -#include <linux/of_platform.h>
>>>>> -#include <linux/pci.h>
>>>>> -#include <linux/platform_device.h>
>>>>> -
>>>>> -#include <linux/amba/bus.h>
>>>>> -
>>>>> -#include "io-pgtable.h"
>>>>> +static void *dmam_alloc_coherent(struct device *dev, size_t size,
>>>>> +               dma_addr_t *dma_handle, gfp_t gfp)
>>>>> +{
>>>>> +    void *vaddr;
>>>>> +    unsigned long alignment = size;
>>>>> +
>>>>> +    /*
>>>>> +     * _xzalloc requires that the (align & (align -1)) = 0. Most of the
>>>>> +     * allocations in SMMU code should send the right value for size. In
>>>>> +     * case this is not true print a warning and align to the size of a
>>>>> +     * (void *)
>>>>> +     */
>>>>> +    if (size & (size - 1)) {
>>>>> +        dev_warn(dev, "Fixing alignment for the DMA buffer\n");
>>>>> +        alignment = sizeof(void *);
>>>>> +    }
>>>>> +
>>>>> +    vaddr = _xzalloc(size, alignment);
>>>>> +    if (!vaddr) {
>>>>> +        dev_err(dev, "DMA allocation failed\n");
>>>>> +        return NULL;
>>>>> +    }
>>>>> +
>>>>> +    *dma_handle = virt_to_maddr(vaddr);
>>>>> +
>>>>> +    return vaddr;
>>>>> +}
>>>>> +
>>>>> +
>>>>> +static void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
>>>>> +            dma_addr_t dma_handle)
>>>>> +{
>>>>> +    xfree(vaddr);
>>>>> +}
>>>>> +
>>>>> +/* Xen: Stub out DMA domain related functions */
>>>>> +#define iommu_get_dma_cookie(dom) 0
>>>>> +#define iommu_put_dma_cookie(dom)
>>>>> +
>>>>> +/* Xen: Stub out module param related function */
>>>>> +#define module_param_named(a, b, c, d)
>>>>> +#define MODULE_PARM_DESC(a, b)
>>>>> +
>>>>> +#define dma_set_mask_and_coherent(d, b) 0
>>>>> +
>>>>> +#define of_dma_is_coherent(n) 0
>>>>> +
>>>>> +#define MODULE_DEVICE_TABLE(type, name)
>>>>> +
>>>>> +static void __iomem *devm_ioremap_resource(struct device *dev,
>>>>> +                       struct resource *res)
>>>>> +{
>>>>> +    void __iomem *ptr;
>>>>> +
>>>>> +    if (!res || res->type != IORESOURCE_MEM) {
>>>>> +        dev_err(dev, "Invalid resource\n");
>>>>> +        return ERR_PTR(-EINVAL);
>>>>> +    }
>>>>> +
>>>>> +    ptr = ioremap_nocache(res->addr, res->size);
>>>>> +    if (!ptr) {
>>>>> +        dev_err(dev,
>>>>> +            "ioremap failed (addr 0x%"PRIx64" size 0x%"PRIx64")\n",
>>>>> +            res->addr, res->size);
>>>>> +        return ERR_PTR(-ENOMEM);
>>>>> +    }
>>>>> +
>>>>> +    return ptr;
>>>>> +}
>>>>> +
>>>>> +/* Xen: Compatibility define for iommu_domain_geometry.*/
>>>>> +struct iommu_domain_geometry {
>>>>> +    dma_addr_t aperture_start; /* First address that can be mapped    */
>>>>> +    dma_addr_t aperture_end;   /* Last address that can be mapped     */
>>>>> +    bool force_aperture;       /* DMA only allowed in mappable range? */
>>>>> +};
>>>>> +
>>>>> +
>>>>> +/* Xen: Type definitions for iommu_domain */
>>>>> +#define IOMMU_DOMAIN_UNMANAGED 0
>>>>> +#define IOMMU_DOMAIN_DMA 1
>>>>> +#define IOMMU_DOMAIN_IDENTITY 2
>>>>> +
>>>>> +/* Xen: Dummy iommu_domain */
>>>>> +struct iommu_domain {
>>>>> +    /* Runtime SMMU configuration for this iommu_domain */
>>>>> +    struct arm_smmu_domain        *priv;
>>>>> +    unsigned int type;
>>>>> +
>>>>> +    /* Dummy compatibility defines */
>>>>> +    unsigned long pgsize_bitmap;
>>>>> +    struct iommu_domain_geometry geometry;
>>>>> +
>>>>> +    atomic_t ref;
>>>>> +    /*
>>>>> +     * Used to link iommu_domain contexts for a same domain.
>>>>> +     * There is at least one per-SMMU to used by the domain.
>>>>> +     */
>>>>> +    struct list_head        list;
>>>>> +};
>>>>> +
>>>>> +/* Xen: Describes information required for a Xen domain */
>>>>> +struct arm_smmu_xen_domain {
>>>>> +    spinlock_t            lock;
>>>>> +    /* List of iommu domains associated to this domain */
>>>>> +    struct list_head        contexts;
>>>>> +};
>>>>> +
>>>>> +/*
>>>>> + * Xen: Information about each device stored in dev->archdata.iommu
>>>>> + *
>>>>> + * The dev->archdata.iommu stores the iommu_domain (runtime configuration of
>>>>> + * the SMMU).
>>>>> + */
>>>>> +struct arm_smmu_xen_device {
>>>>> +    struct iommu_domain *domain;
>>>>> +};
>>>>> +
>>>>> +/*
>>>>> + * Xen: io_pgtable compatibility defines.
>>>>> + * Most of these are to port in the S1 translation code as is.
>>>>> + */
>>>>> +struct io_pgtable_ops {
>>>>> +};
>>>>> +
>>>>> +struct iommu_gather_ops {
>>>>> +    void (*tlb_flush_all)(void *cookie);
>>>>> +    void (*tlb_add_flush)(unsigned long iova, size_t size, size_t granule,
>>>>> +                  bool leaf, void *cookie);
>>>>> +    void (*tlb_sync)(void *cookie);
>>>>> +};
>>>>> +
>>>>> +struct io_pgtable_cfg {
>>>>> +    /*
>>>>> +     * IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE bits in
>>>>> +     *    stage 1 PTEs, for hardware which insists on validating them
>>>>> +     *    even in    non-secure state where they should normally be ignored.
>>>>> +     *
>>>>> +     * IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE and
>>>>> +     *    IOMMU_NOEXEC flags and map everything with full access, for
>>>>> +     *    hardware which does not implement the permissions of a given
>>>>> +     *    format, and/or requires some format-specific default value.
>>>>> +     *
>>>>> +     * IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching invalid
>>>>> +     *    (unmapped) entries but the hardware might do so anyway, perform
>>>>> +     *    TLB maintenance when mapping as well as when unmapping.
>>>>> +     *
>>>>> +     * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
>>>>> +     *    PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
>>>>> +     *    when the SoC is in "4GB mode" and they can only access the high
>>>>> +     *    remap of DRAM (0x1_00000000 to 0x1_ffffffff).
>>>>> +     *
>>>>> +     * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
>>>>> +     *    be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
>>>>> +     *    software-emulated IOMMU), such that pagetable updates need not
>>>>> +     *    be treated as explicit DMA data.
>>>>> +     */
>>>>> +    #define IO_PGTABLE_QUIRK_ARM_NS        BIT(0)
>>>>> +    #define IO_PGTABLE_QUIRK_NO_PERMS    BIT(1)
>>>>> +    #define IO_PGTABLE_QUIRK_TLBI_ON_MAP    BIT(2)
>>>>> +    #define IO_PGTABLE_QUIRK_ARM_MTK_4GB    BIT(3)
>>>>> +    #define IO_PGTABLE_QUIRK_NO_DMA        BIT(4)
>>>>> +    unsigned long            quirks;
>>>>> +    unsigned long            pgsize_bitmap;
>>>>> +    unsigned int            ias;
>>>>> +    unsigned int            oas;
>>>>> +    const struct iommu_gather_ops    *tlb;
>>>>> +    struct device            *iommu_dev;
>>>>> +
>>>>> +    /* Low-level data specific to the table format */
>>>>> +    union {
>>>>> +        struct {
>>>>> +            u64    ttbr[2];
>>>>> +            u64    tcr;
>>>>> +            u64    mair[2];
>>>>> +        } arm_lpae_s1_cfg;
>>>>> +
>>>>> +        struct {
>>>>> +            u64    vttbr;
>>>>> +            u64    vtcr;
>>>>> +        } arm_lpae_s2_cfg;
>>>>> +
>>>>> +        struct {
>>>>> +            u32    ttbr[2];
>>>>> +            u32    tcr;
>>>>> +            u32    nmrr;
>>>>> +            u32    prrr;
>>>>> +        } arm_v7s_cfg;
>>>>> +    };
>>>>> +};
>>>>> +
>>>>> +enum io_pgtable_fmt {
>>>>> +    ARM_32_LPAE_S1,
>>>>> +    ARM_32_LPAE_S2,
>>>>> +    ARM_64_LPAE_S1,
>>>>> +    ARM_64_LPAE_S2,
>>>>> +    ARM_V7S,
>>>>> +    IO_PGTABLE_NUM_FMTS,
>>>>> +};
>>>>> +
>>>>> +/*
>>>>> + * Xen: The pgtable_ops are used by the S1 translations, so return the dummy
>>>>> + * address.
>>>>> + */
>>>>> +#define alloc_io_pgtable_ops(f, c, o) ((struct io_pgtable_ops *)0x0)
>>>> Is this correct? it will make the caller null check fail
>>>>> +#define free_io_pgtable_ops(o)
>>>>> +
>>>>> +/* Xen: Define wrapper for requesting IRQs */
>>>>> +#define IRQF_ONESHOT 0
>>>>> +
>>>>> +typedef void (*irq_handler_t)(int, void *, struct cpu_user_regs *);
>>>>> +
>>>>> +static inline int devm_request_irq(struct device *dev, unsigned int irq,
>>>>> +                   irq_handler_t handler, unsigned long irqflags,
>>>>> +                   const char *devname, void *dev_id)
>>>>> +{
>>>>> +    /*
>>>>> +     * SMMUv3 implementation can support wired interrupt outputs that are
>>>>> +     * edge-triggered. Set the irq type as per the spec.
>>>>> +     */
>>>>> +    irq_set_type(irq, IRQ_TYPE_EDGE_BOTH);
>>>>> +    return request_irq(irq, irqflags, handler, devname, dev_id);
>>>>> +}
>>>>> +
>>>>> +/*
>>>>> + * Xen does not have a concept of threaded irq, but eventually we can use
>>>>> + * tasklets to optimize the following function.
>>>>> + */
>>>>> +int devm_request_threaded_irq(struct device *dev, unsigned int irq, irq_handler_t handler,
>>>>> +                  irq_handler_t thread_fn, unsigned long irqflags,
>>>>> +                  const char *devname, void *dev_id)
>>>>> +{
>>>>> +    return devm_request_irq(dev, irq, thread_fn, irqflags, devname, dev_id);
>>>>> +}
>>>>> +
>>>>> +/* Xen: The mutex is used only during initialization so the typecast is safe */
>>>>> +#define mutex spinlock
>>>>> +#define mutex_init spin_lock_init
>>>>> +#define mutex_lock spin_lock
>>>>> +#define mutex_unlock spin_unlock
>>>>> +
>>>>> +#define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \
>>>>> +({ \
>>>>> +    s_time_t deadline = NOW() + MICROSECS(timeout_us); \
>>>>> +    for (;;) { \
>>>>> +        (val) = op(addr); \
>>>>> +        if (cond) \
>>>>> +            break; \
>>>>> +        if (NOW() > deadline) { \
>>>>> +            (val) = op(addr); \
>>>>> +            break; \
>>>>> +        } \
>>>>> +    udelay(sleep_us); \
>>>>> +    } \
>>>>> +    (cond) ? 0 : -ETIMEDOUT; \
>>>>> +})
>>>>> +
>>>>> +#define readl_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \
>>>>> +    readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, timeout_us)
>>>>> +
>>>>> +#define VA_BITS 0 /* Only needed for S1 translations */
>>>>>     /* MMIO registers */
>>>>>   #define ARM_SMMU_IDR0            0x0
>>>>> @@ -433,6 +819,7 @@ enum pri_resp {
>>>>>       PRI_RESP_SUCC,
>>>>>   };
>>>>>   +#if 0 /* Xen: No MSI support in this iteration */
>>>>>   enum arm_smmu_msi_index {
>>>>>       EVTQ_MSI_INDEX,
>>>>>       GERROR_MSI_INDEX,
>>>>> @@ -457,6 +844,7 @@ static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
>>>>>           ARM_SMMU_PRIQ_IRQ_CFG2,
>>>>>       },
>>>>>   };
>>>>> +#endif
>>>>>     struct arm_smmu_cmdq_ent {
>>>>>       /* Common fields */
>>>>> @@ -561,6 +949,8 @@ struct arm_smmu_s2_cfg {
>>>>>       u16                vmid;
>>>>>       u64                vttbr;
>>>>>       u64                vtcr;
>>>>> +    /* Xen: Domain associated to this configuration */
>>>>> +    struct domain            *domain;
>>>>>   };
>>>>>     struct arm_smmu_strtab_ent {
>>>>> @@ -635,9 +1025,21 @@ struct arm_smmu_device {
>>>>>       struct arm_smmu_strtab_cfg    strtab_cfg;
>>>>>         /* IOMMU core code handle */
>>>>> +#if 0 /*Xen: Generic iommu_device ref not needed here */
>>>>>       struct iommu_device        iommu;
>>>>> +#endif
>>>>> +    /* Xen: Need to keep a list of SMMU devices */
>>>>> +    struct list_head                devices;
>>>>>   };
>>>>>   +/* Xen: Keep a list of devices associated with this driver */
>>>>> +static DEFINE_SPINLOCK(arm_smmu_devices_lock);
>>>>> +static LIST_HEAD(arm_smmu_devices);
>>>>> +/* Xen: Helper for finding a device using fwnode */
>>>>> +static
>>>>> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode);
>>>>> +
>>>>> +
>>>>>   /* SMMU private data for each master */
>>>>>   struct arm_smmu_master_data {
>>>>>       struct arm_smmu_device        *smmu;
>>>>> @@ -1232,7 +1634,7 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)
>>>>>         dev_info(smmu->dev, "unexpected PRI request received:\n");
>>>>>       dev_info(smmu->dev,
>>>>> -         "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n",
>>>>> +         "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova %#" PRIx64 "\n",
>>>>>            sid, ssid, grpid, last ? "L" : "",
>>>>>            evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",
>>>>>            evt[0] & PRIQ_0_PERM_READ ? "R" : "",
>>>>> @@ -1346,6 +1748,8 @@ static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev)
>>>>>   {
>>>>>       arm_smmu_gerror_handler(irq, dev);
>>>>>       arm_smmu_cmdq_sync_handler(irq, dev);
>>>>> +    /*Xen: No threaded irq. So call the required function from here */
>>>>> +    arm_smmu_combined_irq_thread(irq, dev);
>>>>>       return IRQ_WAKE_THREAD;
>>>>>   }
>>>>>   @@ -1358,6 +1762,46 @@ static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
>>>>>       arm_smmu_cmdq_issue_cmd(smmu, &cmd);
>>>>>   }
>>>>>   +/*
>>>>> + * Xen: Define the IRQ handlers for xen. The linux functions would be
>>>>> + * modified to use the functions defined in the following code.
>>>>> + */
>>>>> +static void arm_smmu_evtq_thread_xen(int irq, void *dev,
>>>>> +                       struct cpu_user_regs *regs)
>>>>> +{
>>>>> +    arm_smmu_evtq_thread(irq, dev);
>>>>> +}
>>>>> +
>>>>> +static void arm_smmu_priq_thread_xen(int irq, void *dev,
>>>>> +                       struct cpu_user_regs *regs)
>>>>> +{
>>>>> +    arm_smmu_priq_thread(irq, dev);
>>>>> +}
>>>>> +
>>>>> +static void arm_smmu_cmdq_sync_handler_xen(int irq, void *dev,
>>>>> +                       struct cpu_user_regs *regs)
>>>>> +{
>>>>> +    arm_smmu_cmdq_sync_handler(irq, dev);
>>>>> +}
>>>>> +
>>>>> +static void arm_smmu_gerror_handler_xen(int irq, void *dev,
>>>>> +                       struct cpu_user_regs *regs)
>>>>> +{
>>>>> +    arm_smmu_gerror_handler(irq, dev);
>>>>> +}
>>>>> +
>>>>> +static void arm_smmu_combined_irq_handler_xen(int irq, void *dev,
>>>>> +                       struct cpu_user_regs *regs)
>>>>> +{
>>>>> +    arm_smmu_combined_irq_handler(irq, dev);
>>>>> +}
>>>>> +
>>>>> +#define arm_smmu_evtq_thread arm_smmu_evtq_thread_xen
>>>>> +#define arm_smmu_priq_thread arm_smmu_priq_thread_xen
>>>>> +#define arm_smmu_cmdq_sync_handler arm_smmu_cmdq_sync_handler_xen
>>>>> +#define arm_smmu_gerror_handler arm_smmu_gerror_handler_xen
>>>>> +#define arm_smmu_combined_irq_handler arm_smmu_combined_irq_handler_xen
>>>>> +
>>>>>   static void arm_smmu_tlb_sync(void *cookie)
>>>>>   {
>>>>>       struct arm_smmu_domain *smmu_domain = cookie;
>>>>> @@ -1415,6 +1859,7 @@ static const struct iommu_gather_ops arm_smmu_gather_ops = {
>>>>>       .tlb_sync    = arm_smmu_tlb_sync,
>>>>>   };
>>>>>   +#if 0 /*Xen: Unused functionality */
>>>>>   /* IOMMU API */
>>>>>   static bool arm_smmu_capable(enum iommu_cap cap)
>>>>>   {
>>>>> @@ -1427,6 +1872,7 @@ static bool arm_smmu_capable(enum iommu_cap cap)
>>>>>           return false;
>>>>>       }
>>>>>   }
>>>>> +#endif
>>>>>     static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
>>>>>   {
>>>>> @@ -1546,9 +1992,16 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain,
>>>>>       if (vmid < 0)
>>>>>           return vmid;
>>>>>   -    cfg->vmid    = (u16)vmid;
>>>>> -    cfg->vttbr    = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
>>>>> -    cfg->vtcr    = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
>>>>> +    /*
>>>>> +     * Xen: Get the ttbr and vtcr values
>>>>> +     * vttbr: This is a shared value with the domain page table
>>>>> +     * vtcr: The TCR settings are the same as CPU since the page
>>>>> +     * tables are shared
>>>>> +     */
>>>>> +
>>>>> +    cfg->vmid    = vmid;
>>>>> +    cfg->vttbr    = page_to_maddr(cfg->domain->arch.p2m.root);
>>>>> +    cfg->vtcr    = READ_SYSREG32(VTCR_EL2) & STRTAB_STE_2_VTCR_MASK;
>>>>>       return 0;
>>>>>   }
>>>>>   @@ -1604,6 +2057,7 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain)
>>>>>       if (smmu->features & ARM_SMMU_FEAT_COHERENCY)
>>>>>           pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_NO_DMA;
>>>>>   +    /* Xen: pgtbl_ops gets an invalid address */
>>>>>       pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
>>>>>       if (!pgtbl_ops)
>>>>>           return -ENOMEM;
>>>> Will this not fail ?
>>>>> @@ -1721,6 +2175,7 @@ out_unlock:
>>>>>       return ret;
>>>>>   }
>>>>>   +#if 0 /* Xen: Unused functionality */
>>>>>   static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
>>>>>               phys_addr_t paddr, size_t size, int prot)
>>>>>   {
>>>>> @@ -1772,6 +2227,7 @@ struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
>>>>>       put_device(dev);
>>>>>       return dev ? dev_get_drvdata(dev) : NULL;
>>>>>   }
>>>>> +#endif
>>>>>     static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
>>>>>   {
>>>>> @@ -1783,7 +2239,14 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
>>>>>       return sid < limit;
>>>>>   }
>>>>>   +/* Xen: Unused */
>>>>> +#if 0
>>>>>   static struct iommu_ops arm_smmu_ops;
>>>>> +#endif
>>>>> +
>>>>> +/* Xen: Redefine arm_smmu_ops to what fwspec should evaluate */
>>>>> +static const struct iommu_ops arm_smmu_iommu_ops;
>>>>> +#define arm_smmu_ops arm_smmu_iommu_ops
>>>>>     static int arm_smmu_add_device(struct device *dev)
>>>>>   {
>>>>> @@ -1791,8 +2254,11 @@ static int arm_smmu_add_device(struct device *dev)
>>>>>       struct arm_smmu_device *smmu;
>>>>>       struct arm_smmu_master_data *master;
>>>>>       struct iommu_fwspec *fwspec = dev->iommu_fwspec;
>>>>> +#if 0 /*Xen: iommu_group is not needed */
>>>>>       struct iommu_group *group;
>>>>> +#endif
>>>>>   +    /* Xen: fwspec->ops are not needed */
>>>>>       if (!fwspec || fwspec->ops != &arm_smmu_ops)
>>>>>           return -ENODEV;
>>>>>       /*
>>>>> @@ -1830,6 +2296,11 @@ static int arm_smmu_add_device(struct device *dev)
>>>>>           }
>>>>>       }
>>>>>   +/*
>>>>> + * Xen: Do not need an iommu group as the stream data is carried by the SMMU
>>>>> + * master device object
>>>>> + */
>>>>> +#if 0
>>>>>       group = iommu_group_get_for_dev(dev);
>>>>>       if (!IS_ERR(group)) {
>>>>>           iommu_group_put(group);
>>>>> @@ -1837,8 +2308,16 @@ static int arm_smmu_add_device(struct device *dev)
>>>>>       }
>>>>>         return PTR_ERR_OR_ZERO(group);
>>>>> +#endif
>>>>> +    return 0;
>>>>>   }
>>>>>   +/*
>>>>> + * Xen: We can potentially support this function and destroy a device. This
>>>>> + * will be relevant for PCI hotplug. So, will be implemented as needed after
>>>>> + * passthrough support is available.
>>>>> + */
>>>>> +#if 0
>>>>>   static void arm_smmu_remove_device(struct device *dev)
>>>>>   {
>>>>>       struct iommu_fwspec *fwspec = dev->iommu_fwspec;
>>>>> @@ -1974,6 +2453,7 @@ static struct iommu_ops arm_smmu_ops = {
>>>>>       .put_resv_regions    = arm_smmu_put_resv_regions,
>>>>>       .pgsize_bitmap        = -1UL, /* Restricted during device attach */
>>>>>   };
>>>>> +#endif
>>>>>     /* Probing and initialisation functions */
>>>>>   static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
>>>>> @@ -2182,6 +2662,7 @@ static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr)
>>>>>                         1, ARM_SMMU_POLL_TIMEOUT_US);
>>>>>   }
>>>>>   +#if 0 /* Xen: There is no MSI support as yet */
>>>>>   static void arm_smmu_free_msis(void *data)
>>>>>   {
>>>>>       struct device *dev = data;
>>>>> @@ -2247,12 +2728,15 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
>>>>>       /* Add callback to free MSIs on teardown */
>>>>>       devm_add_action(dev, arm_smmu_free_msis, dev);
>>>>>   }
>>>>> +#endif
>>>>>     static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
>>>>>   {
>>>>>       int irq, ret;
>>>>>   +#if 0 /*Xen: Cannot setup msis for now */
>>>>>       arm_smmu_setup_msis(smmu);
>>>>> +#endif
>>>>>         /* Request interrupt lines */
>>>>>       irq = smmu->evtq.q.irq;
>>>>> @@ -2316,9 +2800,13 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
>>>>>            * Cavium ThunderX2 implementation doesn't not support unique
>>>>>            * irq lines. Use single irq line for all the SMMUv3 interrupts.
>>>>>            */
>>>>> -        ret = devm_request_threaded_irq(smmu->dev, irq,
>>>>> +        /*
>>>>> +         * Xen: Does not support threaded irqs, so serialise the setup.
>>>>> +         * This is the same for pris and event interrupt lines on other
>>>>> +         * systems
>>>>> +         */
>>>>> +        ret = devm_request_irq(smmu->dev, irq,
>>>>>                       arm_smmu_combined_irq_handler,
>>>>> -                    arm_smmu_combined_irq_thread,
>>>>>                       IRQF_ONESHOT,
>>>>>                       "arm-smmu-v3-combined-irq", smmu);
>>>>>           if (ret < 0)
>>>>> @@ -2542,8 +3030,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
>>>>>           smmu->features |= ARM_SMMU_FEAT_STALLS;
>>>>>       }
>>>>>   +/*
>>>>> + * Xen: Block stage 1 translations. By doing this here we do not need to set the
>>>>> + * domain->stage explicitly.
>>>>> + */
>>>>> +#if 0
>>>>>       if (reg & IDR0_S1P)
>>>>>           smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
>>>>> +#endif
>>>>>         if (reg & IDR0_S2P)
>>>>>           smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
>>>>> @@ -2616,10 +3110,12 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
>>>>>       if (reg & IDR5_GRAN4K)
>>>>>           smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
>>>>>   +#if 0 /* Xen: SMMU ops do not have a pgsize_bitmap member for Xen */
>>>>>       if (arm_smmu_ops.pgsize_bitmap == -1UL)
>>>>>           arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
>>>>>       else
>>>>>           arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
>>>>> +#endif
>>>>>         /* Output address size */
>>>>>       switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) {
>>>>> @@ -2680,7 +3176,8 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
>>>>>       struct device *dev = smmu->dev;
>>>>>       struct acpi_iort_node *node;
>>>>>   -    node = *(struct acpi_iort_node **)dev_get_platdata(dev);
>>>>> +    /* Xen: Modification to get iort_node */
>>>>> +    node = (struct acpi_iort_node *)dev->acpi_node;
>>>>>         /* Retrieve SMMUv3 specific data */
>>>>>       iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>>>>> @@ -2703,7 +3200,7 @@ static inline int arm_smmu_device_acpi_probe(struct platform_device *pdev,
>>>>>   static int arm_smmu_device_dt_probe(struct platform_device *pdev,
>>>>>                       struct arm_smmu_device *smmu)
>>>>>   {
>>>>> -    struct device *dev = &pdev->dev;
>>>>> +    struct device *dev = pdev;
>>>>>       u32 cells;
>>>>>       int ret = -EINVAL;
>>>>>   @@ -2716,6 +3213,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev,
>>>>>         parse_driver_options(smmu);
>>>>>   +    /* Xen: of_dma_is_coherent is a stub till dt support is introduced */
>>>>>       if (of_dma_is_coherent(dev->of_node))
>>>>>           smmu->features |= ARM_SMMU_FEAT_COHERENCY;
>>>>>   @@ -2734,9 +3232,11 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>>>>>   {
>>>>>       int irq, ret;
>>>>>       struct resource *res;
>>>>> +#if 0 /*Xen: Do not need to setup sysfs */
>>>>>       resource_size_t ioaddr;
>>>>> +#endif
>>>>>       struct arm_smmu_device *smmu;
>>>>> -    struct device *dev = &pdev->dev;
>>>>> +    struct device *dev = pdev;/* Xen: dev is ignored */
>>>>>       bool bypass;
>>>>>         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
>>>>> @@ -2763,7 +3263,9 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>>>>>           dev_err(dev, "MMIO region too small (%pr)\n", res);
>>>>>           return -EINVAL;
>>>>>       }
>>>>> +#if 0 /*Xen: Do not need to setup sysfs */
>>>>>       ioaddr = res->start;
>>>>> +#endif
>>>>>         smmu->base = devm_ioremap_resource(dev, res);
>>>>>       if (IS_ERR(smmu->base))
>>>>> @@ -2802,13 +3304,18 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>>>>>           return ret;
>>>>>         /* Record our private device structure */
>>>>> +    /* Xen: SMMU is not treated a a platform device*/
>>>>> +#if 0
>>>>>       platform_set_drvdata(pdev, smmu);
>>>>> +#endif
>>>>>         /* Reset the device */
>>>>>       ret = arm_smmu_device_reset(smmu, bypass);
>>>>>       if (ret)
>>>>>           return ret;
>>>>>   +/* Xen: Not creating an IOMMU device list for Xen */
>>>>> +#if 0
>>>>>       /* And we're up. Go go go! */
>>>>>       ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL,
>>>>>                        "smmu3.%pa", &ioaddr);
>>>>> @@ -2844,9 +3351,20 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>>>>>           if (ret)
>>>>>               return ret;
>>>>>       }
>>>>> +#endif
>>>>> +    /*
>>>>> +     * Xen: Keep a list of all probed devices. This will be used to query
>>>>> +     * the smmu devices based on the fwnode.
>>>>> +     */
>>>>> +    INIT_LIST_HEAD(&smmu->devices);
>>>>> +    spin_lock(&arm_smmu_devices_lock);
>>>>> +    list_add(&smmu->devices, &arm_smmu_devices);
>>>>> +    spin_unlock(&arm_smmu_devices_lock);
>>>>>       return 0;
>>>>>   }
>>>>>   +/* Xen: Unused function */
>>>>> +#if 0
>>>>>   static int arm_smmu_device_remove(struct platform_device *pdev)
>>>>>   {
>>>>>       struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
>>>>> @@ -2860,6 +3378,8 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev)
>>>>>   {
>>>>>       arm_smmu_device_remove(pdev);
>>>>>   }
>>>>> +#endif
>>>>> +
>>>>>     static const struct of_device_id arm_smmu_of_match[] = {
>>>>>       { .compatible = "arm,smmu-v3", },
>>>>> @@ -2867,6 +3387,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
>>>>>   };
>>>>>   MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
>>>>>   +#if 0
>>>>>   static struct platform_driver arm_smmu_driver = {
>>>>>       .driver    = {
>>>>>           .name        = "arm-smmu-v3",
>>>>> @@ -2883,3 +3404,316 @@ IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3", NULL);
>>>>>   MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
>>>>>   MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
>>>>>   MODULE_LICENSE("GPL v2");
>>>>> +#endif
>>>>> +
>>>>> +/***** Start of Xen specific code *****/
>>>>> +
>>>>> +static int __must_check arm_smmu_iotlb_flush_all(struct domain *d)
>>>>> +{
>>>>> +    struct arm_smmu_xen_domain *smmu_domain = dom_iommu(d)->arch.priv;
>>>>> +    struct iommu_domain *cfg;
>>>>> +
>>>>> +    spin_lock(&smmu_domain->lock);
>>>>> +    list_for_each_entry(cfg, &smmu_domain->contexts, list) {
>>>>> +        /*
>>>>> +         * Only invalidate the context when SMMU is present.
>>>>> +         * This is because the context initialization is delayed
>>>>> +         * until a master has been added.
>>>>> +         */
>>>>> +        if (unlikely(!ACCESS_ONCE(cfg->priv->smmu)))
>>>>> +            continue;
>>>>> +        arm_smmu_tlb_inv_context(cfg->priv);
>>>>> +    }
>>>>> +    spin_unlock(&smmu_domain->lock);
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +static int __must_check arm_smmu_iotlb_flush(struct domain *d,
>>>>> +                         unsigned long gfn,
>>>>> +                         unsigned int page_count)
>>>>> +{
>>>>> +    return arm_smmu_iotlb_flush_all(d);
>>>>> +}
>>>>> +
>>>>> +static struct iommu_domain *arm_smmu_get_domain(struct domain *d,
>>>>> +                        struct device *dev)
>>>>> +{
>>>>> +    struct iommu_domain *domain;
>>>>> +    struct arm_smmu_xen_domain *xen_domain;
>>>>> +    struct arm_smmu_device *smmu;
>>>>> +    struct arm_smmu_domain *smmu_domain;
>>>>> +
>>>>> +    xen_domain = dom_iommu(d)->arch.priv;
>>>>> +
>>>>> +    smmu = arm_smmu_get_by_fwnode(dev->iommu_fwspec->iommu_fwnode);
>>>>> +    if (!smmu)
>>>>> +        return NULL;
>>>>> +
>>>>> +    /*
>>>>> +     * Loop through the &xen_domain->contexts to locate a context
>>>>> +     * assigned to this SMMU
>>>>> +     */
>>>>> +    list_for_each_entry(domain, &xen_domain->contexts, list) {
>>>>> +        smmu_domain = to_smmu_domain(domain);
>>>>> +        if (smmu_domain->smmu == smmu)
>>>>> +            return domain;
>>>>> +    }
>>>>> +
>>>>> +    return NULL;
>>>>> +}
>>>>> +
>>>>> +static void arm_smmu_destroy_iommu_domain(struct iommu_domain *domain)
>>>>> +{
>>>>> +    list_del(&domain->list);
>>>>> +    arm_smmu_domain_free(domain);
>>>>> +}
>>>>> +
>>>>> +static int arm_smmu_assign_dev(struct domain *d, u8 devfn,
>>>>> +                   struct device *dev, u32 flag)
>>>>> +{
>>>>> +    int ret = 0;
>>>>> +    struct iommu_domain *domain;
>>>>> +    struct arm_smmu_xen_domain *xen_domain;
>>>>> +    struct arm_smmu_domain *arm_smmu;
>>>>> +
>>>>> +    xen_domain = dom_iommu(d)->arch.priv;
>>>>> +
>>>>> +    if (!dev->archdata.iommu) {
>>>>> +        dev->archdata.iommu = xzalloc(struct arm_smmu_xen_device);
>>>>> +        if (!dev->archdata.iommu)
>>>>> +            return -ENOMEM;
>>>>> +    }
>>>>> +
>>>>> +    ret = arm_smmu_add_device(dev);
>>>>> +    if (ret)
>>>>> +        return ret;
>>>>> +
>>>>> +    spin_lock(&xen_domain->lock);
>>>>> +
>>>>> +    /*
>>>>> +     * Check to see if an iommu_domain already exists for this xen domain
>>>>> +     * under the same SMMU
>>>>> +     */
>>>>> +    domain = arm_smmu_get_domain(d, dev);
>>>>> +    if (!domain) {
>>>>> +
>>>>> +        domain = arm_smmu_domain_alloc(IOMMU_DOMAIN_DMA);
>>>>> +        if (!domain) {
>>>>> +            ret = -ENOMEM;
>>>>> +            goto out;
>>>>> +        }
>>>>> +
>>>>> +        arm_smmu = to_smmu_domain(domain);
>>>>> +        arm_smmu->s2_cfg.domain = d;
>>>>> +
>>>>> +        /* Chain the new context to the domain */
>>>>> +        list_add(&domain->list, &xen_domain->contexts);
>>>>> +
>>>>> +    }
>>>>> +
>>>>> +    ret = arm_smmu_attach_dev(domain, dev);
>>>>> +    if (ret) {
>>>>> +        if (domain->ref.counter == 0)
>>>>> +            arm_smmu_destroy_iommu_domain(domain);
>>>>> +    } else {
>>>>> +        atomic_inc(&domain->ref);
>>>>> +    }
>>>>> +
>>>>> +out:
>>>>> +    spin_unlock(&xen_domain->lock);
>>>>> +    return ret;
>>>>> +}
>>>>> +
>>>>> +static int arm_smmu_deassign_dev(struct domain *d, struct device *dev)
>>>>> +{
>>>>> +    struct iommu_domain *domain = arm_smmu_get_domain(d, dev);
>>>>> +    struct arm_smmu_xen_domain *xen_domain;
>>>>> +    struct arm_smmu_domain *arm_smmu = to_smmu_domain(domain);
>>>>> +
>>>>> +    xen_domain = dom_iommu(d)->arch.priv;
>>>>> +
>>>>> +    if (!arm_smmu || arm_smmu->s2_cfg.domain != d) {
>>>>> +        dev_err(dev, " not attached to domain %d\n", d->domain_id);
>>>>> +        return -ESRCH;
>>>>> +    }
>>>>> +
>>>>> +    spin_lock(&xen_domain->lock);
>>>>> +
>>>>> +    arm_smmu_detach_dev(dev);
>>>>> +    atomic_dec(&domain->ref);
>>>>> +
>>>>> +    if (domain->ref.counter == 0)
>>>>> +        arm_smmu_destroy_iommu_domain(domain);
>>>>> +
>>>>> +    spin_unlock(&xen_domain->lock);
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +static int arm_smmu_reassign_dev(struct domain *s, struct domain *t,
>>>>> +                 u8 devfn,  struct device *dev)
>>>>> +{
>>>>> +    int ret = 0;
>>>>> +
>>>>> +    /* Don't allow remapping on other domain than hwdom */
>>>>> +    if (t && t != hardware_domain)
>>>>> +        return -EPERM;
>>>>> +
>>>>> +    if (t == s)
>>>>> +        return 0;
>>>>> +
>>>>> +    ret = arm_smmu_deassign_dev(s, dev);
>>>>> +    if (ret)
>>>>> +        return ret;
>>>>> +
>>>>> +    if (t) {
>>>>> +        /* No flags are defined for ARM. */
>>>>> +        ret = arm_smmu_assign_dev(t, devfn, dev, 0);
>>>>> +        if (ret)
>>>>> +            return ret;
>>>>> +    }
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +static int arm_smmu_iommu_domain_init(struct domain *d)
>>>>> +{
>>>>> +    struct arm_smmu_xen_domain *xen_domain;
>>>>> +
>>>>> +    xen_domain = xzalloc(struct arm_smmu_xen_domain);
>>>>> +    if (!xen_domain)
>>>>> +        return -ENOMEM;
>>>>> +
>>>>> +    spin_lock_init(&xen_domain->lock);
>>>>> +    INIT_LIST_HEAD(&xen_domain->contexts);
>>>>> +
>>>>> +    dom_iommu(d)->arch.priv = xen_domain;
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +static void __hwdom_init arm_smmu_iommu_hwdom_init(struct domain *d)
>>>>> +{
>>>>> +}
>>>>> +
>>>>> +static void arm_smmu_iommu_domain_teardown(struct domain *d)
>>>>> +{
>>>>> +    struct arm_smmu_xen_domain *xen_domain = dom_iommu(d)->arch.priv;
>>>>> +
>>>>> +    ASSERT(list_empty(&xen_domain->contexts));
>>>>> +    xfree(xen_domain);
>>>>> +}
>>>>> +
>>>>> +static int __must_check arm_smmu_map_page(struct domain *d, unsigned long gfn,
>>>>> +            unsigned long mfn, unsigned int flags)
>>>>> +{
>>>>> +    p2m_type_t t;
>>>>> +
>>>>> +    /*
>>>>> +     * Grant mappings can be used for DMA requests. The dev_bus_addr
>>>>> +     * returned by the hypercall is the MFN (not the IPA). For device
>>>>> +     * protected by an IOMMU, Xen needs to add a 1:1 mapping in the domain
>>>>> +     * p2m to allow DMA request to work.
>>>>> +     * This is only valid when the domain is directed mapped. Hence this
>>>>> +     * function should only be used by gnttab code with gfn == mfn.
>>>>> +     */
>>>>> +    BUG_ON(!is_domain_direct_mapped(d));
>>>>> +    BUG_ON(mfn != gfn);
>>>>> +
>>>>> +    /* We only support readable and writable flags */
>>>>> +    if (!(flags & (IOMMUF_readable | IOMMUF_writable)))
>>>>> +        return -EINVAL;
>>>>> +
>>>>> +    t = (flags & IOMMUF_writable) ? p2m_iommu_map_rw : p2m_iommu_map_ro;
>>>>> +
>>>>> +    /*
>>>>> +     * The function guest_physmap_add_entry replaces the current mapping
>>>>> +     * if there is already one...
>>>>> +     */
>>>>> +    return guest_physmap_add_entry(d, _gfn(gfn), _mfn(mfn), 0, t);
>>>>> +}
>>>>> +
>>>>> +static int __must_check arm_smmu_unmap_page(struct domain *d, unsigned long gfn)
>>>>> +{
>>>>> +    /*
>>>>> +     * This function should only be used by gnttab code when the domain
>>>>> +     * is direct mapped
>>>>> +     */
>>>>> +    if (!is_domain_direct_mapped(d))
>>>>> +        return -EINVAL;
>>>>> +
>>>>> +    return guest_physmap_remove_page(d, _gfn(gfn), _mfn(gfn), 0);
>>>>> +}
>>>>> +
>>>>> +static const struct iommu_ops arm_smmu_iommu_ops = {
>>>>> +    .init = arm_smmu_iommu_domain_init,
>>>>> +    .hwdom_init = arm_smmu_iommu_hwdom_init,
>>>>> +    .teardown = arm_smmu_iommu_domain_teardown,
>>>>> +    .iotlb_flush = arm_smmu_iotlb_flush,
>>>>> +    .iotlb_flush_all = arm_smmu_iotlb_flush_all,
>>>>> +    .assign_device = arm_smmu_assign_dev,
>>>>> +    .reassign_device = arm_smmu_reassign_dev,
>>>>> +    .map_page = arm_smmu_map_page,
>>>>> +    .unmap_page = arm_smmu_unmap_page,
>>>>> +};
>>>>> +
>>>>> +static
>>>>> +struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
>>>>> +{
>>>>> +    struct arm_smmu_device *smmu = NULL;
>>>>> +
>>>>> +    spin_lock(&arm_smmu_devices_lock);
>>>>> +    list_for_each_entry(smmu, &arm_smmu_devices, devices) {
>>>>> +        if (smmu->dev->fwnode == fwnode)
>>>>> +            break;
>>>>> +    }
>>>>> +    spin_unlock(&arm_smmu_devices_lock);
>>>>> +
>>>>> +    return smmu;
>>>>> +}
>>>>> +
>>>>> +static __init int arm_smmu_dt_init(struct dt_device_node *dev,
>>>>> +                   const void *data)
>>>>> +{
>>>>> +    int rc;
>>>>> +
>>>>> +    /*
>>>>> +     * Even if the device can't be initialized, we don't want to
>>>>> +     * give the SMMU device to dom0.
>>>>> +     */
>>>>> +    dt_device_set_used_by(dev, DOMID_XEN);
>>>>> +
>>>>> +    rc = arm_smmu_device_probe(dt_to_dev(dev));
>>>>> +    if (rc)
>>>>> +        return rc;
>>>>> +
>>>>> +    iommu_set_ops(&arm_smmu_iommu_ops);
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +DT_DEVICE_START(smmuv3, "ARM SMMU V3", DEVICE_IOMMU)
>>>>> +    .dt_match = arm_smmu_of_match,
>>>>> +    .init = arm_smmu_dt_init,
>>>>> +DT_DEVICE_END
>>>>> +
>>>>> +#ifdef CONFIG_ACPI
>>>>> +/* Set up the IOMMU */
>>>>> +static int __init arm_smmu_acpi_init(const void *data)
>>>>> +{
>>>>> +    int rc;
>>>>> +
>>>>> +    rc = arm_smmu_device_probe((struct device *)data);
>>>>> +    if (rc)
>>>>> +        return rc;
>>>>> +
>>>>> +    iommu_set_ops(&arm_smmu_iommu_ops);
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +ACPI_DEVICE_START(asmmuv3, "ARM SMMU V3", DEVICE_IOMMU)
>>>>> +    .class_type = ACPI_IORT_NODE_SMMU_V3,
>>>>> +    .init = arm_smmu_acpi_init,
>>>>> +ACPI_DEVICE_END
>>>>> +
>>>>> +#endif
>>>>> diff --git a/xen/include/xen/linux_compat.h b/xen/include/xen/linux_compat.h
>>>>> new file mode 100644
>>>>> index 0000000000..8037be0a3e
>>>>> --- /dev/null
>>>>> +++ b/xen/include/xen/linux_compat.h
>>>>> @@ -0,0 +1,84 @@
>>>>> +/******************************************************************************
>>>>> + * include/xen/linux_compat.h
>>>>> + *
>>>>> + * Compatibility defines for porting code from Linux to Xen
>>>>> + *
>>>>> + * Copyright (c) 2017 Linaro Limited
>>>>> + *
>>>>> + * This program is free software; you can redistribute it and/or modify
>>>>> + * it under the terms of the GNU General Public License as published by
>>>>> + * the Free Software Foundation; either version 2 of the License, or
>>>>> + * (at your option) any later version.
>>>>> + *
>>>>> + * This program is distributed in the hope that it will be useful,
>>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>>> + * GNU General Public License for more details.
>>>>> + *
>>>>> + * You should have received a copy of the GNU General Public License
>>>>> + * along with this program; If not, see <http://www.gnu.org/licenses/>.
>>>>> + */
>>>>> +
>>>>> +#ifndef __XEN_LINUX_COMPAT_H__
>>>>> +#define __XEN_LINUX_COMPAT_H__
>>>>> +
>>>>> +#include <asm/types.h>
>>>>> +
>>>>> +typedef paddr_t phys_addr_t;
>>>>> +typedef paddr_t dma_addr_t;
>>>>> +
>>>>> +typedef unsigned int gfp_t;
>>>>> +#define GFP_KERNEL 0
>>>>> +#define __GFP_ZERO 0x01U
>>>>> +
>>>>> +/* Helpers for IRQ functions */
>>>>> +#define free_irq release_irq
>>>>> +
>>>>> +enum irqreturn {
>>>>> +    IRQ_NONE,
>>>>> +    IRQ_HANDLED,
>>>>> +    IRQ_WAKE_THREAD,
>>>>> +};
>>>>> +
>>>>> +typedef enum irqreturn irqreturn_t;
>>>>> +
>>>>> +/* Device logger functions */
>>>>> +#define dev_dbg(dev, fmt, ...) printk(XENLOG_DEBUG fmt, ## __VA_ARGS__)
>>>>> +#define dev_notice(dev, fmt, ...) printk(XENLOG_INFO fmt, ## __VA_ARGS__)
>>>>> +#define dev_warn(dev, fmt, ...) printk(XENLOG_WARNING fmt, ## __VA_ARGS__)
>>>>> +#define dev_err(dev, fmt, ...) printk(XENLOG_ERR fmt, ## __VA_ARGS__)
>>>>> +#define dev_info(dev, fmt, ...) printk(XENLOG_INFO fmt, ## __VA_ARGS__)
>>>>> +
>>>>> +#define dev_err_ratelimited(dev, fmt, ...)                  \
>>>>> +     printk(XENLOG_ERR fmt, ## __VA_ARGS__)
>>>>> +
>>>>> +#define dev_name(dev) dt_node_full_name(dev_to_dt(dev))
>>>>> +
>>>>> +/* Alias to Xen allocation helpers */
>>>>> +#define kfree xfree
>>>>> +#define kmalloc(size, flags) ({\
>>>>> +    void *__ret_alloc = NULL; \
>>>>> +    if (flags & __GFP_ZERO) \
>>>>> +        __ret_alloc = _xzalloc(size, sizeof(void *)); \
>>>>> +    else \
>>>>> +        __ret_alloc = _xmalloc(size, sizeof(void *)); \
>>>>> +    __ret_alloc; \
>>>>> +})
>>>>> +#define kzalloc(size, flags)        _xzalloc(size, sizeof(void *))
>>>>> +#define devm_kzalloc(dev, size, flags)  _xzalloc(size, sizeof(void *))
>>>>> +#define kmalloc_array(size, n, flags) ({\
>>>>> +    void *__ret_alloc = NULL; \
>>>>> +    if (flags & __GFP_ZERO) \
>>>>> +        __ret_alloc = _xzalloc_array(size, sizeof(void *), n); \
>>>>> +    else \
>>>>> +        __ret_alloc = _xmalloc_array(size, sizeof(void *), n); \
>>>>> +    __ret_alloc; \
>>>>> +})
>>>>> +
>>>>> +/* Alias to Xen time functions */
>>>>> +#define ktime_t s_time_t
>>>>> +#define ktime_get()             (NOW())
>>>>> +#define ktime_add_us(t,i)       (t + MICROSECS(i))
>>>>> +#define ktime_compare(t,i)      (t > (i))
>>>>> +
>>>>> +#endif /* __XEN_LINUX_COMPAT_H__ */
>>>>
>>>>
>>>> _______________________________________________
>>>> Xen-devel mailing list
>>>> Xen-devel@lists.xenproject.org
>>>> https://lists.xenproject.org/mailman/listinfo/xen-devel
>>>
>>
>>
>> _______________________________________________
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>> Xen-devel@lists.xenproject.org
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