mbox series

[0/9] target/arm: Implement v8.1-Atomics

Message ID 20180427002651.28356-1-richard.henderson@linaro.org
Headers show
Series target/arm: Implement v8.1-Atomics | expand

Message

Richard Henderson April 27, 2018, 12:26 a.m. UTC 
This implements the Atomics extension, which is mandatory for v8.1.
While testing the v8.2-SVE extension, I've run into issues with the
GCC testsuite expecting this to exist.

Missing is the wiring up of the system registers to indicate that
the extension exists, but we have no system CPU model that would
exercise such a setting.


r~


PS: Given the extension is mandatory, it might be better to save
feature bits and file this under ARM_FEATURE_V8_1.  Thoughts?

PPS: Testing for this will proceed overnight.  It takes a while
to run the gcc testsuite and I'm ready to stop for the day.  ;-)


Richard Henderson (9):
  tcg: Introduce helpers for integer min/max
  target/arm: Use new min/max expanders
  target/xtensa: Use new min/max expanders
  tcg: Introduce atomic helpers for integer min/max
  target/riscv: Use new atomic min/max expanders
  target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode
  target/arm: Fill in disas_ldst_atomic
  target/arm: Implement CAS and CASP
  target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only

 accel/tcg/atomic_template.h |  71 +++++++++
 accel/tcg/tcg-runtime.h     |   8 +
 target/arm/cpu.h            |   1 +
 target/arm/helper-a64.h     |   2 +
 tcg/tcg-op.h                |  50 ++++++
 tcg/tcg.h                   |   8 +
 linux-user/elfload.c        |   1 +
 target/arm/cpu64.c          |   1 +
 target/arm/helper-a64.c     |  43 +++++
 target/arm/translate-a64.c  | 375 +++++++++++++++++++++++++++++++++++---------
 target/riscv/translate.c    |  72 +++------
 target/xtensa/translate.c   |  50 ++++--
 tcg/tcg-op.c                |  48 ++++++
 13 files changed, 583 insertions(+), 147 deletions(-)

-- 
2.14.3

Comments

no-reply@patchew.org April 27, 2018, 12:53 a.m. UTC | #1 
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180427002651.28356-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH 0/9] target/arm: Implement v8.1-Atomics

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]            patchew/1524760009-24710-1-git-send-email-babu.moger@amd.com -> patchew/1524760009-24710-1-git-send-email-babu.moger@amd.com
 t [tag update]            patchew/20180426152805.8469-1-armbru@redhat.com -> patchew/20180426152805.8469-1-armbru@redhat.com
 t [tag update]            patchew/20180426183404.3756-1-lersek@redhat.com -> patchew/20180426183404.3756-1-lersek@redhat.com
 * [new tag]               patchew/20180427002651.28356-1-richard.henderson@linaro.org -> patchew/20180427002651.28356-1-richard.henderson@linaro.org
Switched to a new branch 'test'
f1c0eb1e26 target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only
d8978a3761 target/arm: Implement CAS and CASP
2229dd43ab target/arm: Fill in disas_ldst_atomic
0cc7c4a2bd target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode
3df94031fd target/riscv: Use new atomic min/max expanders
9e1cb6782e tcg: Introduce atomic helpers for integer min/max
b2f9e683c8 target/xtensa: Use new min/max expanders
7c552ca2e7 target/arm: Use new min/max expanders
fa99015f7a tcg: Introduce helpers for integer min/max

=== OUTPUT BEGIN ===
Checking PATCH 1/9: tcg: Introduce helpers for integer min/max...
Checking PATCH 2/9: target/arm: Use new min/max expanders...
Checking PATCH 3/9: target/xtensa: Use new min/max expanders...
Checking PATCH 4/9: tcg: Introduce atomic helpers for integer min/max...
ERROR: memory barrier without comment
#55: FILE: accel/tcg/atomic_template.h:137:
+    smp_mb();                                                       \

ERROR: memory barrier without comment
#95: FILE: accel/tcg/atomic_template.h:285:
+    smp_mb();                                                       \

total: 2 errors, 0 warnings, 236 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 5/9: target/riscv: Use new atomic min/max expanders...
Checking PATCH 6/9: target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode...
Checking PATCH 7/9: target/arm: Fill in disas_ldst_atomic...
Checking PATCH 8/9: target/arm: Implement CAS and CASP...
Checking PATCH 9/9: target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com