| Message ID | 20180308170316.3200-1-ard.biesheuvel@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [edk2,edk2-platforms] Silicon/AMD/Styx: add PPTT ACPI table | expand |
On Thu, Mar 08, 2018 at 05:03:16PM +0000, Ard Biesheuvel wrote: > Add a ACPI PPTT table describing the cache topology of the Seattle SoC. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Looks plausible: Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > --- > Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 1 + > Silicon/AMD/Styx/AcpiTables/Pptt.c | 225 ++++++++++++++++++++ > Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h | 1 + > Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 3 +- > 4 files changed, 229 insertions(+), 1 deletion(-) > > diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf > index cfffc73894c0..057c52512e4e 100644 > --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf > +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf > @@ -38,6 +38,7 @@ [Sources] > Csrt.c > Dsdt.c > Iort.c > + Pptt.c > > [Packages] > ArmPkg/ArmPkg.dec > diff --git a/Silicon/AMD/Styx/AcpiTables/Pptt.c b/Silicon/AMD/Styx/AcpiTables/Pptt.c > new file mode 100644 > index 000000000000..d9d7c494d86f > --- /dev/null > +++ b/Silicon/AMD/Styx/AcpiTables/Pptt.c > @@ -0,0 +1,225 @@ > +/** @file > + > + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> > + > + This program and the accompanying materials are licensed and made available > + under the terms and conditions of the BSD License which accompanies this > + distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#include <IndustryStandard/Acpi.h> > + > +#include <AmdStyxAcpiLib.h> > + > +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) > + > +#pragma pack(1) > +typedef struct { > + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; > + UINT32 Offset[2]; > + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; > + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; > +} STYX_PPTT_CORE; > + > +typedef struct { > + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; > + UINT32 Offset[1]; > + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; > + STYX_PPTT_CORE Cores[2]; > +} STYX_PPTT_CLUSTER; > + > +typedef struct { > + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; > + UINT32 Offset[1]; > + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; > + STYX_PPTT_CLUSTER Clusters[NUM_CORES / 2]; > +} STYX_PPTT_PACKAGE; > + > +typedef struct { > + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; > + STYX_PPTT_PACKAGE Packages[1]; > +} STYX_PPTT_TABLE; > +#pragma pack() > + > +#define PPTT_CORE(pid, cid, id) { \ > + { \ > + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ > + FIELD_OFFSET (STYX_PPTT_CORE, DCache), \ > + {}, \ > + { \ > + 0, /* PhysicalPackage */ \ > + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ > + }, \ > + FIELD_OFFSET (STYX_PPTT_TABLE, \ > + Packages[pid].Clusters[cid]), /* Parent */ \ > + ((cid) << 8) + (id), /* AcpiProcessorId */ \ > + 2, /* NumberOfPrivateResources */\ > + }, { \ > + FIELD_OFFSET (STYX_PPTT_TABLE, \ > + Packages[pid].Clusters[cid].Cores[id].DCache), \ > + FIELD_OFFSET (STYX_PPTT_TABLE, \ > + Packages[pid].Clusters[cid].Cores[id].ICache), \ > + }, { \ > + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ > + {}, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 0, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 1, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + SIZE_32KB, /* Size */ \ > + 256, /* NumberOfSets */ \ > + 2, /* Associativity */ \ > + { \ > + 0, /* AllocationType */ \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ > + }, \ > + 64 /* LineSize */ \ > + }, { \ > + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ > + {}, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 0, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 1, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + 3 * SIZE_16KB,/* Size */ \ > + 256, /* NumberOfSets */ \ > + 3, /* Associativity */ \ > + { \ > + 0, /* AllocationType */ \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ > + }, \ > + 64 /* LineSize */ \ > + } \ > +} > + > +#define PPTT_CLUSTER(pid, cid) { \ > + { \ > + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ > + FIELD_OFFSET (STYX_PPTT_CLUSTER, L2Cache), \ > + {}, \ > + { \ > + 0, /* PhysicalPackage */ \ > + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ > + }, \ > + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid]), /* Parent */ \ > + 0, /* AcpiProcessorId */ \ > + 1, /* NumberOfPrivateResources */ \ > + }, { \ > + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \ > + }, { \ > + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ > + {}, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 0, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 1, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + SIZE_1MB, /* Size */ \ > + 1024, /* NumberOfSets */ \ > + 16, /* Associativity */ \ > + { \ > + 0, /* AllocationType */ \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ > + }, \ > + 64 /* LineSize */ \ > + }, { \ > + PPTT_CORE(pid, cid, 0), \ > + PPTT_CORE(pid, cid, 1), \ > + } \ > +} > + > +STATIC STYX_PPTT_TABLE mSynQuacerPpttTable = { > + { > + AMD_ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, > + STYX_PPTT_TABLE, > + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), > + }, > + { > + { > + { > + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, > + FIELD_OFFSET (STYX_PPTT_PACKAGE, L3Cache), > + {}, > + { > + 1, /* PhysicalPackage */ > + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ > + }, > + 0, /* Parent */ > + 0, /* AcpiProcessorId */ > + 1, /* NumberOfPrivateResources */ > + }, { > + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[0].L3Cache), > + }, { > + EFI_ACPI_6_2_PPTT_TYPE_CACHE, > + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), > + {}, > + { > + 1, /* SizePropertyValid */ > + 1, /* NumberOfSetsValid */ > + 1, /* AssociativityValid */ > + 0, /* AllocationTypeValid */ > + 1, /* CacheTypeValid */ > + 1, /* WritePolicyValid */ > + 1, /* LineSizeValid */ > + }, > + 0, /* NextLevelOfCache */ > + SIZE_8MB, /* Size */ > + 8192, /* NumberOfSets */ > + 16, /* Associativity */ > + { > + 0, /* AllocationType */ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, > + }, > + 64 /* LineSize */ > + }, { > + PPTT_CLUSTER (0, 0), > +#if NUM_CORES > 3 > + PPTT_CLUSTER (0, 1), > +#if NUM_CORES > 5 > + PPTT_CLUSTER (0, 2), > +#if NUM_CORES > 7 > + PPTT_CLUSTER (0, 3), > +#endif > +#endif > +#endif > + } > + } > + } > +}; > + > +EFI_ACPI_DESCRIPTION_HEADER * > +PpttHeader ( > + VOID > + ) > +{ > + return (EFI_ACPI_DESCRIPTION_HEADER *)&mSynQuacerPpttTable.Pptt.Header; > +} > diff --git a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h > index 9438b8b0c27e..58e160b6d727 100644 > --- a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h > +++ b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h > @@ -28,6 +28,7 @@ EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void); > EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void); > EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void); > EFI_ACPI_DESCRIPTION_HEADER *IortHeader (void); > +EFI_ACPI_DESCRIPTION_HEADER *PpttHeader (void); > > #define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'} > #define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ') > diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c > index 15b38bbf89c6..901eac105932 100644 > --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c > +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c > @@ -27,7 +27,7 @@ > #include <Library/PcdLib.h> > #include <Library/UefiBootServicesTableLib.h> > > -#define MAX_ACPI_TABLES 12 > +#define MAX_ACPI_TABLES 16 > > EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES]; > > @@ -69,6 +69,7 @@ AcpiPlatformEntryPoint ( > if (PcdGetBool (PcdEnableSmmus)) { > AcpiTableList[TableIndex++] = IortHeader(); > } > + AcpiTableList[TableIndex++] = PpttHeader(); > AcpiTableList[TableIndex++] = NULL; > > DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__)); > -- > 2.15.1 > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
On 15 March 2018 at 20:07, Leif Lindholm <leif.lindholm@linaro.org> wrote: > On Thu, Mar 08, 2018 at 05:03:16PM +0000, Ard Biesheuvel wrote: >> Add a ACPI PPTT table describing the cache topology of the Seattle SoC. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > > Looks plausible: > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > Pushed as 6d6591a29e52 Thanks >> --- >> Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 1 + >> Silicon/AMD/Styx/AcpiTables/Pptt.c | 225 ++++++++++++++++++++ >> Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h | 1 + >> Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 3 +- >> 4 files changed, 229 insertions(+), 1 deletion(-) >> >> diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf >> index cfffc73894c0..057c52512e4e 100644 >> --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf >> +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf >> @@ -38,6 +38,7 @@ [Sources] >> Csrt.c >> Dsdt.c >> Iort.c >> + Pptt.c >> >> [Packages] >> ArmPkg/ArmPkg.dec >> diff --git a/Silicon/AMD/Styx/AcpiTables/Pptt.c b/Silicon/AMD/Styx/AcpiTables/Pptt.c >> new file mode 100644 >> index 000000000000..d9d7c494d86f >> --- /dev/null >> +++ b/Silicon/AMD/Styx/AcpiTables/Pptt.c >> @@ -0,0 +1,225 @@ >> +/** @file >> + >> + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> >> + >> + This program and the accompanying materials are licensed and made available >> + under the terms and conditions of the BSD License which accompanies this >> + distribution. The full text of the license may be found at >> + http://opensource.org/licenses/bsd-license.php >> + >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. >> + >> +**/ >> + >> +#include <IndustryStandard/Acpi.h> >> + >> +#include <AmdStyxAcpiLib.h> >> + >> +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) >> + >> +#pragma pack(1) >> +typedef struct { >> + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; >> + UINT32 Offset[2]; >> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; >> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; >> +} STYX_PPTT_CORE; >> + >> +typedef struct { >> + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; >> + UINT32 Offset[1]; >> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; >> + STYX_PPTT_CORE Cores[2]; >> +} STYX_PPTT_CLUSTER; >> + >> +typedef struct { >> + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; >> + UINT32 Offset[1]; >> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; >> + STYX_PPTT_CLUSTER Clusters[NUM_CORES / 2]; >> +} STYX_PPTT_PACKAGE; >> + >> +typedef struct { >> + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; >> + STYX_PPTT_PACKAGE Packages[1]; >> +} STYX_PPTT_TABLE; >> +#pragma pack() >> + >> +#define PPTT_CORE(pid, cid, id) { \ >> + { \ >> + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ >> + FIELD_OFFSET (STYX_PPTT_CORE, DCache), \ >> + {}, \ >> + { \ >> + 0, /* PhysicalPackage */ \ >> + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ >> + }, \ >> + FIELD_OFFSET (STYX_PPTT_TABLE, \ >> + Packages[pid].Clusters[cid]), /* Parent */ \ >> + ((cid) << 8) + (id), /* AcpiProcessorId */ \ >> + 2, /* NumberOfPrivateResources */\ >> + }, { \ >> + FIELD_OFFSET (STYX_PPTT_TABLE, \ >> + Packages[pid].Clusters[cid].Cores[id].DCache), \ >> + FIELD_OFFSET (STYX_PPTT_TABLE, \ >> + Packages[pid].Clusters[cid].Cores[id].ICache), \ >> + }, { \ >> + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ >> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ >> + {}, \ >> + { \ >> + 1, /* SizePropertyValid */ \ >> + 1, /* NumberOfSetsValid */ \ >> + 1, /* AssociativityValid */ \ >> + 0, /* AllocationTypeValid */ \ >> + 1, /* CacheTypeValid */ \ >> + 1, /* WritePolicyValid */ \ >> + 1, /* LineSizeValid */ \ >> + }, \ >> + 0, /* NextLevelOfCache */ \ >> + SIZE_32KB, /* Size */ \ >> + 256, /* NumberOfSets */ \ >> + 2, /* Associativity */ \ >> + { \ >> + 0, /* AllocationType */ \ >> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ >> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ >> + }, \ >> + 64 /* LineSize */ \ >> + }, { \ >> + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ >> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ >> + {}, \ >> + { \ >> + 1, /* SizePropertyValid */ \ >> + 1, /* NumberOfSetsValid */ \ >> + 1, /* AssociativityValid */ \ >> + 0, /* AllocationTypeValid */ \ >> + 1, /* CacheTypeValid */ \ >> + 1, /* WritePolicyValid */ \ >> + 1, /* LineSizeValid */ \ >> + }, \ >> + 0, /* NextLevelOfCache */ \ >> + 3 * SIZE_16KB,/* Size */ \ >> + 256, /* NumberOfSets */ \ >> + 3, /* Associativity */ \ >> + { \ >> + 0, /* AllocationType */ \ >> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ >> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ >> + }, \ >> + 64 /* LineSize */ \ >> + } \ >> +} >> + >> +#define PPTT_CLUSTER(pid, cid) { \ >> + { \ >> + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ >> + FIELD_OFFSET (STYX_PPTT_CLUSTER, L2Cache), \ >> + {}, \ >> + { \ >> + 0, /* PhysicalPackage */ \ >> + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ >> + }, \ >> + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid]), /* Parent */ \ >> + 0, /* AcpiProcessorId */ \ >> + 1, /* NumberOfPrivateResources */ \ >> + }, { \ >> + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \ >> + }, { \ >> + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ >> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ >> + {}, \ >> + { \ >> + 1, /* SizePropertyValid */ \ >> + 1, /* NumberOfSetsValid */ \ >> + 1, /* AssociativityValid */ \ >> + 0, /* AllocationTypeValid */ \ >> + 1, /* CacheTypeValid */ \ >> + 1, /* WritePolicyValid */ \ >> + 1, /* LineSizeValid */ \ >> + }, \ >> + 0, /* NextLevelOfCache */ \ >> + SIZE_1MB, /* Size */ \ >> + 1024, /* NumberOfSets */ \ >> + 16, /* Associativity */ \ >> + { \ >> + 0, /* AllocationType */ \ >> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ >> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ >> + }, \ >> + 64 /* LineSize */ \ >> + }, { \ >> + PPTT_CORE(pid, cid, 0), \ >> + PPTT_CORE(pid, cid, 1), \ >> + } \ >> +} >> + >> +STATIC STYX_PPTT_TABLE mSynQuacerPpttTable = { >> + { >> + AMD_ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, >> + STYX_PPTT_TABLE, >> + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), >> + }, >> + { >> + { >> + { >> + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, >> + FIELD_OFFSET (STYX_PPTT_PACKAGE, L3Cache), >> + {}, >> + { >> + 1, /* PhysicalPackage */ >> + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ >> + }, >> + 0, /* Parent */ >> + 0, /* AcpiProcessorId */ >> + 1, /* NumberOfPrivateResources */ >> + }, { >> + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[0].L3Cache), >> + }, { >> + EFI_ACPI_6_2_PPTT_TYPE_CACHE, >> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), >> + {}, >> + { >> + 1, /* SizePropertyValid */ >> + 1, /* NumberOfSetsValid */ >> + 1, /* AssociativityValid */ >> + 0, /* AllocationTypeValid */ >> + 1, /* CacheTypeValid */ >> + 1, /* WritePolicyValid */ >> + 1, /* LineSizeValid */ >> + }, >> + 0, /* NextLevelOfCache */ >> + SIZE_8MB, /* Size */ >> + 8192, /* NumberOfSets */ >> + 16, /* Associativity */ >> + { >> + 0, /* AllocationType */ >> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, >> + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, >> + }, >> + 64 /* LineSize */ >> + }, { >> + PPTT_CLUSTER (0, 0), >> +#if NUM_CORES > 3 >> + PPTT_CLUSTER (0, 1), >> +#if NUM_CORES > 5 >> + PPTT_CLUSTER (0, 2), >> +#if NUM_CORES > 7 >> + PPTT_CLUSTER (0, 3), >> +#endif >> +#endif >> +#endif >> + } >> + } >> + } >> +}; >> + >> +EFI_ACPI_DESCRIPTION_HEADER * >> +PpttHeader ( >> + VOID >> + ) >> +{ >> + return (EFI_ACPI_DESCRIPTION_HEADER *)&mSynQuacerPpttTable.Pptt.Header; >> +} >> diff --git a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h >> index 9438b8b0c27e..58e160b6d727 100644 >> --- a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h >> +++ b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h >> @@ -28,6 +28,7 @@ EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void); >> EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void); >> EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void); >> EFI_ACPI_DESCRIPTION_HEADER *IortHeader (void); >> +EFI_ACPI_DESCRIPTION_HEADER *PpttHeader (void); >> >> #define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'} >> #define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ') >> diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c >> index 15b38bbf89c6..901eac105932 100644 >> --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c >> +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c >> @@ -27,7 +27,7 @@ >> #include <Library/PcdLib.h> >> #include <Library/UefiBootServicesTableLib.h> >> >> -#define MAX_ACPI_TABLES 12 >> +#define MAX_ACPI_TABLES 16 >> >> EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES]; >> >> @@ -69,6 +69,7 @@ AcpiPlatformEntryPoint ( >> if (PcdGetBool (PcdEnableSmmus)) { >> AcpiTableList[TableIndex++] = IortHeader(); >> } >> + AcpiTableList[TableIndex++] = PpttHeader(); >> AcpiTableList[TableIndex++] = NULL; >> >> DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__)); >> -- >> 2.15.1 >> _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf index cfffc73894c0..057c52512e4e 100644 --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf @@ -38,6 +38,7 @@ [Sources] Csrt.c Dsdt.c Iort.c + Pptt.c [Packages] ArmPkg/ArmPkg.dec diff --git a/Silicon/AMD/Styx/AcpiTables/Pptt.c b/Silicon/AMD/Styx/AcpiTables/Pptt.c new file mode 100644 index 000000000000..d9d7c494d86f --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Pptt.c @@ -0,0 +1,225 @@ +/** @file + + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <IndustryStandard/Acpi.h> + +#include <AmdStyxAcpiLib.h> + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} STYX_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + STYX_PPTT_CORE Cores[2]; +} STYX_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + STYX_PPTT_CLUSTER Clusters[NUM_CORES / 2]; +} STYX_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + STYX_PPTT_PACKAGE Packages[1]; +} STYX_PPTT_TABLE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (STYX_PPTT_CORE, DCache), \ + {}, \ + { \ + 0, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ + }, \ + FIELD_OFFSET (STYX_PPTT_TABLE, \ + Packages[pid].Clusters[cid]), /* Parent */ \ + ((cid) << 8) + (id), /* AcpiProcessorId */ \ + 2, /* NumberOfPrivateResources */\ + }, { \ + FIELD_OFFSET (STYX_PPTT_TABLE, \ + Packages[pid].Clusters[cid].Cores[id].DCache), \ + FIELD_OFFSET (STYX_PPTT_TABLE, \ + Packages[pid].Clusters[cid].Cores[id].ICache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_32KB, /* Size */ \ + 256, /* NumberOfSets */ \ + 2, /* Associativity */ \ + { \ + 0, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + 3 * SIZE_16KB,/* Size */ \ + 256, /* NumberOfSets */ \ + 3, /* Associativity */ \ + { \ + 0, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + } \ +} + +#define PPTT_CLUSTER(pid, cid) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (STYX_PPTT_CLUSTER, L2Cache), \ + {}, \ + { \ + 0, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ + }, \ + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid]), /* Parent */ \ + 0, /* AcpiProcessorId */ \ + 1, /* NumberOfPrivateResources */ \ + }, { \ + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_1MB, /* Size */ \ + 1024, /* NumberOfSets */ \ + 16, /* Associativity */ \ + { \ + 0, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + PPTT_CORE(pid, cid, 0), \ + PPTT_CORE(pid, cid, 1), \ + } \ +} + +STATIC STYX_PPTT_TABLE mSynQuacerPpttTable = { + { + AMD_ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + STYX_PPTT_TABLE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), + }, + { + { + { + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, + FIELD_OFFSET (STYX_PPTT_PACKAGE, L3Cache), + {}, + { + 1, /* PhysicalPackage */ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ + }, + 0, /* Parent */ + 0, /* AcpiProcessorId */ + 1, /* NumberOfPrivateResources */ + }, { + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[0].L3Cache), + }, { + EFI_ACPI_6_2_PPTT_TYPE_CACHE, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), + {}, + { + 1, /* SizePropertyValid */ + 1, /* NumberOfSetsValid */ + 1, /* AssociativityValid */ + 0, /* AllocationTypeValid */ + 1, /* CacheTypeValid */ + 1, /* WritePolicyValid */ + 1, /* LineSizeValid */ + }, + 0, /* NextLevelOfCache */ + SIZE_8MB, /* Size */ + 8192, /* NumberOfSets */ + 16, /* Associativity */ + { + 0, /* AllocationType */ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, + }, + 64 /* LineSize */ + }, { + PPTT_CLUSTER (0, 0), +#if NUM_CORES > 3 + PPTT_CLUSTER (0, 1), +#if NUM_CORES > 5 + PPTT_CLUSTER (0, 2), +#if NUM_CORES > 7 + PPTT_CLUSTER (0, 3), +#endif +#endif +#endif + } + } + } +}; + +EFI_ACPI_DESCRIPTION_HEADER * +PpttHeader ( + VOID + ) +{ + return (EFI_ACPI_DESCRIPTION_HEADER *)&mSynQuacerPpttTable.Pptt.Header; +} diff --git a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h index 9438b8b0c27e..58e160b6d727 100644 --- a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h +++ b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h @@ -28,6 +28,7 @@ EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void); EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void); EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void); EFI_ACPI_DESCRIPTION_HEADER *IortHeader (void); +EFI_ACPI_DESCRIPTION_HEADER *PpttHeader (void); #define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'} #define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ') diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 15b38bbf89c6..901eac105932 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -27,7 +27,7 @@ #include <Library/PcdLib.h> #include <Library/UefiBootServicesTableLib.h> -#define MAX_ACPI_TABLES 12 +#define MAX_ACPI_TABLES 16 EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES]; @@ -69,6 +69,7 @@ AcpiPlatformEntryPoint ( if (PcdGetBool (PcdEnableSmmus)) { AcpiTableList[TableIndex++] = IortHeader(); } + AcpiTableList[TableIndex++] = PpttHeader(); AcpiTableList[TableIndex++] = NULL; DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__));
Add a ACPI PPTT table describing the cache topology of the Seattle SoC. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 1 + Silicon/AMD/Styx/AcpiTables/Pptt.c | 225 ++++++++++++++++++++ Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h | 1 + Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 3 +- 4 files changed, 229 insertions(+), 1 deletion(-) -- 2.15.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel