| Message ID | 20180205144651.5934-1-georgi.djakov@linaro.org |
|---|---|
| State | Accepted |
| Commit | d0bf04acd12f5c702ac2b21dca6729a1de1308a7 |
| Headers | show |
| Series | [1/4] arm64: dts: qcom: msm8916: Add msm8916 A53 PLL DT node | expand |
On Mon, Feb 5, 2018 at 8:16 PM, Georgi Djakov <georgi.djakov@linaro.org> wrote: > Add a CPU OPP table to allow CPU frequency scaling on msm8916 platforms. > > Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> For this series, please feel free to add my Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Tested-by: Amit Kucheria <amit.kucheria@linaro.org> It enables basic cpufreq on the DB410c in mainline after enabling QCOM_APCS_IPC. I'll send out another patch to automatically select this Kconfig option. > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 4539571a36b2..e4682779eec7 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -113,6 +113,8 @@ > next-level-cache = <&L2_0>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SPC>; > + clocks = <&apcs 0>; > + operating-points-v2 = <&cpu_opp_table>; > }; > > CPU1: cpu@1 { > @@ -122,6 +124,8 @@ > next-level-cache = <&L2_0>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SPC>; > + clocks = <&apcs 0>; > + operating-points-v2 = <&cpu_opp_table>; > }; > > CPU2: cpu@2 { > @@ -131,6 +135,8 @@ > next-level-cache = <&L2_0>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SPC>; > + clocks = <&apcs 0>; > + operating-points-v2 = <&cpu_opp_table>; > }; > > CPU3: cpu@3 { > @@ -140,6 +146,8 @@ > next-level-cache = <&L2_0>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SPC>; > + clocks = <&apcs 0>; > + operating-points-v2 = <&cpu_opp_table>; > }; > > L2_0: l2-cache { > @@ -212,6 +220,24 @@ > > }; > > + cpu_opp_table: cpu_opp_table { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + }; > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + }; > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + }; > + opp-998400000 { > + opp-hz = /bits/ 64 <998400000>; > + }; > + }; > + > gpu_opp_table: opp_table { > compatible = "operating-points-v2"; > -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e51b04900726..d3592b19cfc9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -326,6 +326,12 @@ status = "disabled"; }; + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + }; + apcs: syscon@b011000 { compatible = "syscon"; reg = <0x0b011000 0x1000>;
Add a device tree node for the A53 PLL, which exists on msm8916 platforms. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html