Message ID | 20180117161435.28981-12-richard.henderson@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | tcg: generic vector operations | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 96316700dd..3ff4dea6b8 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -492,7 +492,7 @@ typedef struct CPUARMState { > * the two execution states, and means we do not need to explicitly > * map these registers when changing states. > */ > - float64 regs[64]; > + float64 regs[64] QEMU_ALIGNED(16); There is a minor conflict that needs to be fixed with the now merged: 3f68b8a5a6862f856524bb347bf348ae364dd43c > > uint32_t xregs[16]; > /* We store these fpcsr fields separately for convenience. */ -- Alex Bennée
On 01/26/2018 01:52 AM, Alex Bennée wrote: > > Richard Henderson <richard.henderson@linaro.org> writes: > >> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> >> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> target/arm/cpu.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/target/arm/cpu.h b/target/arm/cpu.h >> index 96316700dd..3ff4dea6b8 100644 >> --- a/target/arm/cpu.h >> +++ b/target/arm/cpu.h >> @@ -492,7 +492,7 @@ typedef struct CPUARMState { >> * the two execution states, and means we do not need to explicitly >> * map these registers when changing states. >> */ >> - float64 regs[64]; >> + float64 regs[64] QEMU_ALIGNED(16); > > There is a minor conflict that needs to be fixed with the now merged: 3f68b8a5a6862f856524bb347bf348ae364dd43c Already done in v11 which I posted last night. r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 96316700dd..3ff4dea6b8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -492,7 +492,7 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - float64 regs[64]; + float64 regs[64] QEMU_ALIGNED(16); uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */