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+/** @file
+
+ Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/DmaLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NetLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "NetsecDxe.h"
+#include "netsec_for_uefi/pfdep.h"
+
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+STATIC NETSEC_DEVICE_PATH NetsecPathTemplate = {
+ {
+ {
+ MESSAGING_DEVICE_PATH,
+ MSG_MAC_ADDR_DP,
+ {
+ (UINT8)(sizeof (MAC_ADDR_DEVICE_PATH)),
+ (UINT8)(sizeof (MAC_ADDR_DEVICE_PATH) >> 8)
+ }
+ },
+ {
+ {
+ 0
+ }
+ },
+ 0
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ sizeof (EFI_DEVICE_PATH_PROTOCOL), 0
+ }
+ }
+};
+
+STATIC
+VOID
+GetCurrentMacAddress (
+ OUT UINT8 *Mac)
+{
+ Mac[0] = MmioRead8 (MAC_ADDRESS + 3);
+ Mac[1] = MmioRead8 (MAC_ADDRESS + 2);
+ Mac[2] = MmioRead8 (MAC_ADDRESS + 1);
+ Mac[3] = MmioRead8 (MAC_ADDRESS + 0);
+ Mac[4] = MmioRead8 (MAC_ADDRESS + 7);
+ Mac[5] = MmioRead8 (MAC_ADDRESS + 6);
+}
+
+/*
+ * Probe()
+ */
+STATIC
+EFI_STATUS
+Probe (
+ IN EFI_HANDLE Handle,
+ IN NETSEC_DRIVER *LanDriver
+ )
+{
+ ogma_param_t Param;
+ ogma_err_t ogma_err;
+ UINT64 dmac_hm_cmd_base, dmac_mh_cmd_base, core_cmd_base;
+ UINT32 dmac_hm_cmd_size, dmac_mh_cmd_size, core_cmd_size;
+
+ SetMem (&Param, sizeof (Param), 0);
+
+ Param.use_gmac_flag = OGMA_TRUE;
+
+ Param.use_jumbo_pkt_flag = PcdGet8 (PcdJumboPacket);
+
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag = OGMA_TRUE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].little_endian_flag = OGMA_TRUE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].tmr_mode_flag = OGMA_FALSE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].entry_num = PcdGet16 (PcdEncTxDescNum);
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag = OGMA_TRUE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].little_endian_flag = OGMA_TRUE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].tmr_mode_flag = OGMA_FALSE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].entry_num = PcdGet16 (PcdDecRxDescNum);
+
+ // phy-interface
+ Param.gmac_config.phy_interface = OGMA_PHY_INTERFACE_RGMII;
+
+ // Read and save the Permanent MAC Address
+ GetCurrentMacAddress (LanDriver->SnpMode.PermanentAddress.Addr);
+
+ LanDriver->SnpMode.CurrentAddress = LanDriver->SnpMode.PermanentAddress;
+ DEBUG ((DEBUG_NET | DEBUG_INFO,
+ "Netsec: HW MAC Address: %02x-%02x-%02x-%02x-%02x-%02x\n",
+ LanDriver->SnpMode.PermanentAddress.Addr[0],
+ LanDriver->SnpMode.PermanentAddress.Addr[1],
+ LanDriver->SnpMode.PermanentAddress.Addr[2],
+ LanDriver->SnpMode.PermanentAddress.Addr[3],
+ LanDriver->SnpMode.PermanentAddress.Addr[4],
+ LanDriver->SnpMode.PermanentAddress.Addr[5]));
+
+ //
+ // The NETSEC microcode for the core engine and the TX and RX engines
+ // is loaded from a separate memory mapped ROM.
+ //
+
+ // Get hm microcode's physical addresses
+ dmac_hm_cmd_base = MmioRead32 (HM_ME_ADDRESS_H);
+ dmac_hm_cmd_base <<= 32;
+ dmac_hm_cmd_base |= MmioRead32 (HM_ME_ADDRESS_L);
+ dmac_hm_cmd_size = MmioRead32 (HM_ME_SIZE);
+
+ // Get mh microcode's physical addresses
+ dmac_mh_cmd_base = MmioRead32 (MH_ME_ADDRESS_H);
+ dmac_mh_cmd_base <<= 32;
+ dmac_mh_cmd_base |= MmioRead32 (MH_ME_ADDRESS_L);
+ dmac_mh_cmd_size = MmioRead32 (MH_ME_SIZE);
+
+ // Get core microcode's physical addresses
+ core_cmd_base = MmioRead32 (PACKET_ME_ADDRESS);
+ core_cmd_size = MmioRead32 (PACKET_ME_SIZE);
+
+ ogma_err = ogma_init ((VOID *)((UINTN)PcdGet32 (PcdNetsecDxeBaseAddress)),
+ Handle, &Param,
+ (VOID *)dmac_hm_cmd_base, dmac_hm_cmd_size,
+ (VOID *)dmac_mh_cmd_base, dmac_mh_cmd_size,
+ (VOID *)core_cmd_base, core_cmd_size,
+ &LanDriver->Handle);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR, "NETSEC: ogma_init() failed with error code %d\n",
+ ogma_err));
+ return EFI_DEVICE_ERROR;
+ }
+
+ ogma_enable_top_irq (LanDriver->Handle,
+ OGMA_TOP_IRQ_REG_NRM_RX | OGMA_TOP_IRQ_REG_NRM_TX);
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * UEFI Stop() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpStop (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp
+ )
+{
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+
+ // Check Snp Instance
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+ // Check state of the driver
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkStarted:
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Change the state
+ Snp->Mode->State = EfiSimpleNetworkStopped;
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * UEFI Initialize() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpInitialize (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+ IN UINTN RxBufferSize OPTIONAL,
+ IN UINTN TxBufferSize OPTIONAL
+ )
+{
+ NETSEC_DRIVER *LanDriver;
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+
+ ogma_phy_link_status_t phy_link_status;
+ ogma_err_t ogma_err;
+ ogma_gmac_mode_t ogma_gmac_mode;
+
+ // Check Snp Instance
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+ // Check that driver was started but not initialised
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkStarted:
+ break;
+ case EfiSimpleNetworkInitialized:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver already initialized\n"));
+ ReturnUnlock (EFI_SUCCESS);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Find the LanDriver structure
+ LanDriver = INSTANCE_FROM_SNP_THIS (Snp);
+
+ // Clean all descriptors on the RX ring.
+ ogma_err = ogma_clean_rx_desc_ring (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_RX);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_clean_rx_desc_ring() failed with error code %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_clean_tx_desc_ring() failed with error code %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_clear_desc_ring_irq_status (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
+ OGMA_CH_IRQ_REG_EMPTY);
+
+ // Start the RX queue
+ ogma_err = ogma_start_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_start_desc_ring(ring_id=%d) failed with error code %d\n",
+ OGMA_DESC_RING_ID_NRM_RX,
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_set_irq_coalesce_param (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_RX,
+ RXINT_PKTCNT,
+ OGMA_FALSE,
+ RXINT_TMR_CNT_US);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_set_irq_coalesce_param() failed with error code %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_start_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_start_desc_ring(ring_id=%d) failed with error code %d\n",
+ OGMA_DESC_RING_ID_NRM_TX,
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_disable_desc_ring_irq (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
+ OGMA_CH_IRQ_REG_EMPTY);
+
+ // Stop and restart the physical link
+ ogma_err = ogma_stop_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_stop_gmac() failed with error status %d\n",
+ ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_get_phy_link_status (LanDriver->Handle, PcdGet8 (PcdPhyDevAddr), &phy_link_status);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_get_phy_link_status() failed error code %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ SetMem (&ogma_gmac_mode, sizeof (ogma_gmac_mode_t), 0);
+ ogma_gmac_mode.link_speed = phy_link_status.link_speed;
+ ogma_gmac_mode.half_duplex_flag = (ogma_bool)phy_link_status.half_duplex_flag;
+ if ((!phy_link_status.half_duplex_flag) && PcdGet8 (PcdFlowCtrl)) {
+ ogma_gmac_mode.flow_ctrl_enable_flag = (ogma_bool)PcdGet8 (PcdFlowCtrl);
+ ogma_gmac_mode.flow_ctrl_start_threshold = (ogma_uint16)PcdGet16 (PcdFlowCtrlStartThreshold);
+ ogma_gmac_mode.flow_ctrl_stop_threshold = (ogma_uint16)PcdGet16 (PcdFlowCtrlStopThreshold);
+ ogma_gmac_mode.pause_time = (ogma_uint16)PcdGet16 (PcdPauseTime);
+ }
+
+ ogma_err = ogma_set_gmac_mode (LanDriver->Handle, &ogma_gmac_mode);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_set_gmac() failed with error status %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_start_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_start_gmac() failed with error status %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Declare the driver as initialized
+ Snp->Mode->State = EfiSimpleNetworkInitialized;
+ Status = EFI_SUCCESS;
+
+ DEBUG ((DEBUG_INFO | DEBUG_LOAD, "NETSEC: Driver started\n"));
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * UEFI Shutdown () function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpShutdown (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp
+ )
+{
+ NETSEC_DRIVER *LanDriver;
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+
+ // Check Snp Instance
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+ // First check that driver has already been initialized
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStarted:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver in stopped state\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Find the LanDriver structure
+ LanDriver = INSTANCE_FROM_SNP_THIS (Snp);
+
+ ogma_stop_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
+
+ ogma_stop_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX);
+ ogma_stop_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
+
+ Snp->Mode->State = EfiSimpleNetworkStarted;
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+STATIC
+VOID
+EFIAPI
+NotifyExitBoot (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
+ EFI_STATUS Status;
+
+ Snp = Context;
+
+ if (Snp->Mode != EfiSimpleNetworkStopped) {
+ Status = SnpShutdown (Snp);
+ if (!EFI_ERROR (Status)) {
+ SnpStop (Snp);
+ }
+ }
+ gBS->CloseEvent (Event);
+}
+
+/*
+ * UEFI Start() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpStart (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp
+ )
+{
+ EFI_SIMPLE_NETWORK_MODE *Mode;
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+ NETSEC_DRIVER *LanDriver;
+
+ LanDriver = INSTANCE_FROM_SNP_THIS (Snp);
+
+ // Check Snp instance
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ Mode = Snp->Mode;
+
+ // Check state of the driver
+ switch (Mode->State) {
+ case EfiSimpleNetworkStopped:
+ break;
+ case EfiSimpleNetworkStarted:
+ case EfiSimpleNetworkInitialized:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver already started\n"));
+ ReturnUnlock (EFI_ALREADY_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_CALLBACK,
+ NotifyExitBoot, Snp, &LanDriver->ExitBootEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ // Change state
+ Mode->State = EfiSimpleNetworkStarted;
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+
+}
+
+/*
+ * UEFI ReceiveFilters() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpReceiveFilters (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+ IN UINT32 Enable,
+ IN UINT32 Disable,
+ IN BOOLEAN Reset,
+ IN UINTN NumMfilter OPTIONAL,
+ IN EFI_MAC_ADDRESS *Mfilter OPTIONAL
+ )
+{
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+
+ // Check Snp Instance
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+ // First check that driver has already been initialized
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStarted:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n", (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * UEFI GetStatus () function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpGetStatus (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+ OUT UINT32 *IrqStat OPTIONAL,
+ OUT VOID **TxBuff OPTIONAL
+ )
+{
+ NETSEC_DRIVER *LanDriver;
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+ pfdep_pkt_handle_t pkt_handle;
+ LIST_ENTRY *Link;
+
+ ogma_phy_link_status_t phy_link_status;
+ ogma_err_t ogma_err;
+
+ // Check preliminaries
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+ // Check that driver was started and initialised
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStarted:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Find the LanDriver structure
+ LanDriver = INSTANCE_FROM_SNP_THIS (Snp);
+
+ // Update the media status
+ ogma_err = ogma_get_phy_link_status (LanDriver->Handle,
+ PcdGet8 (PcdPhyDevAddr),
+ &phy_link_status);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_get_phy_link_status failed with error code: %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ Snp->Mode->MediaPresent = phy_link_status.up_flag;
+
+ ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX);
+
+ if (TxBuff != NULL) {
+ *TxBuff = NULL;
+ //
+ // Find a buffer in the list that has been released
+ //
+ for (Link = GetFirstNode (&LanDriver->TxBufferList);
+ !IsNull (&LanDriver->TxBufferList, Link);
+ Link = GetNextNode (&LanDriver->TxBufferList, Link)) {
+
+ pkt_handle = BASE_CR (Link, PACKET_HANDLE, Link);
+ if (pkt_handle->Released) {
+ *TxBuff = pkt_handle->Buffer;
+ RemoveEntryList (Link);
+ FreePool (pkt_handle);
+ break;
+ }
+ }
+ }
+
+ if (IrqStat != 0) {
+ *IrqStat = 0;
+ }
+
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * UEFI Transmit() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpTransmit (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+ IN UINTN HdrSize,
+ IN UINTN BufSize,
+ IN VOID *BufAddr,
+ IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
+ IN EFI_MAC_ADDRESS *DstAddr OPTIONAL,
+ IN UINT16 *Protocol OPTIONAL
+ )
+{
+ NETSEC_DRIVER *LanDriver;
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+
+ ogma_tx_pkt_ctrl_t tx_pkt_ctrl;
+ ogma_frag_info_t scat_info;
+ ogma_uint16 tx_avail_num;
+ ogma_err_t ogma_err;
+ UINT16 Proto;
+ pfdep_pkt_handle_t pkt_handle;
+
+ // Check preliminaries
+ if ((Snp == NULL) || (BufAddr == NULL)) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: SnpTransmit(): NULL Snp (%p) or BufAddr (%p)\n", Snp, BufAddr));
+ return EFI_DEVICE_ERROR;
+ }
+
+ pkt_handle = AllocateZeroPool (sizeof (*pkt_handle));
+ if (pkt_handle == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ pkt_handle->Buffer = BufAddr;
+ pkt_handle->RecycleForTx = TRUE;
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+ // Check that driver was started and initialised
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStarted:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Find the LanDriver structure
+ LanDriver = INSTANCE_FROM_SNP_THIS (Snp);
+
+ ogma_err = ogma_clear_desc_ring_irq_status (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX,
+ OGMA_CH_IRQ_REG_EMPTY);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_clear_desc_ring_irq_status failed with error code: %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_clean_tx_desc_ring failed with error code: %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Ensure header is correct size if non-zero
+ if (HdrSize) {
+ if (HdrSize != Snp->Mode->MediaHeaderSize) {
+ DEBUG ((DEBUG_ERROR, "NETSEC: SnpTransmit(): Invalid HdrSize %d\n",
+ HdrSize));
+ ReturnUnlock (EFI_INVALID_PARAMETER);
+ }
+
+ if ((DstAddr == NULL) || (Protocol == NULL)) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: SnpTransmit(): NULL DstAddr %p or Protocol %p\n",
+ DstAddr, Protocol));
+ ReturnUnlock (EFI_INVALID_PARAMETER);
+ }
+
+ // Copy destination address
+ CopyMem (BufAddr, (VOID *)DstAddr, NET_ETHER_ADDR_LEN);
+ // Copy source address
+ CopyMem (BufAddr + NET_ETHER_ADDR_LEN, (VOID *)SrcAddr, NET_ETHER_ADDR_LEN);
+ // Copy protocol
+ Proto = HTONS (*Protocol);
+ CopyMem (BufAddr + (NET_ETHER_ADDR_LEN * 2), (VOID *)&Proto, sizeof (UINT16));
+ }
+
+ Status = DmaMap (MapOperationBusMasterRead, BufAddr, &BufSize,
+ &scat_info.phys_addr, &pkt_handle->Mapping);
+ if (EFI_ERROR (Status)) {
+ goto ExitUnlock;
+ }
+
+ scat_info.addr = BufAddr;
+ scat_info.len = BufSize;
+
+ SetMem (&tx_pkt_ctrl, sizeof (ogma_tx_pkt_ctrl_t), 0);
+
+ tx_pkt_ctrl.pass_through_flag = OGMA_TRUE;
+ tx_pkt_ctrl.target_desc_ring_id = OGMA_DESC_RING_ID_GMAC;
+
+ // check empty slot
+ do {
+ tx_avail_num = ogma_get_tx_avail_num (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX);
+ } while (tx_avail_num < SCAT_NUM);
+
+ // send
+ ogma_err = ogma_set_tx_pkt_data (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX,
+ &tx_pkt_ctrl,
+ SCAT_NUM,
+ &scat_info,
+ pkt_handle);
+
+ if (ogma_err != OGMA_ERR_OK) {
+ DmaUnmap (pkt_handle->Mapping);
+ FreePool (pkt_handle);
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_set_tx_pkt_data failed with error code: %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ //
+ // Queue the descriptor so we can release the buffer once it has been
+ // consumed by the hardware.
+ //
+ InsertTailList (&LanDriver->TxBufferList, &pkt_handle->Link);
+
+ gBS->RestoreTPL (SavedTpl);
+ return EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ FreePool (pkt_handle);
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * UEFI Receive() function
+ */
+EFI_STATUS
+EFIAPI
+SnpReceive (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+ OUT UINTN *HdrSize OPTIONAL,
+ IN OUT UINTN *BuffSize,
+ OUT VOID *Data,
+ OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
+ OUT EFI_MAC_ADDRESS *DstAddr OPTIONAL,
+ OUT UINT16 *Protocol OPTIONAL
+ )
+{
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+ NETSEC_DRIVER *LanDriver;
+
+ ogma_err_t ogma_err;
+ ogma_rx_pkt_info_t rx_pkt_info;
+ ogma_frag_info_t rx_data;
+ ogma_uint16 len;
+ pfdep_pkt_handle_t pkt_handle;
+
+ // Check preliminaries
+ if ((Snp == NULL) || (Data == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+ // Check that driver was started and initialised
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStarted:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Find the LanDriver structure
+ LanDriver = INSTANCE_FROM_SNP_THIS (Snp);
+
+ if (ogma_get_rx_num (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX) > 0) {
+
+ ogma_err = ogma_get_rx_pkt_data (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_RX,
+ &rx_pkt_info, &rx_data, &len, &pkt_handle);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_get_rx_pkt_data failed with error code: %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ DmaUnmap (pkt_handle->Mapping);
+ pkt_handle->Mapping = NULL;
+
+ CopyMem (Data, (VOID*)rx_data.addr, len);
+ *BuffSize = len;
+
+ pfdep_free_pkt_buf (LanDriver->Handle, rx_data.len, rx_data.addr,
+ rx_data.phys_addr, PFDEP_TRUE, pkt_handle);
+ } else {
+ // not received any packets
+ ReturnUnlock (EFI_NOT_READY);
+ }
+
+ if (HdrSize != NULL) {
+ *HdrSize = LanDriver->SnpMode.MediaHeaderSize;
+ }
+
+ ogma_clear_desc_ring_irq_status (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX,
+ OGMA_CH_IRQ_REG_EMPTY);
+
+ ogma_clean_tx_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
+
+ ogma_enable_top_irq (LanDriver->Handle,
+ OGMA_TOP_IRQ_REG_NRM_TX | OGMA_TOP_IRQ_REG_NRM_RX);
+
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * Entry point for the Netxec driver
+ */
+EFI_STATUS
+NetsecDxeEntry (
+ IN EFI_HANDLE Handle,
+ IN EFI_SYSTEM_TABLE *SystemTable)
+{
+ EFI_STATUS Status;
+ NETSEC_DRIVER *LanDriver;
+ EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
+ EFI_SIMPLE_NETWORK_MODE *SnpMode;
+ NETSEC_DEVICE_PATH *NetsecPath;
+
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
+ ASSERT_EFI_ERROR (Status);
+
+ // Allocate Resources
+ LanDriver = AllocateZeroPool (sizeof (NETSEC_DRIVER));
+ NetsecPath = AllocateCopyPool (sizeof (NETSEC_DEVICE_PATH),
+ &NetsecPathTemplate);
+
+ // Initialize pointers
+ Snp = &(LanDriver->Snp);
+ SnpMode = &(LanDriver->SnpMode);
+ Snp->Mode = SnpMode;
+
+ // Set the signature of the LAN Driver structure
+ LanDriver->Signature = NETSEC_SIGNATURE;
+
+ // Probe the device
+ Status = Probe (Handle, LanDriver);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC:NetsecDxeEntry(): Probe failed with status %d\n", Status));
+ return Status;
+ }
+
+ // Assign fields and func pointers
+ Snp->Revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
+ Snp->WaitForPacket = NULL;
+ Snp->Initialize = SnpInitialize;
+ Snp->Start = SnpStart;
+ Snp->Stop = SnpStop;
+ Snp->Reset = NULL;
+ Snp->Shutdown = SnpShutdown;
+ Snp->ReceiveFilters = SnpReceiveFilters;
+ Snp->StationAddress = NULL;
+ Snp->Statistics = NULL;
+ Snp->MCastIpToMac = NULL;
+ Snp->NvData = NULL;
+ Snp->GetStatus = SnpGetStatus;
+ Snp->Transmit = SnpTransmit;
+ Snp->Receive = SnpReceive;
+
+ // Fill in simple network mode structure
+ SnpMode->State = EfiSimpleNetworkStopped;
+ SnpMode->HwAddressSize = NET_ETHER_ADDR_LEN; // HW address is 6 bytes
+ SnpMode->MediaHeaderSize = sizeof (ETHER_HEAD); // Size of an Ethernet header
+ SnpMode->MaxPacketSize = EFI_PAGE_SIZE; // Ethernet Frame (with VLAN tag +4 bytes)
+
+ // Supported receive filters
+ SnpMode->ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
+ EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
+ EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST |
+ EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS |
+ EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
+
+ // Initially-enabled receive filters
+ SnpMode->ReceiveFilterSetting = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
+ EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
+ EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST;
+
+ // Netsec has 64bit hash table. We can filter an infinite MACs, but
+ // higher-level software must filter out any hash collisions.
+ SnpMode->MaxMCastFilterCount = MAX_MCAST_FILTER_CNT;
+ SnpMode->MCastFilterCount = 0;
+ ZeroMem (&SnpMode->MCastFilter,
+ MAX_MCAST_FILTER_CNT * sizeof (EFI_MAC_ADDRESS));
+
+ // Set the interface type (1: Ethernet or 6: IEEE 802 Networks)
+ SnpMode->IfType = NET_IFTYPE_ETHERNET;
+
+ // Mac address is changeable
+ SnpMode->MacAddressChangeable = TRUE;
+
+ // We can only transmit one packet at a time
+ SnpMode->MultipleTxSupported = FALSE;
+
+ // MediaPresent checks for cable connection and partner link
+ SnpMode->MediaPresentSupported = TRUE;
+ SnpMode->MediaPresent = FALSE;
+
+ // Set broadcast address
+ SetMem (&SnpMode->BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);
+
+ // Assign fields for device path
+ NetsecPath->Netsec.MacAddress = SnpMode->PermanentAddress;
+ NetsecPath->Netsec.IfType = SnpMode->IfType;
+
+ InitializeListHead (&LanDriver->TxBufferList);
+
+ // Initialise the protocol
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &LanDriver->ControllerHandle,
+ &gEfiSimpleNetworkProtocolGuid, Snp,
+ &gEfiDevicePathProtocolGuid, NetsecPath,
+ NULL);
+
+ // Say what the status of loading the protocol structure is
+ if (EFI_ERROR (Status)) {
+ ogma_terminate (LanDriver->Handle);
+ FreePool (LanDriver);
+ }
+
+ return Status;
+}
new file mode 100644
@@ -0,0 +1,47 @@
+## @file
+#
+# Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = OpenPlatformDriversNetNetsecDxePkg
+ PACKAGE_GUID = bd8ddfdd-2e8d-4081-8117-99405df3ffc8
+ PACKAGE_VERSION = 0.1
+
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Guids.common]
+ gNetsecDxeTokenSpaceGuid = { 0x47d6c028, 0x2413, 0x416d, { 0xa8, 0xef, 0xe4, 0x5c, 0x58, 0x83, 0x5e, 0x49 }}
+
+[PcdsFixedAtBuild.common]
+ # Netsec Ethernet Driver PCDs
+ gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress|0x0|UINT32|0x00000000
+ gNetsecDxeTokenSpaceGuid.PcdEepRomBase|0x0|UINT32|0x00000001
+ gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|0x0|UINT16|0x00000002
+ gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|0x0|UINT16|0x00000003
+ gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0x0|UINT8|0x00000004
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0x0|UINT8|0x00000005
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|0x0|UINT16|0x00000006
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|0x0|UINT16|0x00000007
+ gNetsecDxeTokenSpaceGuid.PcdPauseTime|0x0|UINT16|0x00000008
+ gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr|0x0|UINT8|0x00000009
new file mode 100644
@@ -0,0 +1,83 @@
+/** @file
+
+ Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NETSEC_DXE_H_
+#define __NETSEC_DXE_H_
+
+#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
+
+/*--------------- Simple Network Driver entry point functions ----------------*/
+
+// Refer to the Simple Network Protocol section (21.1)
+// in the UEFI 2.3.1 Specification for documentation.
+
+#define ReturnUnlock(s) do { Status = (s); goto ExitUnlock; } while (0)
+
+/*------------------------------------------------------------------------------
+ NETSEC Information Structure
+------------------------------------------------------------------------------*/
+
+typedef struct {
+ // Driver signature
+ UINT32 Signature;
+ EFI_HANDLE ControllerHandle;
+
+ // EFI SNP protocol instances
+ EFI_SIMPLE_NETWORK_PROTOCOL Snp;
+ EFI_SIMPLE_NETWORK_MODE SnpMode;
+
+ // EFI Snp statistics instance
+ EFI_NETWORK_STATISTICS Stats;
+
+ // ogma handle
+ ogma_handle_t Handle;
+
+ // List of submitted TX buffers
+ LIST_ENTRY TxBufferList;
+
+ EFI_EVENT ExitBootEvent;
+} NETSEC_DRIVER;
+
+#define NETSEC_SIGNATURE SIGNATURE_32('n', 't', 's', 'c')
+#define INSTANCE_FROM_SNP_THIS(a) CR((a), NETSEC_DRIVER, Snp, NETSEC_SIGNATURE)
+
+typedef struct {
+ MAC_ADDR_DEVICE_PATH Netsec;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} NETSEC_DEVICE_PATH;
+
+/*------------------------------------------------------------------------------
+
+------------------------------------------------------------------------------*/
+
+#define MAC_ADDRESS (PcdGet32 (PcdEepRomBase) + 0x00)
+
+#define HM_ME_ADDRESS_H (PcdGet32 (PcdEepRomBase) + 0x08)
+#define HM_ME_ADDRESS_L (PcdGet32 (PcdEepRomBase) + 0x0C)
+#define HM_ME_SIZE (PcdGet32 (PcdEepRomBase) + 0x10)
+
+#define MH_ME_ADDRESS_H (PcdGet32 (PcdEepRomBase) + 0x14)
+#define MH_ME_ADDRESS_L (PcdGet32 (PcdEepRomBase) + 0x18)
+#define MH_ME_SIZE (PcdGet32 (PcdEepRomBase) + 0x1C)
+
+#define PACKET_ME_ADDRESS (PcdGet32 (PcdEepRomBase) + 0x20)
+#define PACKET_ME_SIZE (PcdGet32 (PcdEepRomBase) + 0x24)
+
+#define SCAT_NUM 1
+
+#define RXINT_TMR_CNT_US 0
+#define RXINT_PKTCNT 1
+
+#endif
new file mode 100644
@@ -0,0 +1,69 @@
+## @file
+#
+# Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = NetsecDxe
+ FILE_GUID = a4eed3af-9837-46b3-9275-c71cb47071f9
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 0.1
+ ENTRY_POINT = NetsecDxeEntry
+
+[Sources]
+ NetsecDxe.c
+
+ netsec_for_uefi/pfdep_uefi.c
+ netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
+ netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
+ netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
+ netsec_for_uefi/netsec_sdk/src/ogma_misc.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ NetworkPkg/NetworkPkg.dec
+ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DevicePathLib
+ DmaLib
+ IoLib
+ NetLib
+ SynchronizationLib
+ TimerLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Protocols]
+ gEfiDevicePathProtocolGuid
+ gEfiSimpleNetworkProtocolGuid
+
+[FixedPcd]
+ gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum
+ gNetsecDxeTokenSpaceGuid.PcdEepRomBase
+ gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrl
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold
+ gNetsecDxeTokenSpaceGuid.PcdJumboPacket
+ gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress
+ gNetsecDxeTokenSpaceGuid.PcdPauseTime
+ gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr
+
+[Depex]
+ gEfiCpuArchProtocolGuid
new file mode 100644
@@ -0,0 +1,736 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_API_H
+#define OGMA_API_H
+
+#include "ogma_version.h"
+#include "netsec_for_uefi/ogma_config.h"
+#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
+#include "netsec_for_uefi/pfdep.h"
+/**
+ * Check configuration macro settings.
+ */
+#ifdef OGMA_CONFIG_CLK_HZ
+#if ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) )
+#error "OGMA_CONFIG_CLK_HZ is not appropriate."
+#endif /* ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) ) */
+#else /* ! OGMA_CONFIG_CLK_HZ */
+#error "OGMA_CONFIG_CLK_HZ is not given."
+#endif /* OGMA_CONFIG_CLK_HZ */
+
+#ifndef OGMA_CONFIG_GMAC_CLK_HZ
+#define OGMA_CONFIG_GMAC_CLK_HZ OGMA_CONFIG_CLK_HZ
+#endif
+
+/**
+ * Number of hardware limits
+ */
+
+
+/**
+ * Number of Common Descriptor ring id
+ */
+#define OGMA_DESC_RING_ID_NRM_TX 0
+#define OGMA_DESC_RING_ID_NRM_RX 1
+
+#define OGMA_DESC_RING_ID_GMAC 15
+#define OGMA_DESC_RING_ID_MAX 1
+
+/**
+ * Numbre of TCP Segmentation length limits
+ */
+#define OGMA_TCP_SEG_LEN_MAX 1460
+#define OGMA_TCP_JUMBO_SEG_LEN_MAX 8960
+
+/**
+ * Number of ER check result for received packet
+ */
+#define OGMA_RX_ER_RESULT_NG 0x1
+#define OGMA_RX_ER_RESULT_OK 0x0
+
+/**
+ * Number of checksum calculation result for received packet
+ */
+#define OGMA_RX_CKSUM_RESULT_OK 0x1
+#define OGMA_RX_CKSUM_RESULT_NG 0x2
+#define OGMA_RX_CKSUM_RESULT_NOTAVAIL 0x0
+
+/**
+ * Number of ErrorCode for received packet
+ */
+#define OGMA_RX_ERRCODE_HEADER_INCOMLETE_ERR 0x2
+#define OGMA_RX_ERRCODE_IP_HEADER_ERR 0x1
+#define OGMA_RX_ERRCODE_NONE 0x0
+
+/**
+ * Number of top interrupt enable register bit field
+ */
+#define OGMA_TOP_IRQ_REG_ME_START (1UL << 20)
+#define OGMA_TOP_IRQ_REG_MAC (1UL << 19)
+#define OGMA_TOP_IRQ_REG_PKT (1UL << 18)
+#define OGMA_TOP_IRQ_REG_BOOTCODE_TX (1UL << 5)
+#define OGMA_TOP_IRQ_REG_NRM_RX (1UL << 1)
+#define OGMA_TOP_IRQ_REG_NRM_TX (1UL << 0)
+
+
+/**
+ * Number of top channel enable register bit field
+ */
+#define OGMA_CH_IRQ_REG_EMPTY (1UL << 17)
+#define OGMA_CH_IRQ_REG_ERR (1UL << 16)
+#define OGMA_CH_IRQ_REG_PKT_CNT (1UL << 15)
+#define OGMA_CH_IRQ_REG_TIMEUP (1UL << 14)
+#define OGMA_CH_IRQ_REG_RCV (OGMA_CH_IRQ_REG_PKT_CNT | OGMA_CH_IRQ_REG_TIMEUP)
+
+/**
+ * Number of top channel enable register bit field for F_NETSEC_C
+ */
+#define OGMA_CH_IRQ_REG_TX_DONE (1UL << 15)
+#define OGMA_CH_IRQ_REG_SND (OGMA_CH_IRQ_REG_TX_DONE | OGMA_CH_IRQ_REG_TIMEUP)
+
+
+/**
+ * Number of packet interrupt enable register bit field
+ */
+#define OGMA_PKT_IRQ_MAC_ER (1UL << 5)
+#define OGMA_PKT_IRQ_JUMBO_ER (1UL << 4)
+#define OGMA_PKT_IRQ_CHKSUM_ER (1UL << 3)
+#define OGMA_PKT_IRQ_HD_INCOMPLETE (1UL << 2)
+#define OGMA_PKT_IRQ_HD_ER (1UL << 1)
+#define OGMA_PKT_IRQ_DRP_NO_MATCH (1UL << 0)
+
+
+/**
+ * Number of mac irq enable register bit field
+ */
+#define OGMA_MAC_IRQ_INT_PMT (1UL << 31)
+#define OGMA_MAC_IRQ_INT_SBD (1UL << 30)
+#define OGMA_MAC_IRQ_INT_LPI (1UL << 29)
+#define OGMA_MAC_IRQ_INT_MAC_TX_RX_INFO_INT (1UL << 27)
+#define OGMA_MAC_IRQ_INT_LPI_TX_ENTRY (1UL << 26)
+#define OGMA_MAC_IRQ_INT_LPI_RX_ENTRY (1UL << 25)
+#define OGMA_MAC_IRQ_INT_LPI_TX_EXIT (1UL << 24)
+#define OGMA_MAC_IRQ_INT_LPI_RX_EXIT (1UL << 23)
+
+
+/**
+ * Number of SR IER register bit field
+ */
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GLPII (1U << 30)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TTI (1U << 29)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GPI (1U << 28)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GMI (1U << 27)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GLI (1U << 26)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_NIS (1U << 16)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_AIS (1U << 15)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_ERI (1U << 14)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_FBI (1U << 13)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_ETI (1U << 10)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RWT (1U << 9)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RPS (1U << 8)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RU (1U << 7)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RI (1U << 6)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_UNF (1U << 5)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_OVF (1U << 4)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TJT (1U << 3)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TU (1U << 2)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TPS (1U << 1)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TI (1U << 0)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TI)
+
+#define OGMA_GMAC_INT_SBD_IRQ_SR_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_GLPII | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TTI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_GPI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_GMI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_GLI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TI)
+
+#define OGMA_GMAC_INT_SBD_IRQ_IER_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TI)
+
+/**
+ * Number of ISR IMR register bit field
+ */
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_LPII (1U << 10)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_TSI (1U << 9)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_COI (1U << 7)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_TI (1U << 6)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_RI (1U << 5)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_MI (1U << 4)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_PI (1U << 3)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_RGI (1U << 0)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_ALL ( OGMA_GMAC_INT_SBD_IRQ_ISR_LPII | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_TSI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_COI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_TI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_RI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_MI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_PI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_RGI)
+
+/**
+ * Number of LPICSR register bit field
+ */
+#define OGMA_GMAC_LPICSR_REG_LPITXA (1U << 19)
+#define OGMA_GMAC_LPICSR_REG_PLSEN (1U << 18)
+#define OGMA_GMAC_LPICSR_REG_PLS (1U << 17)
+#define OGMA_GMAC_LPICSR_REG_LPIEN (1U << 16)
+#define OGMA_GMAC_LPICSR_REG_RLPIST (1U << 9)
+#define OGMA_GMAC_LPICSR_REG_TLPIST (1U << 8)
+#define OGMA_GMAC_LPICSR_REG_RLPIEX (1U << 3)
+#define OGMA_GMAC_LPICSR_REG_RLPIEN (1U << 2)
+#define OGMA_GMAC_LPICSR_REG_TLPIEX (1U << 1)
+#define OGMA_GMAC_LPICSR_REG_TLPIEN (1U << 0)
+
+/**
+ * Number of RGSR register bit field
+ */
+#define OGMA_GMAC_RGSR_REG_LS (1U << 3)
+#define OGMA_GMAC_RGSR_REG_LSP (1U << 1)
+#define OGMA_GMAC_RGSR_REG_LM (1U << 0)
+
+/**
+ * Number of various limits
+ */
+#define OGMA_DESC_ENTRY_NUM_MIN 2
+#define OGMA_DESC_ENTRY_NUM_MAX 2047
+#define OGMA_INT_PKTCNT_MAX 2047
+#define OGMA_L4_MIN_LEN_MAX 64
+
+/**
+ * Number of ogma phy interface setting
+ */
+#define OGMA_PHY_INTERFACE_GMII 0
+#define OGMA_PHY_INTERFACE_RGMII 1
+#define OGMA_PHY_INTERFACE_RMII 4
+
+/**
+ * Number of ogma link speed setting
+ */
+#define OGMA_PHY_LINK_SPEED_1G 0
+#define OGMA_PHY_LINK_SPEED_100M 1U
+#define OGMA_PHY_LINK_SPEED_10M 2U
+#define OGMA_PHY_LINK_SPEED_100M_OR_10M 3U
+
+/**
+ * Number of flow control limits
+ */
+#define OGMA_FLOW_CTRL_START_THRESHOLD_MAX 95
+#define OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX 95
+#define OGMA_FLOW_CTRL_PAUSE_TIME_MIN 5
+
+enum ogma_err_e{
+ OGMA_ERR_OK = 0,
+ OGMA_ERR_PARAM,
+ OGMA_ERR_ALLOC,
+ OGMA_ERR_BUSY,
+ OGMA_ERR_RANGE,
+ OGMA_ERR_DATA,
+ OGMA_ERR_NOTAVAIL,
+ OGMA_ERR_INTERRUPT,
+ OGMA_ERR_AGAIN,
+ OGMA_ERR_INVALID,
+};
+
+typedef void *ogma_handle_t;
+typedef struct ogma_param_s ogma_param_t;
+typedef struct ogma_pkt_ctrl_param_s ogma_pkt_ctrl_param_t;
+typedef struct ogma_desc_ring_param_s ogma_desc_ring_param_t;
+typedef enum ogma_err_e ogma_err_t;
+typedef ogma_uint8 ogma_desc_ring_id_t;
+typedef struct ogma_tx_pkt_ctrl_s ogma_tx_pkt_ctrl_t;
+typedef struct ogma_rx_pkt_info_s ogma_rx_pkt_info_t;
+typedef struct ogma_frag_info_s ogma_frag_info_t;
+typedef struct ogma_gmac_config_s ogma_gmac_config_t;
+typedef struct ogma_gmac_mode_s ogma_gmac_mode_t;
+
+struct ogma_gmac_config_s{
+ ogma_uint8 phy_interface;
+};
+
+struct ogma_pkt_ctrl_param_s{
+ ogma_uint log_chksum_er_flag:1;
+ ogma_uint log_hd_imcomplete_flag:1;
+ ogma_uint log_hd_er_flag:1;
+ ogma_uint drp_no_match_flag:1;
+};
+
+struct ogma_desc_ring_param_s{
+ ogma_uint valid_flag:1;
+ ogma_uint little_endian_flag:1;
+ ogma_uint tmr_mode_flag:1;
+ ogma_uint16 entry_num;
+};
+
+struct ogma_param_s{
+
+ ogma_uint use_gmac_flag:1;
+ ogma_uint use_jumbo_pkt_flag:1;
+ ogma_pkt_ctrl_param_t pkt_ctrl_param;
+ ogma_desc_ring_param_t desc_ring_param[OGMA_DESC_RING_ID_MAX+1];
+ ogma_gmac_config_t gmac_config;
+ ogma_uint8 mac_addr[6];
+};
+
+struct ogma_tx_pkt_ctrl_s{
+ ogma_uint pass_through_flag:1;
+ ogma_uint cksum_offload_flag:1;
+ ogma_uint tcp_seg_offload_flag:1;
+ ogma_desc_ring_id_t target_desc_ring_id;
+ ogma_uint16 tcp_seg_len;
+};
+
+struct ogma_rx_pkt_info_s{
+ ogma_uint fragmented_flag:1;
+ ogma_uint err_flag:1;
+ ogma_uint rx_cksum_result:2;
+ ogma_uint8 err_code;
+};
+
+struct ogma_frag_info_s{
+ pfdep_phys_addr_t phys_addr;
+ void *addr;
+ ogma_uint32 len;
+};
+
+struct ogma_gmac_mode_s{
+ ogma_uint half_duplex_flag:1;
+ ogma_uint flow_ctrl_enable_flag:1;
+ ogma_uint8 link_speed;
+ ogma_uint16 flow_ctrl_start_threshold;
+ ogma_uint16 flow_ctrl_stop_threshold;
+ ogma_uint16 pause_time;
+};
+
+#ifdef OGMA_CONFIG_REC_STAT
+typedef struct ogma_stat_info_s {
+ ogma_uint16 current_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1];
+ ogma_uint16 max_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1];
+} ogma_stat_info_t;
+#endif /* OGMA_CONFIG_REC_STAT */
+
+typedef struct ogma_gmac_int_sbd_regs_s{
+ ogma_uint32 base;
+ ogma_uint32 extended;
+} ogma_gmac_int_sbd_regs_t;
+
+typedef struct ogma_phy_link_status_s{
+ ogma_uint up_flag:1;
+ ogma_uint auto_nego_enable_flag:1;
+ ogma_uint auto_nego_complete_flag:1;
+ ogma_uint half_duplex_flag:1;
+ ogma_uint latched_link_down_flag:1;
+ ogma_uint lpi_capable_flag:1;
+ ogma_uint8 link_speed;
+} ogma_phy_link_status_t;
+
+/**************************
+***************************
+***************************/
+
+ogma_err_t ogma_init (
+ void *base_addr,
+ pfdep_dev_handle_t dev_handle,
+ const ogma_param_t *param_p,
+ const void *dma_hm_mc_addr,
+ ogma_uint32 dma_hm_mc_len,
+ const void *dma_mh_mc_addr,
+ ogma_uint32 dma_mh_mc_len,
+ const void *pktc_mc_addr,
+ ogma_uint32 pktc_mc_len,
+ ogma_handle_t *ogma_handle_p
+ );
+
+void ogma_terminate (
+ ogma_handle_t ogma_handle
+ );
+
+ogma_err_t ogma_start_gmac (
+ ogma_handle_t ogma_handle,
+ ogma_bool rx_flag,
+ ogma_bool tx_flag
+ );
+
+ogma_err_t ogma_stop_gmac (
+ ogma_handle_t ogma_handle,
+ ogma_bool rx_flag,
+ ogma_bool tx_flag
+ );
+
+ogma_err_t ogma_set_gmac_mode (
+ ogma_handle_t ogma_handle,
+ const ogma_gmac_mode_t *gmac_mode_p
+ );
+
+void ogma_set_phy_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr,
+ ogma_uint16 value
+ );
+
+ogma_uint16 ogma_get_phy_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr
+ );
+
+ogma_err_t ogma_get_gmac_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool *valid_flag_p,
+ ogma_gmac_mode_t *gmac_mode_p,
+ ogma_bool *rx_running_flag_p,
+ ogma_bool *tx_running_flag_p
+ );
+
+ogma_uint32 ogma_get_top_irq_enable (
+ ogma_handle_t ogma_handle
+ );
+
+ogma_uint32 ogma_get_top_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ );
+
+#define ogma_get_top_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_top_irq_status(ogma_handle,mask_flag)
+
+ogma_err_t ogma_clear_top_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ );
+
+ogma_uint32 ogma_get_desc_ring_irq_enable (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_uint32 ogma_get_desc_ring_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_bool mask_flag
+ );
+
+#define ogma_get_desc_ring_irq_status_non_clear(ogma_handle,ring_id,mask_flag) \
+ogma_get_desc_ring_irq_status(ogma_handle,ring_id,mask_flag)
+
+
+
+ogma_err_t ogma_clear_desc_ring_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 value
+ );
+
+ogma_uint32 ogma_get_pkt_irq_enable (
+ ogma_handle_t ogma_handle
+ );
+
+ogma_uint32 ogma_get_pkt_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ );
+
+#define ogma_get_pkt_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_pkt_irq_status(ogma_handle,mask_flag)
+
+
+ogma_err_t ogma_clear_pkt_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ );
+
+/* ogma_desc_ring_access.c */
+ogma_err_t ogma_start_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_err_t ogma_stop_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_uint16 ogma_get_rx_num (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_uint16 ogma_get_tx_avail_num (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_err_t ogma_clean_tx_desc_ring(
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_err_t ogma_clean_rx_desc_ring(
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_err_t ogma_set_tx_pkt_data (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+ ogma_uint8 scat_num,
+ const ogma_frag_info_t *scat_info_p,
+ pfdep_pkt_handle_t pkt_handle
+ );
+
+ogma_err_t ogma_get_rx_pkt_data (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_rx_pkt_info_t *rx_pkt_info_p,
+ ogma_frag_info_t *frag_info_p,
+ ogma_uint16 *len_p,
+ pfdep_pkt_handle_t *pkt_handle_p
+ );
+
+ogma_err_t ogma_enable_top_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_disable_top_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_enable_desc_ring_irq (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_disable_desc_ring_irq (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_enable_pkt_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_disable_pkt_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+ogma_uint32 ogma_get_hw_ver (
+ ogma_handle_t ogma_handle
+ );
+
+ogma_uint32 ogma_get_mcr_ver (
+ ogma_handle_t ogma_handle
+ );
+
+/**
+ * Set up IRQ coalesce parameters.
+ *
+ * [Note]
+ * - This is a tentative implementation.
+ * Not tested enough. Use with care.
+ *
+ * - Call this function after every invocation of ogma_start_desc_ring()
+ * because ogma_start_desc_ring() resets IRQ coalesce settings.
+ *
+ */
+ogma_err_t ogma_set_irq_coalesce_param (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint16 int_pktcnt,
+ ogma_bool int_tmr_unit_ms_flag,
+ ogma_uint16 int_tmr_cnt
+ );
+
+ogma_uint32 ogma_get_mac_irq_enable (
+ ogma_handle_t ogma_handle
+ );
+
+
+ogma_uint32 ogma_get_mac_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ );
+
+#define ogma_get_mac_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_mac_irq_status(ogma_handle,mask_flag)
+
+
+ogma_err_t ogma_clear_mac_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ );
+
+ogma_err_t ogma_enable_mac_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_disable_mac_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+#ifdef OGMA_CONFIG_REC_STAT
+/**
+ * Get statistics information.
+ */
+ogma_err_t ogma_get_stat_info (
+ ogma_handle_t ogma_handle,
+ ogma_stat_info_t *stat_info_p,
+ ogma_bool clear_flag
+ );
+#endif /* OGMA_CONFIG_REC_STAT */
+
+ogma_err_t ogma_set_gmac_lpictrl_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ );
+
+ogma_err_t ogma_get_gmac_lpictrl_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p
+ );
+
+ogma_err_t ogma_set_gmac_lpitimer_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint16 ls_timer_ms,
+ ogma_uint16 tw_timer_ms
+ );
+
+ogma_err_t ogma_get_gmac_lpitimer_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint16 *ls_timer_ms_p,
+ ogma_uint16 *tw_timer_ms_p
+ );
+
+void ogma_set_phy_mmd_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr,
+ ogma_uint16 value
+ );
+
+ogma_uint16 ogma_get_phy_mmd_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ );
+
+ogma_err_t ogma_get_phy_link_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_phy_link_status_t *phy_link_status_p
+ );
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable (
+ ogma_handle_t ogma_handle
+ );
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ );
+
+#define ogma_get_gmac_int_sbd_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_gmac_int_sbd_irq_status(ogma_handle,mask_flag)
+
+ogma_err_t ogma_clear_gmac_int_sbd_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ );
+
+ogma_err_t ogma_enable_gmac_int_sbd_irq (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ );
+
+ogma_err_t ogma_disable_gmac_int_sbd_irq (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ );
+
+ogma_err_t ogma_get_gmac_rgmii_status_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p
+ );
+
+#ifdef OGMA_CONFIG_USE_READ_GMAC_STAT
+ogma_err_t ogma_read_gmac_stat (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p,
+ ogma_bool reset_flag
+ );
+#endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */
+
+ogma_err_t ogma_reset_gmac_stat (
+ ogma_handle_t ogma_handle
+ );
+
+/**************************
+***************************
+***************************/
+
+#endif /* OGMA_API_H*/
new file mode 100644
@@ -0,0 +1,45 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_BASIC_TYPE_H
+#define OGMA_BASIC_TYPE_H
+#include "netsec_for_uefi/pfdep.h"
+
+/**
+ *
+ */
+#define OGMA_TRUE PFDEP_TRUE
+#define OGMA_FALSE PFDEP_FALSE
+
+/**
+ * OGMA SDK BASIC DATA TYPE
+ */
+typedef pfdep_int8 ogma_int8;
+typedef pfdep_uint8 ogma_uint8;
+typedef pfdep_int16 ogma_int16;
+typedef pfdep_uint16 ogma_uint16;
+typedef pfdep_int32 ogma_int32;
+typedef pfdep_uint32 ogma_uint32;
+typedef int ogma_int;
+typedef unsigned int ogma_uint;
+typedef pfdep_bool ogma_bool;
+typedef pfdep_char ogma_char;
+
+#ifdef PFDEP_INT64_AVAILABLE
+typedef signed long long ogma_int64;
+typedef unsigned long long ogma_uint64;
+#endif /* PFDEP_INT64_AVAILABLE*/
+
+#endif /* OGMA_BASIC_TYPE_H */
new file mode 100644
@@ -0,0 +1,24 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_VERSION_H
+#define OGMA_VERSION_H
+
+#define OGMA_VER_NETSEC (0x00050050UL)
+
+#define OGMA_INVALID_VER 0x0
+#define OGMA_VER_MAJOR_NUM(x) ((x) & 0xffff0000UL)
+
+#endif /* OGMA_VERSION_H */
new file mode 100644
@@ -0,0 +1,88 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+void ogma_set_mac_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 addr,
+ ogma_uint32 value)
+{
+
+ ogma_uint32 cmd;
+
+ ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+ /*
+ * Argument check is omitted because this function is
+ * of private use only.
+ */
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_DATA,
+ value);
+
+ cmd = addr | OGMA_GMAC_CMD_ST_WRITE;
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_CMD,
+ cmd);
+
+ /*
+ * Waits until BUSY bit is cleared.
+ */
+ while ( ( ogma_read_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_CMD)
+ & OGMA_GMAC_CMD_ST_BUSY)
+ != 0) {
+ ;
+ }
+}
+
+ogma_uint32 ogma_get_mac_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 addr)
+{
+ ogma_uint32 cmd;
+
+ ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+ /*
+ * Argument check is omitted because this function is
+ * of private use only.
+ */
+
+ cmd = addr | OGMA_GMAC_CMD_ST_READ;
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_CMD,
+ cmd);
+
+ /*
+ * Waits until BUSY bit is cleared.
+ */
+ while ( ( ogma_read_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_CMD)
+ & OGMA_GMAC_CMD_ST_BUSY)
+ != 0) {
+ ;
+ }
+ return ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DATA);
+}
new file mode 100644
@@ -0,0 +1,52 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_BASIC_ACCESS_H
+#define OGMA_BASIC_ACCESS_H
+
+#include "ogma_internal.h"
+
+static __inline void ogma_write_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 reg_addr,
+ ogma_uint32 value
+ )
+{
+
+ pfdep_iomem_write( (void *) ( ( pfdep_cpu_addr_t)ctrl_p->base_addr +
+ ( reg_addr << 2) ),
+ value);
+}
+
+static __inline ogma_uint32 ogma_read_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 reg_addr
+ )
+{
+
+ return ( ogma_uint32)pfdep_iomem_read( (void *)( ( pfdep_cpu_addr_t)ctrl_p->base_addr +
+ ( reg_addr << 2) ) );
+}
+
+void ogma_set_mac_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 addr,
+ ogma_uint32 value);
+
+ogma_uint32 ogma_get_mac_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 addr);
+
+#endif/* OGMA_BASIC_ACCESS_H */
new file mode 100644
@@ -0,0 +1,1391 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+#include "ogma_desc_ring_access_internal.h"
+
+
+const ogma_uint32 ogma_desc_start_reg_addr_upper[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_DESC_START_UP,
+ OGMA_REG_ADDR_NRM_RX_DESC_START_UP,
+};
+
+const ogma_uint32 ogma_desc_start_reg_addr_lower[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_DESC_START_LW,
+ OGMA_REG_ADDR_NRM_RX_DESC_START_LW,
+};
+
+const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+ OGMA_REG_ADDR_NRM_TX_INTEN,
+ OGMA_REG_ADDR_NRM_RX_INTEN,
+};
+
+const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+ OGMA_REG_ADDR_NRM_TX_INTEN_SET,
+ OGMA_REG_ADDR_NRM_RX_INTEN_SET,
+};
+
+const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+ OGMA_REG_ADDR_NRM_TX_INTEN_CLR,
+ OGMA_REG_ADDR_NRM_RX_INTEN_CLR,
+};
+
+static const ogma_uint32 int_tmr_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_TXINT_TMR,
+ OGMA_REG_ADDR_NRM_RX_RXINT_TMR,
+};
+
+static const ogma_uint32 rx_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+ 0,
+ OGMA_REG_ADDR_NRM_RX_PKTCNT,
+};
+
+static const ogma_uint32 tx_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_PKTCNT,
+ 0,
+
+};
+
+static const ogma_uint32 int_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT,
+ OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT,
+};
+
+static const ogma_uint32 tx_done_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT,
+ 0,
+};
+
+
+STATIC void ogma_set_tx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+ ogma_bool first_flag,
+ ogma_bool last_flag,
+ ogma_bool trs_flag,
+ const ogma_frag_info_t *frag_info_p,
+ pfdep_pkt_handle_t pkt_handle);
+
+STATIC void ogma_set_rx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ const ogma_frag_info_t *frag_info_p,
+ pfdep_pkt_handle_t pkt_handle);
+
+STATIC void ogma_get_rx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ ogma_rx_pkt_info_t *rx_pkt_info_p,
+ ogma_frag_info_t *frag_info_p,
+ ogma_uint16 *len_p,
+ pfdep_pkt_handle_t *pkt_handle_p);
+
+STATIC void ogma_clean_tx_desc_ring_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+STATIC void ogma_clean_rx_desc_ring_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+STATIC void ogma_inc_desc_head_idx (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 increment);
+
+STATIC void ogma_inc_desc_tail_idx (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 increment);
+
+STATIC ogma_uint16 ogma_get_tx_avail_num_sub (
+ ogma_ctrl_t *ctrl_p,
+ const ogma_desc_ring_t *desc_ring_p
+ );
+
+STATIC ogma_uint16 ogma_get_tx_done_num_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+static __inline void ogma_desc_ring_cpy_to_mem(
+ void *dst_p,
+ void *src_p,
+ ogma_uint32 len)
+{
+ pfdep_memcpy(dst_p,src_p,len);
+}
+
+static __inline void ogma_desc_ring_cpy_from_mem(
+ void *dst_p,
+ void *src_p,
+ ogma_uint32 len)
+{
+ pfdep_memcpy(dst_p,src_p,len);
+}
+
+static __inline void ogma_desc_ring_memclr(
+ void *dst_p,
+ ogma_uint32 len)
+{
+ pfdep_memset(dst_p,0,len);
+}
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+ogma_err_t ogma_alloc_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_desc_ring_t *desc_ring_p = &ctrl_p->desc_ring[ring_id];
+ ogma_desc_ring_param_t *desc_ring_param_p = &ctrl_p->desc_ring[ring_id].param;
+ pfdep_err_t pfdep_err;
+
+ if ( ( ctrl_p->param.desc_ring_param[ring_id].valid_flag) &&
+ ( ( ctrl_p->param.desc_ring_param[ring_id].entry_num <
+ OGMA_DESC_ENTRY_NUM_MIN) ||
+ ( ctrl_p->param.desc_ring_param[ring_id].entry_num >
+ OGMA_DESC_ENTRY_NUM_MAX) ) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Please set entry_num between %d and %d.\n",
+ OGMA_DESC_ENTRY_NUM_MIN, OGMA_DESC_ENTRY_NUM_MAX);
+ return OGMA_ERR_PARAM;
+ }
+
+ desc_ring_p->ring_id = ring_id;
+
+ pfdep_memcpy( desc_ring_param_p,
+ &ctrl_p->param.desc_ring_param[ring_id],
+ sizeof( ogma_desc_ring_param_t) );
+
+ if ( !desc_ring_param_p->valid_flag) {
+
+ desc_ring_p->desc_ring_phys_addr = ctrl_p->dummy_desc_entry_phys_addr;
+
+ ogma_write_reg( ctrl_p,
+ ogma_desc_start_reg_addr_upper[ring_id],
+ (ogma_uint32)(desc_ring_p->desc_ring_phys_addr >> 32));
+ ogma_write_reg( ctrl_p,
+ ogma_desc_start_reg_addr_lower[ring_id],
+ (ogma_uint32)desc_ring_p->desc_ring_phys_addr);
+
+ return OGMA_ERR_OK;
+ }
+
+ switch ( ring_id) {
+ case OGMA_DESC_RING_ID_NRM_TX:
+ desc_ring_p->tx_desc_ring_flag = OGMA_TRUE;
+ desc_ring_p->desc_entry_len = sizeof( ogma_tx_desc_entry_t);
+ break;
+
+ case OGMA_DESC_RING_ID_NRM_RX:
+ desc_ring_p->rx_desc_ring_flag = OGMA_TRUE;
+ desc_ring_p->desc_entry_len = sizeof( ogma_rx_desc_entry_t);
+ break;
+
+ default:
+ pfdep_assert(0);
+ }
+
+ if ( ( pfdep_err = pfdep_init_hard_lock ( &desc_ring_p->inten_reg_hard_lock) )
+ != PFDEP_ERR_OK) {
+ pfdep_memset( desc_ring_param_p,
+ 0,
+ sizeof( ogma_desc_ring_param_t) );
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Failed to inten_reg_hard_lock's initialization.\n");
+ return OGMA_ERR_ALLOC;
+ }
+
+ if ( ( pfdep_err = pfdep_init_soft_lock ( &desc_ring_p->soft_lock) )
+ != PFDEP_ERR_OK) {
+ pfdep_uninit_hard_lock ( &desc_ring_p->inten_reg_hard_lock);
+ pfdep_memset( desc_ring_param_p,
+ 0,
+ sizeof( ogma_desc_ring_param_t) );
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Failed to soft_lock's initialization.\n");
+ return OGMA_ERR_ALLOC;
+ }
+
+ if ( ( pfdep_err = pfdep_dma_malloc (
+ ( pfdep_dev_handle_t) ctrl_p->dev_handle,
+ ( pfdep_uint32) desc_ring_p->desc_entry_len * desc_ring_param_p->entry_num,
+ ( void **) &desc_ring_p->desc_ring_cpu_addr,
+ ( pfdep_phys_addr_t *) &desc_ring_p->desc_ring_phys_addr) )
+ != PFDEP_ERR_OK) {
+ ogma_err = OGMA_ERR_ALLOC;
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Failed to desc_ring entry memory allocation.\n");
+ goto err;
+ }
+
+ ogma_desc_ring_memclr(
+ desc_ring_p->desc_ring_cpu_addr,
+ ( ogma_uint32)desc_ring_p->desc_entry_len * desc_ring_param_p->entry_num);
+
+ ogma_write_reg( ctrl_p,
+ ogma_desc_start_reg_addr_upper[ring_id],
+ (ogma_uint32)(desc_ring_p->desc_ring_phys_addr >> 32));
+ ogma_write_reg( ctrl_p,
+ ogma_desc_start_reg_addr_lower[ring_id],
+ (ogma_uint32)desc_ring_p->desc_ring_phys_addr);
+
+ if ( ( desc_ring_p->frag_info_p =
+ pfdep_malloc( sizeof( ogma_frag_info_t) * desc_ring_param_p->entry_num) )
+ == NULL) {
+ ogma_err = OGMA_ERR_ALLOC;
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Failed to fragment infomation memory allocation.\n");
+ goto err;
+ }
+
+ pfdep_memset(
+ desc_ring_p->frag_info_p,
+ 0,
+ sizeof( ogma_frag_info_t) * desc_ring_param_p->entry_num);
+
+ if ( ( desc_ring_p->priv_data_p =
+ pfdep_malloc( sizeof( ogma_desc_entry_priv_t) * desc_ring_param_p->entry_num) )
+ == NULL) {
+ ogma_err = OGMA_ERR_ALLOC;
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Failed to private data memory allocation.\n");
+ goto err;
+ }
+
+ pfdep_memset(
+ desc_ring_p->priv_data_p,
+ 0,
+ sizeof( ogma_desc_entry_priv_t) * desc_ring_param_p->entry_num);
+
+ return OGMA_ERR_OK;
+
+err:
+ ogma_free_desc_ring( ctrl_p, desc_ring_p);
+ return ogma_err;
+}
+
+void ogma_free_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+
+ if ( !desc_ring_p->param.valid_flag) {
+ return ;
+ }
+ if ( ogma_is_pkt_desc_ring ( desc_ring_p) ) {
+ if ( ( desc_ring_p->desc_ring_cpu_addr != NULL) &&
+ ( desc_ring_p->frag_info_p != NULL) &&
+ ( desc_ring_p->priv_data_p != NULL) ) {
+ ogma_uninit_pkt_desc_ring( ctrl_p, desc_ring_p);
+ }
+ }
+ if ( desc_ring_p->desc_ring_cpu_addr != NULL) {
+ pfdep_dma_free( ctrl_p->dev_handle,
+ ( ogma_uint32)desc_ring_p->desc_entry_len *
+ desc_ring_p->param.entry_num,
+ desc_ring_p->desc_ring_cpu_addr,
+ desc_ring_p->desc_ring_phys_addr);
+ }
+
+ if ( desc_ring_p->frag_info_p != NULL) {
+ pfdep_free(desc_ring_p->frag_info_p);
+ }
+
+ if ( desc_ring_p->priv_data_p != NULL) {
+ pfdep_free( desc_ring_p->priv_data_p);
+ }
+
+ pfdep_uninit_hard_lock ( &desc_ring_p->inten_reg_hard_lock);
+
+ pfdep_uninit_soft_lock ( &desc_ring_p->soft_lock);
+
+ pfdep_memset( desc_ring_p, 0, sizeof( ogma_desc_ring_t) );
+}
+
+ogma_err_t ogma_setup_rx_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+ ogma_uint16 idx;
+ ogma_frag_info_t frag_info= {0,0,0};
+
+ pfdep_err_t pfdep_err;
+ pfdep_pkt_handle_t tmp_pkt_handle;
+
+ frag_info.len = ctrl_p->rx_pkt_buf_len;
+
+ for ( idx = 0; idx < desc_ring_p->param.entry_num; idx++) {
+ if ( ( pfdep_err = pfdep_alloc_pkt_buf (
+ ( pfdep_dev_handle_t)ctrl_p->dev_handle,
+ ( ogma_uint16)frag_info.len,
+ ( void **)&frag_info.addr,
+ ( pfdep_phys_addr_t *)&frag_info.phys_addr,
+ ( pfdep_pkt_handle_t *)&tmp_pkt_handle) )
+ != PFDEP_ERR_OK) {
+ ogma_uninit_pkt_desc_ring( ctrl_p, desc_ring_p);
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_setup_rx_desc_ring.\n"
+ "Failed to rx packet memory allocation.\n");
+ return OGMA_ERR_ALLOC;
+ }
+ ogma_set_rx_desc_entry( ctrl_p,
+ desc_ring_p,
+ idx,
+ &frag_info,
+ tmp_pkt_handle);
+ }
+ return OGMA_ERR_OK;
+}
+
+void ogma_uninit_pkt_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+ ogma_uint16 idx;
+ ogma_uint32 tmp;
+ ogma_bool last_flag;
+
+ for ( idx = 0; idx < desc_ring_p->param.entry_num; idx++) {
+ if ( desc_ring_p->frag_info_p[idx].addr == NULL ) {
+ continue;
+ }
+
+ tmp = ogma_get_desc_ring_attr(desc_ring_p, idx);
+
+ last_flag = ( ( ( tmp >> 8) & 0x1) != 0);
+
+ pfdep_free_pkt_buf (
+ ctrl_p->dev_handle,
+ desc_ring_p->frag_info_p[idx].len,
+ desc_ring_p->frag_info_p[idx].addr,
+ desc_ring_p->frag_info_p[idx].phys_addr,
+ last_flag,
+ desc_ring_p->priv_data_p[idx].pkt_handle);
+ }
+
+ /* clear frag_info_p */
+ pfdep_memset( desc_ring_p->frag_info_p,
+ 0,
+ sizeof( ogma_frag_info_t) * desc_ring_p->param.entry_num);
+
+ /* clear pkt_handle_p */
+ pfdep_memset( desc_ring_p->priv_data_p,
+ 0,
+ sizeof( ogma_desc_entry_priv_t) * desc_ring_p->param.entry_num);
+
+ /* clear desc ring entry*/
+ ogma_desc_ring_memclr ( desc_ring_p->desc_ring_cpu_addr,
+ ( ogma_uint32)desc_ring_p->desc_entry_len *
+ desc_ring_p->param.entry_num);
+}
+
+STATIC void ogma_set_tx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+ ogma_bool first_flag,
+ ogma_bool last_flag,
+ ogma_bool trs_flag,
+ const ogma_frag_info_t *frag_info_p,
+ pfdep_pkt_handle_t pkt_handle
+ )
+{
+ ogma_tx_desc_entry_t tx_desc_entry;
+ ogma_uint32 attr, i, *debug_desc_entry_p;
+
+ ogma_check_desc_own_sanity(ctrl_p, desc_ring_p, idx, 0);
+
+ pfdep_memset( &tx_desc_entry, 0, sizeof( ogma_tx_desc_entry_t) );
+
+ attr = ( 1UL << OGMA_TX_PKT_DESC_RING_OWN_FIELD) |
+ ( desc_ring_p->ring_id << OGMA_TX_PKT_DESC_RING_DRID_FIELD) |
+ ( tx_pkt_ctrl_p->pass_through_flag <<
+ OGMA_TX_PKT_DESC_RING_PT_FIELD) |
+ ( tx_pkt_ctrl_p->target_desc_ring_id <<
+ OGMA_TX_PKT_DESC_RING_TDRID_FIELD) |
+ ( first_flag << OGMA_TX_PKT_DESC_RING_FS_FIELD) |
+ ( last_flag << OGMA_TX_PKT_DESC_RING_LS_FIELD) |
+ ( tx_pkt_ctrl_p->cksum_offload_flag <<
+ OGMA_TX_PKT_DESC_RING_CO_FIELD) |
+ ( tx_pkt_ctrl_p->tcp_seg_offload_flag <<
+ OGMA_TX_PKT_DESC_RING_SO_FIELD) |
+ ( trs_flag << OGMA_TX_PKT_DESC_RING_TRS_FIELD);
+
+ if ( idx == ( desc_ring_p->param.entry_num - 1) ) {
+ attr |= ( 0x1U << OGMA_TX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
+ }
+
+ tx_desc_entry.attr = attr;
+
+ tx_desc_entry.data_buf_addr_upper = (ogma_uint32)(frag_info_p->phys_addr >> 32);
+
+ tx_desc_entry.data_buf_addr_lower = (ogma_uint32)frag_info_p->phys_addr;
+
+ tx_desc_entry.buf_len_info =
+ ( tx_pkt_ctrl_p->tcp_seg_len << 16) | frag_info_p->len;
+
+ ogma_desc_ring_cpy_to_mem( ( (void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+ desc_ring_p->desc_entry_len * idx) ),
+ ( void *)&tx_desc_entry,
+ desc_ring_p->desc_entry_len);
+
+ debug_desc_entry_p = ( ogma_uint32 *)&tx_desc_entry;
+
+ for ( i = 0; i < ( sizeof( ogma_tx_desc_entry_t) >> 2); i++) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "%08x\n", debug_desc_entry_p[i]);
+ }
+
+ desc_ring_p->frag_info_p[idx].phys_addr = frag_info_p->phys_addr;
+ desc_ring_p->frag_info_p[idx].addr = frag_info_p->addr;
+ desc_ring_p->frag_info_p[idx].len = frag_info_p->len;
+ desc_ring_p->priv_data_p[idx].pkt_handle = pkt_handle;
+
+}
+
+STATIC void ogma_set_rx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ const ogma_frag_info_t *frag_info_p,
+ pfdep_pkt_handle_t pkt_handle
+ )
+{
+ ogma_rx_desc_entry_t rx_desc_entry;
+
+ ogma_check_desc_own_sanity(ctrl_p, desc_ring_p, idx, 0);
+
+ pfdep_memset( &rx_desc_entry, 0, sizeof ( ogma_rx_desc_entry_t) );
+
+ rx_desc_entry.attr = ( 1UL << OGMA_RX_PKT_DESC_RING_OWN_FIELD) |
+ ( 1UL << OGMA_RX_PKT_DESC_RING_FS_FIELD) |
+ ( 1UL << OGMA_RX_PKT_DESC_RING_LS_FIELD) ; /* OWN = FS = LS = 1 */
+
+ rx_desc_entry.data_buf_addr_upper = (ogma_uint32)(frag_info_p->phys_addr >> 32);
+
+ rx_desc_entry.data_buf_addr_lower = (ogma_uint32)frag_info_p->phys_addr;
+
+ rx_desc_entry.buf_len_info = frag_info_p->len;
+
+ if ( idx == ( desc_ring_p->param.entry_num - 1) ) {
+ rx_desc_entry.attr |= ( 0x1U << OGMA_RX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
+ }
+
+ ogma_desc_ring_cpy_to_mem( ( ( void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+ desc_ring_p->desc_entry_len * idx + 4) ),
+ ( void *) ( ( pfdep_cpu_addr_t)&rx_desc_entry + 4),
+ ( ogma_uint32)( desc_ring_p->desc_entry_len - 4U) );
+
+ pfdep_write_mem_barrier();
+
+ ogma_desc_ring_cpy_to_mem( ( ( void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+ desc_ring_p->desc_entry_len * idx) ),
+ ( void *)&rx_desc_entry,
+ 4);
+
+ desc_ring_p->frag_info_p[idx].phys_addr = frag_info_p->phys_addr;
+ desc_ring_p->frag_info_p[idx].addr = frag_info_p->addr;
+ desc_ring_p->frag_info_p[idx].len = frag_info_p->len;
+ desc_ring_p->priv_data_p[idx].pkt_handle = pkt_handle;
+}
+
+STATIC void ogma_get_rx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ ogma_rx_pkt_info_t *rx_pkt_info_p,
+ ogma_frag_info_t *frag_info_p,
+ ogma_uint16 *len_p,
+ pfdep_pkt_handle_t *pkt_handle_p)
+{
+ ogma_uint32 *debug_desc_entry_p;
+ ogma_rx_desc_entry_t rx_desc_entry;
+
+ ogma_check_desc_own_sanity( ctrl_p, desc_ring_p, idx, 0);
+
+ pfdep_memset( &rx_desc_entry, 0, sizeof( ogma_rx_desc_entry_t) );
+ pfdep_memset( rx_pkt_info_p, 0, sizeof( ogma_rx_pkt_info_t) );
+
+ ogma_desc_ring_cpy_from_mem( &rx_desc_entry,
+ (void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+ desc_ring_p->desc_entry_len * idx),
+ desc_ring_p->desc_entry_len);
+
+ debug_desc_entry_p = (ogma_uint32 *)&rx_desc_entry;
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "%08x\n", *debug_desc_entry_p);
+
+ *len_p = rx_desc_entry.buf_len_info >> 16;
+
+ rx_pkt_info_p->fragmented_flag =
+ ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_FR_FIELD) & 0x1; /* FR*/
+
+ rx_pkt_info_p->err_flag =
+ ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_ER_FIELD) & 0x1; /* ER */
+
+ rx_pkt_info_p->rx_cksum_result =
+ ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_CO_FIELD) & 0x3; /* CO */
+
+ rx_pkt_info_p->err_code =
+ ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD) &
+ OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK; /* Error Code */
+
+ pfdep_memcpy( frag_info_p,
+ &desc_ring_p->frag_info_p[idx],
+ sizeof(ogma_frag_info_t) );
+
+ *pkt_handle_p = desc_ring_p->priv_data_p[idx].pkt_handle;
+}
+
+#ifdef OGMA_CONFIG_REC_STAT
+STATIC __inline ogma_uint16 ogma_calc_busy_entry_num (
+ ogma_uint16 head_idx,
+ ogma_uint16 tail_idx,
+ ogma_uint16 entry_num,
+ ogma_bool full_flag
+ )
+{
+
+ ogma_int16 busy_entry_num;
+
+ if (full_flag) {
+ busy_entry_num = entry_num;
+ } else if (head_idx >= tail_idx) {
+ busy_entry_num = head_idx - tail_idx;
+ } else {
+ busy_entry_num = entry_num + head_idx - tail_idx;
+ }
+
+ return busy_entry_num;
+
+}
+#endif /* OGMA_CONFIG_REC_STAT */
+
+STATIC void ogma_clean_tx_desc_ring_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+
+ ogma_uint32 tmp;
+
+ ogma_get_tx_done_num_sub( ctrl_p, desc_ring_p);
+
+ while( ( (desc_ring_p->tail_idx != desc_ring_p->head_idx) ||
+ desc_ring_p->full_flag) && ( desc_ring_p->tx_done_num != 0) ) {
+
+ tmp = ogma_get_desc_ring_attr(desc_ring_p,
+ desc_ring_p->tail_idx);
+
+ pfdep_free_pkt_buf (
+ ctrl_p->dev_handle,
+ desc_ring_p->frag_info_p[desc_ring_p->tail_idx].len,
+ desc_ring_p->frag_info_p[desc_ring_p->tail_idx].addr,
+ desc_ring_p->frag_info_p[desc_ring_p->tail_idx].phys_addr,
+ ( ( ( tmp >> OGMA_TX_PKT_DESC_RING_LS_FIELD) & 0x1) != 0),
+ desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
+
+ pfdep_memset( &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
+ 0,
+ sizeof( ogma_frag_info_t) );
+
+ ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
+
+ if ( ( tmp & ( 1UL << OGMA_TX_PKT_DESC_RING_LS_FIELD) ) != 0) {
+
+ pfdep_assert( desc_ring_p->tx_done_num != 0);
+
+ desc_ring_p->tx_done_num--;
+
+ }
+ }
+
+}
+
+STATIC void ogma_clean_rx_desc_ring_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+
+ while( desc_ring_p->full_flag ||
+ ( desc_ring_p->tail_idx != desc_ring_p->head_idx) ) {
+
+ ogma_set_rx_desc_entry(
+ ctrl_p,
+ desc_ring_p,
+ desc_ring_p->tail_idx,
+ &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
+ desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
+
+ --desc_ring_p->rx_num;
+ ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
+ }
+
+ pfdep_assert( desc_ring_p->rx_num == 0);/* error check*/
+
+}
+
+STATIC void ogma_inc_desc_head_idx (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 increment)
+{
+ ogma_uint32 sum;
+
+ if ( ( desc_ring_p->tail_idx > desc_ring_p->head_idx) ||
+ desc_ring_p->full_flag) {
+ pfdep_assert( increment <=
+ ( desc_ring_p->tail_idx -
+ desc_ring_p->head_idx));
+ } else {
+ pfdep_assert( increment <=
+ ( desc_ring_p->param.entry_num +
+ desc_ring_p->tail_idx -
+ desc_ring_p->head_idx) );
+ }
+
+ sum = (ogma_uint32) desc_ring_p->head_idx + increment;
+
+ if ( sum >= desc_ring_p->param.entry_num) {
+ sum -= desc_ring_p->param.entry_num;
+ }
+
+ desc_ring_p->head_idx = ( ogma_uint16)sum;
+
+ if ( desc_ring_p->head_idx == desc_ring_p->tail_idx) {
+ desc_ring_p->full_flag = OGMA_TRUE;
+ }
+
+}
+
+STATIC void ogma_inc_desc_tail_idx (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 increment)
+{
+ ogma_uint32 sum;
+
+ if ( ( desc_ring_p->head_idx >= desc_ring_p->tail_idx) &&
+ ( !desc_ring_p->full_flag) ) {
+ pfdep_assert( increment <=
+ ( desc_ring_p->head_idx -
+ desc_ring_p->tail_idx) );
+ } else {
+ pfdep_assert( increment <=
+ ( desc_ring_p->param.entry_num +
+ desc_ring_p->head_idx -
+ desc_ring_p->tail_idx) );
+ }
+
+ sum = (ogma_uint32) desc_ring_p->tail_idx + increment;
+
+ if ( sum >= desc_ring_p->param.entry_num) {
+ sum -= desc_ring_p->param.entry_num;
+ }
+
+ desc_ring_p->tail_idx = ( ogma_uint16)sum;
+
+ desc_ring_p->full_flag = OGMA_FALSE;
+}
+
+
+STATIC ogma_uint16 ogma_get_tx_avail_num_sub (
+ ogma_ctrl_t *ctrl_p,
+ const ogma_desc_ring_t *desc_ring_p
+ )
+{
+ ogma_uint16 tx_avail_num;
+
+ if ( desc_ring_p->full_flag) {
+
+ tx_avail_num = 0;
+
+ } else if ( desc_ring_p->tail_idx > desc_ring_p->head_idx) {
+
+ tx_avail_num = desc_ring_p->tail_idx - desc_ring_p->head_idx;
+
+ } else {
+
+ tx_avail_num =
+ desc_ring_p->param.entry_num +
+ desc_ring_p->tail_idx -
+ desc_ring_p->head_idx;
+ }
+
+ return tx_avail_num;
+}
+
+STATIC ogma_uint16 ogma_get_tx_done_num_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+ ogma_uint32 value;
+
+ value = ogma_read_reg ( ctrl_p,
+ tx_done_pkt_cnt_reg_addr[desc_ring_p->ring_id] );
+
+ desc_ring_p->tx_done_num += value;
+
+ return desc_ring_p->tx_done_num;
+}
+
+
+ogma_err_t ogma_start_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+ pfdep_err_t pfdep_err;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ if ( desc_ring_p->running_flag) {
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return OGMA_ERR_BUSY;
+ }
+
+ if ( desc_ring_p->rx_desc_ring_flag) {
+
+ ogma_write_reg ( ctrl_p,
+ desc_ring_irq_inten_set_reg_addr[ring_id],
+ OGMA_CH_IRQ_REG_RCV);
+
+ ogma_write_reg ( ctrl_p,
+ int_pkt_cnt_reg_addr[ring_id],
+ 1);
+ }
+
+ if ( desc_ring_p->tx_desc_ring_flag) {
+
+
+ value = OGMA_CH_IRQ_REG_EMPTY;
+
+
+ ogma_write_reg ( ctrl_p,
+ desc_ring_irq_inten_set_reg_addr[ring_id],
+ value);
+
+ ogma_write_reg ( ctrl_p,
+ int_pkt_cnt_reg_addr[ring_id],
+ 1);
+
+ }
+
+ desc_ring_p->running_flag = OGMA_TRUE;
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ return ogma_err;
+}
+
+
+ogma_err_t ogma_stop_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+ pfdep_err_t pfdep_err;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ogma_is_pkt_desc_ring( &ctrl_p->desc_ring[ring_id] ) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ if ( !desc_ring_p->running_flag) {
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return OGMA_ERR_INVALID;
+ }
+
+ value = ( OGMA_CH_IRQ_REG_RCV |
+ OGMA_CH_IRQ_REG_EMPTY |
+ OGMA_CH_IRQ_REG_SND);
+
+ ogma_write_reg ( ctrl_p,
+ desc_ring_irq_inten_clr_reg_addr[ring_id],
+ value);
+
+ desc_ring_p->running_flag = OGMA_FALSE;
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ return OGMA_ERR_OK;
+}
+
+ogma_uint16 ogma_get_rx_num (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+
+ ogma_uint32 result;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p = NULL;
+ ogma_desc_ring_id_t tmp_ring_id;
+
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+ pfdep_err_t pfdep_err;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_rx_num.\n"
+ "Please set valid argument.\n");
+ return 0;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_rx_num.\n"
+ "Please set valid argument.\n");
+ return 0;
+ }
+
+ tmp_ring_id = ring_id;
+
+ if (! ctrl_p->desc_ring[tmp_ring_id].rx_desc_ring_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_rx_num.\n"
+ "Please select rx packet desc ring or bulk desc ring.\n");
+ return 0;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[tmp_ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_rx_num.\n"
+ "Failed to get soft lock.\n");
+ return 0;
+ }
+
+ result = ogma_read_reg( ctrl_p, rx_pkt_cnt_reg_addr[tmp_ring_id]);
+
+ desc_ring_p->rx_num += result;
+
+ if ( desc_ring_p->rx_desc_ring_flag && ( result != 0) ) {
+ ogma_inc_desc_head_idx( ctrl_p, desc_ring_p, ( ogma_uint16)result);
+ }
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ return desc_ring_p->rx_num;
+}
+
+
+ogma_uint16 ogma_get_tx_avail_num (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+
+ ogma_uint16 result;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_id_t tmp_ring_id;
+ ogma_desc_ring_t *desc_ring_p = NULL;
+
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+ pfdep_err_t pfdep_err;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ||
+ ( !ctrl_p->desc_ring[ring_id].param.valid_flag) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_tx_avail_num.\n"
+ "Please select valid argument.\n");
+ return 0;
+ }
+
+ tmp_ring_id = ring_id;
+
+ if (! ctrl_p->desc_ring[tmp_ring_id].tx_desc_ring_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_tx_avail_num.\n"
+ "Please select tx packet desc ring or bulk desc ring.\n");
+ return 0;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[tmp_ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_tx_avail_num.\n"
+ "Failed to get soft lock.\n");
+ return 0;
+ }
+
+ if ( !desc_ring_p->running_flag) {
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_tx_avail_num.\n"
+ "Please select running desc ring.\n");
+ return 0;
+ }
+
+ result = ogma_get_tx_avail_num_sub( ctrl_p, desc_ring_p);
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return result;
+}
+
+ogma_err_t ogma_clean_tx_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+
+ pfdep_err_t pfdep_err;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].tx_desc_ring_flag) {
+ return OGMA_ERR_PARAM;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ ogma_clean_tx_desc_ring_sub(ctrl_p, desc_ring_p);
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return OGMA_ERR_OK;
+
+
+}
+
+ogma_err_t ogma_clean_rx_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+
+ pfdep_err_t pfdep_err;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].rx_desc_ring_flag) {
+ return OGMA_ERR_PARAM;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ ogma_clean_rx_desc_ring_sub(ctrl_p, desc_ring_p);
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_set_tx_pkt_data (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+ ogma_uint8 scat_num,
+ const ogma_frag_info_t *scat_info_p,
+ pfdep_pkt_handle_t pkt_handle
+ )
+{
+ ogma_uint i;
+ ogma_uint16 tx_avail_num;
+ ogma_uint32 sum_len = 0;
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+
+ pfdep_err_t pfdep_err;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG, "%s call.\n", __func__);
+
+ if ( ( ctrl_p == NULL) ||
+ ( tx_pkt_ctrl_p == NULL) ||
+ ( scat_info_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].tx_desc_ring_flag) {
+ return OGMA_ERR_PARAM;
+ }
+
+ {
+ if ( !ctrl_p->param.use_gmac_flag ||
+ ( tx_pkt_ctrl_p->target_desc_ring_id != OGMA_DESC_RING_ID_GMAC) ) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+
+ if ( tx_pkt_ctrl_p->tcp_seg_offload_flag &&
+ ( !tx_pkt_ctrl_p->cksum_offload_flag) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( tx_pkt_ctrl_p->tcp_seg_offload_flag) {
+
+ if ( tx_pkt_ctrl_p->tcp_seg_len == 0) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( ctrl_p->param.use_jumbo_pkt_flag) {
+ if (tx_pkt_ctrl_p->tcp_seg_len > OGMA_TCP_JUMBO_SEG_LEN_MAX) {
+ return OGMA_ERR_DATA;
+ }
+ } else {
+ if (tx_pkt_ctrl_p->tcp_seg_len > OGMA_TCP_SEG_LEN_MAX) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+ } else {
+ if ( tx_pkt_ctrl_p->tcp_seg_len != 0) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+
+ if ( scat_num == 0) {
+ return OGMA_ERR_RANGE;
+ }
+
+ for ( i = 0; i < scat_num; i++) {
+ if ( ( scat_info_p[i].len == 0) ||
+ ( scat_info_p[i].len > 0xffffU) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_set_tx_pkt_data.\n"
+ "Pleas check scat_info_p[%u].len.\n",
+ i);
+ return OGMA_ERR_DATA;
+ }
+ sum_len += scat_info_p[i].len;
+ }
+
+ if ( !tx_pkt_ctrl_p->tcp_seg_offload_flag) {
+
+ if ( ctrl_p->param.use_jumbo_pkt_flag) {
+ if ( sum_len > OGMA_MAX_TX_JUMBO_PKT_LEN) {
+ return OGMA_ERR_DATA;
+ }
+ } else {
+ if ( sum_len > OGMA_MAX_TX_PKT_LEN) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ if ( !desc_ring_p->running_flag) {
+ ogma_err = OGMA_ERR_NOTAVAIL;
+ goto end;
+ }
+
+ tx_avail_num = ogma_get_tx_avail_num_sub( ctrl_p, desc_ring_p);
+
+ if ( scat_num > tx_avail_num ) {
+ ogma_err = OGMA_ERR_BUSY;
+ goto end;
+ }
+
+ for ( i = 0; i < scat_num; i++) {
+
+
+ ogma_set_tx_desc_entry(
+ ctrl_p,
+ desc_ring_p,
+ desc_ring_p->head_idx,
+ tx_pkt_ctrl_p,
+ ( i == 0),
+ ( i == ( scat_num - 1U) ),
+ OGMA_TRUE,
+ &scat_info_p[i],
+ pkt_handle);
+ ogma_inc_desc_head_idx( ctrl_p, desc_ring_p, 1);
+ }
+
+ pfdep_write_mem_barrier();
+
+ ogma_write_reg( ctrl_p,
+ tx_pkt_cnt_reg_addr[ring_id],
+ (ogma_uint32)1);
+
+end:
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ return ogma_err;
+}
+
+ogma_err_t ogma_get_rx_pkt_data (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_rx_pkt_info_t *rx_pkt_info_p,
+ ogma_frag_info_t *frag_info_p,
+ ogma_uint16 *len_p,
+ pfdep_pkt_handle_t *pkt_handle_p
+ )
+{
+
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+ ogma_frag_info_t tmp_frag_info;
+
+ pfdep_err_t pfdep_err;
+ pfdep_pkt_handle_t tmp_pkt_handle;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG, "%s call.\n", __func__);
+
+ if ( ( ctrl_p == NULL) ||
+ ( rx_pkt_info_p == NULL) ||
+ ( frag_info_p == NULL) ||
+ ( len_p == NULL) ||
+ ( pkt_handle_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].rx_desc_ring_flag) {
+ return OGMA_ERR_PARAM;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ if ( desc_ring_p->rx_num == 0 ) {
+ ogma_err = OGMA_ERR_INVALID;
+ goto end;
+ }
+
+ tmp_frag_info.len = ctrl_p->rx_pkt_buf_len;
+
+ pfdep_read_mem_barrier();
+
+ if ( ( pfdep_err = pfdep_alloc_pkt_buf (
+ ctrl_p->dev_handle,
+ tmp_frag_info.len,
+ &tmp_frag_info.addr,
+ &tmp_frag_info.phys_addr,
+ &tmp_pkt_handle) ) != PFDEP_ERR_OK) {
+ ogma_set_rx_desc_entry( ctrl_p,
+ desc_ring_p,
+ desc_ring_p->tail_idx,
+ &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
+ desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
+ ogma_err = OGMA_ERR_ALLOC;
+
+ } else {
+
+ ogma_get_rx_desc_entry( ctrl_p,
+ desc_ring_p,
+ desc_ring_p->tail_idx,
+ rx_pkt_info_p,
+ frag_info_p,
+ len_p,
+ pkt_handle_p);
+
+
+ ogma_set_rx_desc_entry( ctrl_p,
+ desc_ring_p,
+ desc_ring_p->tail_idx,
+ &tmp_frag_info,
+ tmp_pkt_handle);
+ }
+
+ ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
+
+ --desc_ring_p->rx_num;
+
+end:
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ return ogma_err;
+}
+
+ogma_err_t ogma_set_irq_coalesce_param (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint16 int_pktcnt,
+ ogma_bool int_tmr_unit_ms_flag,
+ ogma_uint16 int_tmr_cnt
+ )
+{
+
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( int_pktcnt > OGMA_INT_PKTCNT_MAX) {
+ return OGMA_ERR_RANGE;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ogma_is_pkt_desc_ring( &ctrl_p->desc_ring[ring_id]) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ ogma_write_reg( ctrl_p,
+ int_pkt_cnt_reg_addr[ring_id],
+ int_pktcnt);
+
+ ogma_write_reg( ctrl_p,
+ int_tmr_reg_addr[ring_id],
+ ( ( ( ( ogma_uint32)int_tmr_unit_ms_flag) << 31) |
+ int_tmr_cnt) );
+
+ return ogma_err;
+
+}
new file mode 100644
@@ -0,0 +1,111 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_DESC_RING_ACCESS_INTERNAL_H
+#define OGMA_DESC_RING_ACCESS_INTERNAL_H
+
+#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
+#include "ogma_internal.h"
+
+#define OGMA_TX_PKT_DESC_RING_OWN_FIELD (31)
+#define OGMA_TX_PKT_DESC_RING_LD_FIELD (30)
+#define OGMA_TX_PKT_DESC_RING_DRID_FIELD (24)
+#define OGMA_TX_PKT_DESC_RING_PT_FIELD (21)
+#define OGMA_TX_PKT_DESC_RING_TDRID_FIELD (16)
+#define OGMA_TX_PKT_DESC_RING_FS_FIELD (9)
+#define OGMA_TX_PKT_DESC_RING_LS_FIELD (8)
+#define OGMA_TX_PKT_DESC_RING_CO_FIELD (7)
+#define OGMA_TX_PKT_DESC_RING_SO_FIELD (6)
+#define OGMA_TX_PKT_DESC_RING_USRKEY_FIELD (5)
+#define OGMA_TX_PKT_DESC_RING_TRS_FIELD (4)
+
+#define OGMA_RX_PKT_DESC_RING_OWN_FIELD (31)
+#define OGMA_RX_PKT_DESC_RING_LD_FIELD (30)
+#define OGMA_RX_PKT_DESC_RING_SDRID_FIELD (24)
+#define OGMA_RX_PKT_DESC_RING_FR_FIELD (23)
+#define OGMA_RX_PKT_DESC_RING_ER_FIELD (21)
+#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD (16)
+#define OGMA_RX_PKT_DESC_RING_TDRID_FIELD (12)
+#define OGMA_RX_PKT_DESC_RING_FS_FIELD (9)
+#define OGMA_RX_PKT_DESC_RING_LS_FIELD (8)
+#define OGMA_RX_PKT_DESC_RING_CO_FIELD (6)
+
+#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK (0x3)
+
+#define OGMA_MAX_TX_PKT_LEN 1518U
+#define OGMA_MAX_TX_JUMBO_PKT_LEN 9018U
+
+typedef struct ogma_tx_desc_entry_s ogma_tx_desc_entry_t;
+typedef struct ogma_rx_desc_entry_s ogma_rx_desc_entry_t;
+
+struct ogma_tx_desc_entry_s{
+
+ ogma_uint32 attr;
+
+ ogma_uint32 data_buf_addr_upper;
+
+ ogma_uint32 data_buf_addr_lower;
+
+ ogma_uint32 buf_len_info;
+};
+
+struct ogma_rx_desc_entry_s{
+
+ ogma_uint32 attr;
+
+ ogma_uint32 data_buf_addr_upper;
+
+ ogma_uint32 data_buf_addr_lower;
+
+ ogma_uint32 buf_len_info;
+};
+
+static __inline ogma_bool ogma_is_pkt_desc_ring (
+ const ogma_desc_ring_t *desc_ring_p
+ )
+{
+ return ( desc_ring_p->rx_desc_ring_flag ||
+ desc_ring_p->tx_desc_ring_flag);
+}
+
+static __inline ogma_uint32 ogma_get_desc_ring_attr (
+ const ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx
+ )
+{
+ ogma_uint32 *addr =
+ (ogma_uint32 *)
+ ((pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+ desc_ring_p->desc_entry_len * idx);
+
+ return *addr;
+}
+
+
+
+static __inline void ogma_check_desc_own_sanity (
+ ogma_ctrl_t *ctrl_p,
+ const ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ ogma_uint expected_own)
+{
+ ogma_uint32 tmp;
+ ( void)ctrl_p; /* Suppress compiler warning */
+
+ tmp = ogma_get_desc_ring_attr(desc_ring_p, idx);
+ pfdep_assert( ( tmp >> 31) == expected_own);
+}
+
+#endif /* OGMA_DESC_RING_ACCESS_INTERNAL_H */
new file mode 100644
@@ -0,0 +1,1454 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_config.h"
+
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+
+
+/**********************************************************************
+ * Constant definitions
+ **********************************************************************/
+
+/**
+ * Clock range index for F_GMAC4MT::GAR::CR field.
+ */
+#if (OGMA_CONFIG_GMAC_CLK_HZ < 35 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_25_35_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 60 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_35_60_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 100 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_60_100_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 150 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_100_150_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 250 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_150_250_MHZ
+#else
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_250_300_MHZ
+#endif
+
+
+/**********************************************************************
+ * Local function declarations
+ **********************************************************************/
+static void ogma_set_phy_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr,
+ ogma_uint16 value
+ );
+
+static ogma_uint16 ogma_get_phy_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr
+ );
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p);
+#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
+static void ogma_set_phy_target_mmd_reg_addr (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ );
+
+static void ogma_set_phy_mmd_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr,
+ ogma_uint16 value
+ );
+
+static ogma_uint16 ogma_get_phy_mmd_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ );
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+ogma_err_t ogma_start_gmac (
+ ogma_handle_t ogma_handle,
+ ogma_bool rx_flag,
+ ogma_bool tx_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ pfdep_err_t pfdep_err;
+ ogma_err_t ogma_err;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ctrl_p->gmac_mode_valid_flag) {
+ return OGMA_ERR_INVALID;
+ }
+
+ if ( ( !rx_flag) && ( !tx_flag) ) {
+ return OGMA_ERR_OK;
+ }
+
+ if ( ctrl_p->gmac_rx_running_flag &&
+ ctrl_p->gmac_tx_running_flag) {
+ return OGMA_ERR_OK;
+ }
+
+
+ if ( ( rx_flag && ctrl_p->gmac_rx_running_flag) &&
+ !tx_flag) {
+ return OGMA_ERR_OK;
+ }
+
+ if ( ( tx_flag && ctrl_p->gmac_tx_running_flag) &&
+ !rx_flag ) {
+ return OGMA_ERR_OK;
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "%s call.\n", __func__);
+
+ if ( (! ctrl_p->gmac_rx_running_flag) &&
+ (! ctrl_p->gmac_tx_running_flag) ) {
+
+ /* Initializes F_GMAC4MT */
+ if ( ctrl_p->gmac_mode.link_speed ==
+ OGMA_PHY_LINK_SPEED_1G) {
+ /* Writes 0 to FGMAC4 MCR */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_MCR,
+ 0);
+ } else {
+ /* Writes PS bit to FGMAC4 MCR */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_MCR,
+ OGMA_GMAC_MCR_10M_HALF);/* 10M half Reset */
+ }
+
+ /* F_GMAC4MT soft reset*/
+ if ( ( ogma_err = ogma_softreset_gmac( ctrl_p)) != OGMA_ERR_OK) {
+ return ogma_err;
+ }
+
+ /* MAC desc soft reset */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_DESC_SOFT_RST,
+ OGMA_MAC_DESC_SOFT_RST_SOFT_RST);
+
+ /* Wait MAC desc soft reset */
+ pfdep_err = pfdep_msleep( 1);
+
+ if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_start_gmac.\n");
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "Wait for MAC desc soft reset error.\n");
+
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ /* Check MAC desc soft reset done */
+ if ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_SOFT_RST) &
+ OGMA_MAC_DESC_SOFT_RST_SOFT_RST) != 0) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "ogma_start_gmac():MAC desc soft reset timeout. Try Again.\n");
+
+ return OGMA_ERR_AGAIN;
+ }
+
+ /* MAC desc init */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_DESC_INIT,
+ OGMA_MAC_DESC_INIT_REG_INIT);
+
+ /* Wait MAC desc init done */
+ pfdep_err = pfdep_msleep( 1);
+
+ if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_start_gmac().\n");
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "Wait for MAC desc init done error.\n");
+
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ /* Check MAC desc init done */
+ if ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT) &
+ OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "ogma_start_gmac():MAC desc init timeout. Try Again.\n");
+
+ return OGMA_ERR_AGAIN;
+ }
+
+ /* set BMR */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_BMR,
+ OGMA_GMAC_BMR_REG_COMMON);
+ /* set RDLAR */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_RDLAR,
+ OGMA_GMAC_RDLAR_REG_COMMON);
+ /* set TDLAR*/
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_TDLAR,
+ OGMA_GMAC_TDLAR_REG_COMMON);
+ /* set MFFR*/
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_MFFR,
+ 0x80000001UL);
+
+ /* calc MCR setting val */
+ value = ( ctrl_p->gmac_mode.half_duplex_flag ?
+ OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON :
+ OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON);
+
+ if ( ctrl_p->gmac_mode.link_speed != OGMA_PHY_LINK_SPEED_1G) {
+ value |= OGMA_GMAC_MCR_REG_PS;
+ }
+
+ if ( ( ctrl_p->param.gmac_config.phy_interface !=
+ OGMA_PHY_INTERFACE_GMII ) &&
+ ( ctrl_p->gmac_mode.link_speed == OGMA_PHY_LINK_SPEED_100M) ) {
+ value |= OGMA_GMAC_MCR_REG_FES;
+ }
+ /* set CST bit */
+ value |= OGMA_GMAC_MCR_REG_CST;
+
+ /* set JE bit */
+ value |= OGMA_GMAC_MCR_REG_JE;
+
+ if ( ctrl_p->param.gmac_config.phy_interface ==
+ OGMA_PHY_INTERFACE_RGMII) {
+ /* set ignore in-band-status watch option. force tx clk out. */
+ value |= 0x40000000U;
+ }
+
+ /* set MCR */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_MCR,
+ value);
+
+ if ( ctrl_p->gmac_mode.flow_ctrl_enable_flag) {
+ /* Set Flow Control Threshold */
+ value =
+ ( ctrl_p->gmac_mode.flow_ctrl_stop_threshold << 16) |
+ ctrl_p->gmac_mode.flow_ctrl_start_threshold;
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_FLOW_TH,
+ value);
+ /* Set Flow Control Threshold F_GMAC4MT*/
+ value =
+ ( ctrl_p->gmac_mode.pause_time << 16) |
+ OGMA_GMAC_FCR_REG_RFE |
+ OGMA_GMAC_FCR_REG_TFE;
+
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_FCR,
+ value);
+ }
+
+ }
+
+ if ( ( rx_flag && (! ctrl_p->gmac_rx_running_flag) ) ||
+ ( tx_flag && (! ctrl_p->gmac_tx_running_flag) )
+ ) {
+ /* Read F_GMAC4MT OMR*/
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_OMR);
+
+ if ( rx_flag && (! ctrl_p->gmac_rx_running_flag) ) {
+ value |= OGMA_GMAC_OMR_REG_SR;
+ ctrl_p->gmac_rx_running_flag = OGMA_TRUE;
+ }
+
+ if ( tx_flag && (! ctrl_p->gmac_tx_running_flag) ) {
+ value |= OGMA_GMAC_OMR_REG_ST;
+ ctrl_p->gmac_tx_running_flag = OGMA_TRUE;
+ }
+
+ /* set OMR*/
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_OMR,
+ value);
+
+ }
+
+ return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_stop_gmac (
+ ogma_handle_t ogma_handle,
+ ogma_bool rx_flag,
+ ogma_bool tx_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+
+ if ( ( !rx_flag) && ( !tx_flag) ) {
+ return OGMA_ERR_OK;
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "%s call.\n", __func__);
+
+ if ( ( rx_flag && ctrl_p->gmac_rx_running_flag) ||
+ ( tx_flag && ctrl_p->gmac_tx_running_flag) ) {
+ /* Read F_GMAC4MT OMR*/
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_OMR);
+
+ if ( rx_flag && ctrl_p->gmac_rx_running_flag) {
+ value &= (~OGMA_GMAC_OMR_REG_SR);
+ ctrl_p->gmac_rx_running_flag = OGMA_FALSE;
+ }
+
+ if ( tx_flag && ctrl_p->gmac_tx_running_flag) {
+ value &= (~OGMA_GMAC_OMR_REG_ST);
+ ctrl_p->gmac_tx_running_flag = OGMA_FALSE;
+ }
+
+ /* set F_GMAC4MT OMR*/
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_OMR,
+ value);
+ }
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+ ogma_dump_gmac_stat (ctrl_p);
+#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
+
+ return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_set_gmac_mode (
+ ogma_handle_t ogma_handle,
+ const ogma_gmac_mode_t *gmac_mode_p
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( gmac_mode_p == NULL) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( ( ctrl_p->gmac_rx_running_flag) ||
+ ( ctrl_p->gmac_tx_running_flag) ) {
+ return OGMA_ERR_BUSY;
+ }
+
+ if ( ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_1G ) &&
+ ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_100M) &&
+ ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_10M ) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( ( gmac_mode_p->link_speed == OGMA_PHY_LINK_SPEED_1G) &&
+ ( gmac_mode_p->half_duplex_flag) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( gmac_mode_p->half_duplex_flag &&
+ gmac_mode_p->flow_ctrl_enable_flag) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( gmac_mode_p->flow_ctrl_enable_flag) {
+
+ if ( ( gmac_mode_p->flow_ctrl_start_threshold == 0) ||
+ ( gmac_mode_p->flow_ctrl_start_threshold >
+ OGMA_FLOW_CTRL_START_THRESHOLD_MAX) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( ( gmac_mode_p->flow_ctrl_stop_threshold <
+ gmac_mode_p->flow_ctrl_start_threshold) ||
+ ( gmac_mode_p->flow_ctrl_stop_threshold >
+ OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( gmac_mode_p->pause_time < OGMA_FLOW_CTRL_PAUSE_TIME_MIN) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "%s call.\n", __func__);
+
+ pfdep_memcpy( ( void *)&ctrl_p->gmac_mode,
+ ( void *)gmac_mode_p,
+ sizeof( ogma_gmac_mode_t) );
+
+ ctrl_p->gmac_mode_valid_flag = OGMA_TRUE;
+
+
+ return OGMA_ERR_OK;
+
+}
+
+static void ogma_set_phy_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr,
+ ogma_uint16 value
+ )
+{
+
+ ogma_uint32 cmd;
+
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_GDR,
+ value);
+
+ cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) |
+ ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) |
+ ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) |
+ OGMA_GMAC_GAR_REG_GW |
+ OGMA_GMAC_GAR_REG_GB);
+
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_GAR,
+ cmd);
+
+ while ( ( ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GAR) &
+ OGMA_GMAC_GAR_REG_GB)
+ != 0) {
+ ;
+ }
+}
+
+void ogma_set_phy_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr,
+ ogma_uint16 value
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if (( ctrl_p == NULL)
+ || ( !ctrl_p->param.use_gmac_flag)
+ || ( phy_addr >= 32)
+ || ( reg_addr >= 32) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_set_phy_reg.\nPlease set valid argument.\n");
+ return;
+ }
+
+ ogma_set_phy_reg_sub( ctrl_p, phy_addr, reg_addr, value);
+
+}
+
+static ogma_uint16 ogma_get_phy_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr
+ )
+{
+
+ ogma_uint32 cmd;
+
+ cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) |
+ ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) |
+ ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) |
+ OGMA_GMAC_GAR_REG_GB);
+
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_GAR,
+ cmd);
+
+ while ( ( ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GAR) &
+ OGMA_GMAC_GAR_REG_GB)
+ != 0) {
+ ;
+ }
+ return (ogma_uint16)ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GDR);
+
+}
+
+ogma_uint16 ogma_get_phy_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr
+ )
+{
+ ogma_uint16 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL)
+ || ( !ctrl_p->param.use_gmac_flag)
+ || ( phy_addr >= 32)
+ || ( reg_addr >= 32) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_phy_reg.\nPlease set valid argument.\n");
+ return 0;
+ }
+
+ value = ogma_get_phy_reg_sub(ctrl_p, phy_addr, reg_addr);
+
+
+ return value;
+}
+
+#if ( defined(OGMA_CONFIG_USE_READ_GMAC_STAT) || defined(OGMA_CONFIG_USE_DUMP_GMAC_STAT) )
+static const struct {
+ ogma_uint32 addr;
+ ogma_char *name_p;
+} ogma_gmac_mmc_reg_info[] = {
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_RX , "MMC_INTR_RX"},
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_TX , "MMC_INTR_TX"},
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX , "MMC_INTR_MASK_RX"},
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX , "MMC_INTR_MASK_TX"},
+ {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB , "TXOCTETCOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB , "TXFRAMECOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G , "TXBROADCASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G , "TXMULTICASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_TX64OCTETS_GB , "TX64OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB , "TX65TO127OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB , "TX128TO255OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB , "TX256TO511OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB, "TX512TO1023OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB, "TX1024TOMAXOCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB , "TXUNICASTFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB, "TXMULTICASTFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB, "TXBROADCASTFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR , "TXUNDERFLOWERROR"},
+ {OGMA_GMAC_REG_ADDR_TXSINGLECOL_G , "TXSINGLECOL_G"},
+ {OGMA_GMAC_REG_ADDR_TXMULTICOL_G , "TXMULTICOL_G"},
+ {OGMA_GMAC_REG_ADDR_TXDEFERRED , "TXDEFERRED"},
+ {OGMA_GMAC_REG_ADDR_TXLATECOL , "TXLATECOL"},
+ {OGMA_GMAC_REG_ADDR_TXEXESSCOL , "TXEXESSCOL"},
+ {OGMA_GMAC_REG_ADDR_TXCARRIERERRROR , "TXCARRIERERRROR"},
+ {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G , "TXOCTETCOUNT_G"},
+ {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G , "TXFRAMECOUNT_G"},
+ {OGMA_GMAC_REG_ADDR_TXEXECESSDEF , "TXEXECESSDEF"},
+ {OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES , "TXPAUSEFRAMES"},
+ {OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G , "TXVLANFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB , "RXFRAMECOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB , "RXOCTETCOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G , "RXOCTETCOUNT_G"},
+ {OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G , "RXBROADCASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G , "RXMULTICASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXCRCERROR , "RXCRCERROR"},
+ {OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR , "RXALLIGNMENTERROR"},
+ {OGMA_GMAC_REG_ADDR_RXRUNTERROR , "RXRUNTERROR"},
+ {OGMA_GMAC_REG_ADDR_RXJABBERERROR , "RXJABBERERROR"},
+ {OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G , "RXUNDERSIZE_G"},
+ {OGMA_GMAC_REG_ADDR_RXOVERSIZE_G , "RXOVERSIZE_G"},
+ {OGMA_GMAC_REG_ADDR_RX64OCTETS_GB , "RX64OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB , "RX65TO127OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB , "RX128TO255OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB , "RX256TO511OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB, "RX512TO1023OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB, "RX1024TOMAXOCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G , "RXUNICASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXLENGTHERROR , "RXLENGTHERROR"},
+ {OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE , "RXOUTOFRANGETYPE"},
+ {OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES , "RXPAUSEFRAMES"},
+ {OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW , "RXFIFOOVERFLOW"},
+ {OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB , "RXVLANFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR , "RXWATCHDOGERROR"},
+ {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX, "MMC_IPC_INTR_MASK_RX"},
+ {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX , "MMC_IPC_INTR_RX"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS , "RXIPV4_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS , "RXIPV4_HDRERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS , "RXIPV4_NOPAY_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS , "RXIPV4_FRAG_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS , "RXIPV4_UDSBL_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS , "RXIPV6_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS , "RXIPV6_HDRERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS , "RXIPV6_NOPAY_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS , "RXUDP_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS , "RXUDP_ERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS , "RXTCP_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS , "RXTCP_ERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS , "RXICMP_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS , "RXICMP_ERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS , "RXIPV4_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS, "RXIPV4_HDRERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS , "RXIPV4_NOPAY_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS , "RXIPV4_FRAG_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS , "RXIPV4_UDSBL_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS , "RXIPV6_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS, "RXIPV6_HDRERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS , "RXIPV6_NOPAY_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS , "RXUDP_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS , "RXUDP_ERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS , "RXTCP_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS , "RXTCP_ERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS , "RXICMP_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS , "RXICMP_ERR_OCTETS"}
+};
+#endif /* ( defined(OGMA_CONFIG_USE_READ_GMAC_STAT) || defined(OGMA_CONFIG_USE_DUMP_GMAC_STAT) ) */
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p)
+{
+
+ ogma_uint i;
+
+ pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+ "Dumping GMAC statistics registers(MMC registers):\n");
+
+ for (i = 0;
+ i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0]);
+ i++) {
+ pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+ " %s => 0x%08x\n",
+ ogma_gmac_mmc_reg_info[i].name_p,
+ ( unsigned long)ogma_get_mac_reg(ctrl_p,
+ ogma_gmac_mmc_reg_info[i].addr));
+ }
+
+
+ /* Reset all counters. */
+ ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
+
+
+}
+
+#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
+
+ogma_err_t ogma_get_gmac_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool *valid_flag_p,
+ ogma_gmac_mode_t *gmac_mode_p,
+ ogma_bool *rx_running_flag_p,
+ ogma_bool *tx_running_flag_p
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( valid_flag_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ( ctrl_p == NULL) ||
+ ( gmac_mode_p == NULL) ||
+ ( rx_running_flag_p == NULL) ||
+ ( tx_running_flag_p == NULL) ) {
+ *valid_flag_p = OGMA_FALSE;
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ *valid_flag_p = OGMA_FALSE;
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+
+ *valid_flag_p = ctrl_p->gmac_mode_valid_flag;
+
+ *rx_running_flag_p = ctrl_p->gmac_rx_running_flag;
+ *tx_running_flag_p = ctrl_p->gmac_tx_running_flag;
+
+ pfdep_memcpy( ( void *)gmac_mode_p,
+ ( const void *)&ctrl_p->gmac_mode,
+ sizeof( ogma_gmac_mode_t) );
+
+
+ return OGMA_ERR_OK;
+
+}
+
+static void ogma_set_phy_target_mmd_reg_addr (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ )
+{
+ ogma_uint32 cmd;
+
+ /* set MMD ADDR */
+ cmd = ( ogma_uint32)dev_addr;
+
+ /*set command to MMD access control register */
+ ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd);
+
+ /* set MMD access address data register Write reg_addr */
+ ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, reg_addr);
+
+ /* write value to MMD ADDR */
+ cmd = ( (1U << 14) | dev_addr);
+
+ /* set command to MMD access control register */
+ ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd);
+}
+
+static void ogma_set_phy_mmd_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr,
+ ogma_uint16 value
+ )
+{
+ /* set target mmd reg_addr */
+ ogma_set_phy_target_mmd_reg_addr( ctrl_p,
+ phy_addr,
+ dev_addr,
+ reg_addr);
+
+ /* Write value to MMD access address data register */
+ ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, value);
+
+}
+
+static ogma_uint16 ogma_get_phy_mmd_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ )
+{
+ /* set target mmd reg_addr */
+ ogma_set_phy_target_mmd_reg_addr( ctrl_p,
+ phy_addr,
+ dev_addr,
+ reg_addr);
+
+ /* Read value for MMD access address data register */
+ return ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD);
+}
+
+ogma_err_t ogma_set_gmac_lpictrl_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* set value tp LSIPCR Register */
+ ogma_set_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_LPICSR, value);
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_get_gmac_lpictrl_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( value_p == NULL) ){
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Read LSIPCR Register */
+ *value_p = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_LPICSR);
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_set_gmac_lpitimer_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint16 ls_timer_ms,
+ ogma_uint16 tw_timer_ms
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ls_timer_ms > 1024U) {
+ return OGMA_ERR_RANGE;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* make LPICTR value*/
+ value = ( ( ( ogma_uint32)ls_timer_ms << OGMA_GMAC_LPITCR_REG_LIT) |
+ ( tw_timer_ms << OGMA_GMAC_LPITCR_REG_TWT) );
+
+ /* Write timer value to LSIPCR Register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_LPITCR,
+ value);
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_get_gmac_lpitimer_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint16 *ls_timer_ms_p,
+ ogma_uint16 *tw_timer_ms_p
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ls_timer_ms_p == NULL) ||
+ ( tw_timer_ms_p == NULL) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Read timer value for LSIPCR Register */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_LPITCR);
+
+ /* make ls_timer_ms value*/
+ *ls_timer_ms_p = ( ogma_uint16)( ( value >> OGMA_GMAC_LPITCR_REG_LIT) &
+ OGMA_GMAC_LPITCR_REG_MASK_LIT);
+
+ /* make tw_timer_ms value*/
+ *tw_timer_ms_p = ( ogma_uint16)( ( value >> OGMA_GMAC_LPITCR_REG_TWT) &
+ OGMA_GMAC_LPITCR_REG_MASK_TWT);
+
+
+ return OGMA_ERR_OK;
+}
+
+void ogma_set_phy_mmd_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr,
+ ogma_uint16 value
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return;
+ }
+
+ if ( ( phy_addr > 31U) ||
+ ( dev_addr > 31U) ) {
+ return;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return;
+ }
+
+ ogma_set_phy_mmd_reg_sub ( ctrl_p,
+ phy_addr,
+ dev_addr,
+ reg_addr,
+ value);
+
+
+ return;
+}
+
+ogma_uint16 ogma_get_phy_mmd_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ )
+{
+ ogma_uint16 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return 0;
+ }
+
+ if ( ( phy_addr > 31U) ||
+ ( dev_addr > 31U) ) {
+ return 0;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return 0;
+ }
+
+ value = ogma_get_phy_mmd_reg_sub ( ctrl_p,
+ phy_addr,
+ dev_addr,
+ reg_addr);
+
+
+ return value;
+}
+
+ogma_err_t ogma_get_phy_link_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_phy_link_status_t *phy_link_status_p
+ )
+{
+ ogma_uint32 value, tmp, exp;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( phy_link_status_p == NULL) ){
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( phy_addr >= 32) {
+ return OGMA_ERR_RANGE;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ pfdep_memset( phy_link_status_p, 0, sizeof( ogma_phy_link_status_t) );
+
+ /* Read PHY CONTROL Register */
+ tmp = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_CONTROL);
+
+ /* Read PHY STATUS Register */
+ value = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_STATUS);
+
+ /* check latched_link_down_flag */
+ if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) == 0) {
+ phy_link_status_p->latched_link_down_flag = OGMA_TRUE;
+
+ /* Read PHY STATUS Register */
+ value = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_STATUS);
+
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "CONTROL Register value %08x\n", tmp);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "PHY STATUS register value %08x\n", value);
+
+ /* Check Current Link Status */
+ if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) != 0 ) {
+ phy_link_status_p->up_flag = OGMA_TRUE;
+ }
+
+ /* check Auto-Negotiation Enable */
+ if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE) ) != 0) &&
+ ( ( value & ( 1U << OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY) ) != 0) ) {
+ phy_link_status_p->auto_nego_enable_flag = OGMA_TRUE;
+ }
+
+ /* Check Current Autonegotiation Complete Status */
+ if ( phy_link_status_p->up_flag &&
+ phy_link_status_p->auto_nego_enable_flag &&
+ ( ( value & ( 1U << OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP) ) != 0) ) {
+ phy_link_status_p->auto_nego_complete_flag = OGMA_TRUE;
+ }
+
+ /* start Check Current Link Speed */
+ if ( phy_link_status_p->up_flag) {
+
+ if ( phy_link_status_p->auto_nego_enable_flag == OGMA_FALSE) {
+
+ /* Speed check */
+ if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB) ) == 0) &&
+ ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB) ) != 0) ) {
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
+
+ } else if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB) ) != 0) &&
+ ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB) ) == 0) ) {
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
+
+ } else {
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
+ }
+
+ /* Duplex check */
+ if ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_DUPLEX_MODE) ) == 0) {
+
+ phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+ }
+
+ } else if ( phy_link_status_p->auto_nego_complete_flag == OGMA_TRUE) {
+ /* case auto_nego_enable_flag TRUE && auto_nego_complete_flag TRUE */
+
+ /* Read MASTER-SLAVE Control Register */
+ value = ogma_get_phy_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL);
+
+ /* Read MASTER-SLAVE Status Register */
+ tmp = ogma_get_phy_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS);
+
+ /* Check Current Link Speed */
+ if ( ( ( value & ( 1U << OGMA_PHY_MSC_REG_1000BASE_FULL) ) != 0) &&
+ ( ( tmp & ( 1U << OGMA_PHY_MSS_REG_LP_1000BASE_FULL) ) != 0) ) {
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
+
+ } else if ( ( ( value & ( 1U << OGMA_PHY_MSC_REG_1000BASE_HALF) ) != 0) &&
+ ( ( tmp & ( 1U << OGMA_PHY_MSS_REG_LP_1000BASE_HALF) ) != 0) ) {
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
+
+ phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+
+ } else {
+
+ /* Read Auto-Negotiation Advertisement register */
+ value = ogma_get_phy_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY);
+
+ /* Read Auto-Negotiation Link Partner Base Page Ability register */
+ tmp = ogma_get_phy_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY);
+
+ value = ( ( ( value & tmp) >> OGMA_PHY_ANA_REG_TAF) &
+ OGMA_PHY_ANA_REG_TAF_MASK);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "TAF value %08x\n", value);
+
+ if ( value & OGMA_PHY_TAF_REG_100BASE_FULL) { /* 100M full */
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
+
+ } else if ( value & OGMA_PHY_TAF_REG_100BASE_HALF) { /* 100M half */
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
+
+ phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+
+ } else if ( value & OGMA_PHY_TAF_REG_10BASE_FULL) { /* 10M full */
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
+
+ } else { /* value = OGMA_PHY_TAF_REG_10BASE_HALF 10M Half */
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
+
+ phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+ }
+
+ }
+ }
+ } /* End Check Current Link Speed */
+
+ /* Check LPI Capable */
+ if ( phy_link_status_p->up_flag &&
+ phy_link_status_p->auto_nego_complete_flag &&
+ phy_link_status_p->link_speed != OGMA_PHY_LINK_SPEED_10M &&
+ phy_link_status_p->half_duplex_flag == OGMA_FALSE &&
+ ctrl_p->param.gmac_config.phy_interface != OGMA_PHY_INTERFACE_RMII) {
+
+ /* Read EEE advertisement register */
+ value = ogma_get_phy_mmd_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_DEV_ADDR_AUTO_NEGO,
+ OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE);
+
+ /* Read EEE link partner ability register */
+ tmp = ogma_get_phy_mmd_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_DEV_ADDR_AUTO_NEGO,
+ OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY);
+
+ exp = ( ( phy_link_status_p->link_speed == OGMA_PHY_LINK_SPEED_1G) ?
+ OGMA_PHY_AUTO_NEGO_1000BASE_EEE:
+ OGMA_PHY_AUTO_NEGO_100BASE_EEE);
+
+ /* Check EEE Advertise and EEE LP Ability */
+ if ( ( value & tmp & exp) != 0 ) {
+ phy_link_status_p->lpi_capable_flag = OGMA_TRUE;
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "EEE advertisement register value %08x\n",
+ value);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "EEE link partner ability register value %08x\n",
+ tmp);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "EEE LPI EXP value %08x\n",
+ exp);
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->latched_link_down_flag %u\n",
+ phy_link_status_p->latched_link_down_flag);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->up_flag %u\n",
+ phy_link_status_p->up_flag);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->auto_nego_enable_flag %u\n",
+ phy_link_status_p->auto_nego_enable_flag);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->auto_nego_complete_flag %u\n",
+ phy_link_status_p->auto_nego_complete_flag);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->link_speed %u\n",
+ phy_link_status_p->link_speed);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->lpi_capable_flag %u\n",
+ phy_link_status_p->lpi_capable_flag);
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_gmac_int_sbd_regs_t gmac_int_sbd_regs = {0};
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return gmac_int_sbd_regs;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return gmac_int_sbd_regs;
+ }
+
+ /* Read IER register */
+ gmac_int_sbd_regs.base = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER);
+ /* Read IMR register */
+ gmac_int_sbd_regs.extended = ( ( ~( ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR) ) ) &
+ OGMA_GMAC_INT_SBD_IRQ_ISR_ALL);
+
+
+
+ return gmac_int_sbd_regs;
+}
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status_non_clear (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ )
+{
+ ogma_gmac_int_sbd_regs_t gmac_int_sbd_regs = {0};
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return gmac_int_sbd_regs;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return gmac_int_sbd_regs;
+ }
+
+ /* Read SR register */
+ gmac_int_sbd_regs.base = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_SR);
+
+ /* Read ISR register */
+ gmac_int_sbd_regs.extended = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_ISR);
+
+ if ( mask_flag) {
+
+ /* Read IER register */
+ gmac_int_sbd_regs.base &= ( ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER) |
+ ( ~OGMA_GMAC_INT_SBD_IRQ_IER_ALL) );
+ /* Read IMR register */
+ gmac_int_sbd_regs.extended &= ( ( ~( ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR) ) ) &
+ OGMA_GMAC_INT_SBD_IRQ_ISR_ALL);
+ }
+
+
+ return gmac_int_sbd_regs;
+}
+
+ogma_err_t ogma_clear_gmac_int_sbd_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Write Clear SR register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_SR,
+ ( int_sbd_regs.base & OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL) );
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_enable_gmac_int_sbd_irq (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Read IER register for No Change Value Keep */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER);
+ /* Write IER register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER,
+ ( value | ( int_sbd_regs.base & OGMA_GMAC_INT_SBD_IRQ_IER_ALL) ) );
+
+ /* Read IMR register for No Change Value Keep */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR);
+ /* Write IMR register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR,
+ ( value & ( ~( int_sbd_regs.extended &
+ OGMA_GMAC_INT_SBD_IRQ_ISR_ALL) ) ) );
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_disable_gmac_int_sbd_irq (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Read IER register for No Change Value Keep */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER);
+ /* Write IER register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER,
+ ( value & ( ~(int_sbd_regs.base) ) ) );
+
+ /* Read IMR register for No Change Value Keep */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR);
+ /* Write IMR register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR,
+ ( value | ( int_sbd_regs.extended &
+ OGMA_GMAC_INT_SBD_IRQ_ISR_ALL) ) );
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_get_gmac_rgmii_status_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( value_p == NULL) ){
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Read RGMII Status Register */
+ *value_p = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_RSR);
+
+
+ return OGMA_ERR_OK;
+}
+
+#ifdef OGMA_CONFIG_USE_READ_GMAC_STAT
+ogma_err_t ogma_read_gmac_stat (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p,
+ ogma_bool reset_flag
+ )
+{
+
+ ogma_uint i;
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( value_p == NULL) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+
+ for ( i = 0;
+ i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0] );
+ i++) {
+
+ value_p[i] = ogma_get_mac_reg(ctrl_p,
+ ogma_gmac_mmc_reg_info[i].addr);
+ }
+
+ if ( reset_flag) {
+ /* Reset all counters. */
+ ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
+ }
+
+
+ return OGMA_ERR_OK;
+}
+#endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */
+
+ogma_err_t ogma_reset_gmac_stat (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+
+ /* Reset all counters. */
+ ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_softreset_gmac (
+ ogma_ctrl_t *ctrl_p
+ )
+{
+ ogma_uint32 value;
+ pfdep_err_t pfdep_err;
+
+ /* F_GMAC4MT soft reset*/
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_BMR,
+ OGMA_GMAC_BMR_REG_RESET);
+ /* Wait soft reset */
+ pfdep_err = pfdep_msleep( 1);
+
+ if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "Wait for BMR soft reset error.\n");
+
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ /* Read F_GMAC4MT BMR */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_BMR);
+
+ /* check software reset result*/
+ if ( value & OGMA_GMAC_BMR_REG_SWR) {
+ return OGMA_ERR_AGAIN;
+ }
+
+ return OGMA_ERR_OK;
+}
new file mode 100644
@@ -0,0 +1,210 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_INTERNAL_H
+#define OGMA_INTERNAL_H
+#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
+#include "ogma_reg.h"
+#include "pfdep.h"
+
+/* Just a million to prevent typing errors. */
+#define OGMA_CLK_MHZ (1000000)
+
+#define OGMA_INSTANCE_NUM_MAX 1
+
+#define OGMA_RX_PKT_BUF_LEN 1522
+#define OGMA_RX_JUMBO_PKT_BUF_LEN 9022
+#define OGMA_DUMMY_DESC_ENTRY_LEN 48
+
+#define OGMA_REG_ADDR_CLK_EN OGMA_REG_ADDR_CLK_EN_0
+
+extern const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const ogma_uint32 ogma_desc_start_reg_addr[OGMA_DESC_RING_ID_MAX+1];
+
+typedef struct ogma_ctrl_s ogma_ctrl_t;
+typedef struct ogma_desc_ring_s ogma_desc_ring_t;
+typedef struct ogma_clk_ctrl_s ogma_clk_ctrl_t;
+typedef union ogma_desc_entry_priv_u ogma_desc_entry_priv_t;
+
+struct ogma_clk_ctrl_s{
+ ogma_uint8 mac_req_num;
+};
+
+
+struct ogma_desc_ring_s{
+
+ ogma_desc_ring_id_t ring_id;
+
+ ogma_desc_ring_param_t param;
+
+ ogma_uint rx_desc_ring_flag:1;
+
+ ogma_uint tx_desc_ring_flag:1;
+
+ ogma_uint running_flag:1;
+
+ ogma_uint full_flag:1;
+
+ ogma_uint8 desc_entry_len;
+
+ ogma_uint16 head_idx;
+
+ ogma_uint16 tail_idx;
+
+ ogma_uint16 rx_num;
+
+ ogma_uint16 tx_done_num;
+
+ pfdep_hard_lock_t inten_reg_hard_lock;
+
+ pfdep_soft_lock_t soft_lock;
+
+ void *desc_ring_cpu_addr;
+
+ pfdep_phys_addr_t desc_ring_phys_addr;
+
+ ogma_frag_info_t *frag_info_p;
+
+ ogma_desc_entry_priv_t *priv_data_p;
+};
+
+struct ogma_ctrl_s{
+ ogma_ctrl_t *next_p;
+
+ ogma_uint core_enabled_flag:1;
+
+ ogma_uint gmac_rx_running_flag:1;
+
+ ogma_uint gmac_tx_running_flag:1;
+
+ ogma_uint gmac_mode_valid_flag:1;
+
+ ogma_uint normal_desc_ring_valid:1;
+
+ void *base_addr;
+
+ pfdep_dev_handle_t dev_handle;
+
+ ogma_param_t param;
+
+ ogma_clk_ctrl_t clk_ctrl;
+
+ ogma_uint32 rx_pkt_buf_len;
+
+ ogma_desc_ring_t desc_ring[OGMA_DESC_RING_ID_MAX+1];
+
+ ogma_gmac_mode_t gmac_mode;
+
+ pfdep_hard_lock_t inten_reg_hard_lock;
+
+ pfdep_hard_lock_t clk_ctrl_hard_lock;
+
+ void *dummy_desc_entry_addr;
+
+ pfdep_phys_addr_t dummy_desc_entry_phys_addr;
+
+#ifdef OGMA_CONFIG_REC_STAT
+ /**
+ * Statistics information.
+ *
+ * Note: Since mutual access exclusion is omitted,
+ * these values might be inaccurate.
+ */
+ ogma_stat_info_t stat_info;
+#endif /* OGMA_CONFIG_REC_STAT */
+
+};
+
+union ogma_desc_entry_priv_u{
+ pfdep_pkt_handle_t pkt_handle;
+};
+
+/*****************************************************************
+ *****************************************************************
+ *****************************************************************/
+
+/**
+ *
+ */
+ogma_err_t ogma_alloc_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_id_t ring_idx
+ );
+/**
+ *
+ */
+void ogma_free_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+/**
+ *
+ */
+ogma_err_t ogma_setup_rx_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+/**
+ *
+ */
+void ogma_uninit_pkt_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+/**
+ *
+ */
+void ogma_push_clk_req (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 domain
+ );
+
+void ogma_pop_clk_req(
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 domain
+ );
+
+
+ogma_err_t ogma_softreset_gmac (
+ ogma_ctrl_t *ctrl_p
+ );
+
+#ifdef OGMA_CONFIG_CHECK_CLK_SUPPLY
+#include "ogma_basic_access.h"
+/*include for ogma_read_reg*/
+static __inline void ogma_check_clk_supply (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 domain
+ )
+{
+ ogma_uint32 value;
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN);
+
+ pfdep_assert( ( ( value & domain ) == domain) );
+}
+
+#else
+
+#define ogma_check_clk_supply( ctrl_p, domain)
+
+#endif /* OGMA_CONFIG_CHECK_CLK_SUPPLY */
+
+#endif /* OGMA_INTERNAL_H */
new file mode 100644
@@ -0,0 +1,1385 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_config.h"
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+#include "ogma_misc_internal.h"
+
+#include <Library/IoLib.h>
+
+ogma_global_t ogma_global = {
+ OGMA_FALSE,
+ 0,
+ NULL
+};
+
+
+static const ogma_uint32 hw_ver_reg_addr = OGMA_REG_ADDR_HW_VER;
+static const ogma_uint32 mc_ver_reg_addr = OGMA_REG_ADDR_MC_VER;
+
+static const ogma_uint32 desc_ring_irq_status_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+ OGMA_REG_ADDR_NRM_TX_STATUS,
+ OGMA_REG_ADDR_NRM_RX_STATUS,
+};
+
+static const ogma_uint32 desc_ring_config_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+ OGMA_REG_ADDR_NRM_TX_CONFIG,
+ OGMA_REG_ADDR_NRM_RX_CONFIG,
+
+};
+
+
+/* Internal function definition*/
+#ifndef OGMA_CONFIG_DISABLE_CLK_CTRL
+STATIC void ogma_set_clk_en_reg (
+ ogma_ctrl_t *ctrl_p
+ );
+#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
+STATIC void ogma_global_init ( void);
+
+STATIC ogma_err_t ogma_probe_hardware (
+ void *base_addr
+ );
+
+STATIC void ogma_reset_hardware (
+ ogma_ctrl_t *ctrl_p
+ );
+
+STATIC void ogma_set_microcode(
+ ogma_ctrl_t *ctrl_p,
+ const void *dma_hm_mc_addr,
+ ogma_uint32 dma_hm_mc_len,
+ const void *dma_mh_mc_addr,
+ ogma_uint32 dma_mh_mc_len,
+ const void *pktc_mc_addr,
+ ogma_uint32 pktc_mc_len
+ );
+
+STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
+ const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
+ );
+
+STATIC void ogma_internal_terminate (
+ ogma_ctrl_t *ctrl_p
+ );
+
+#ifdef OGMA_CONFIG_DISABLE_CLK_CTRL
+
+#define ogma_set_clk_en_reg( ctrl_p)
+
+#else /* OGMA_CONFIG_DISABLE_CLK_CTRL */
+STATIC void ogma_set_clk_en_reg (
+ ogma_ctrl_t *ctrl_p
+ )
+{
+ ogma_uint32 value = 0;
+
+ if ( ctrl_p->clk_ctrl.mac_req_num != 0) {
+ value |= OGMA_CLK_EN_REG_DOM_G;
+ }
+
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN, value);
+}
+#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
+
+void ogma_push_clk_req (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 domain
+ )
+{
+ pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
+
+ pfdep_acquire_hard_lock (
+ &ctrl_p->clk_ctrl_hard_lock,
+ &clk_ctrl_hard_lock_ctx);
+
+ if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
+ ++ctrl_p->clk_ctrl.mac_req_num;
+ }
+
+ ogma_set_clk_en_reg( ctrl_p);
+
+ pfdep_release_hard_lock(
+ &ctrl_p->clk_ctrl_hard_lock,
+ &clk_ctrl_hard_lock_ctx);
+}
+
+void ogma_pop_clk_req(
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 domain
+ )
+{
+ pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
+
+ pfdep_acquire_hard_lock(
+ &ctrl_p->clk_ctrl_hard_lock,
+ &clk_ctrl_hard_lock_ctx);
+
+ if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
+ --ctrl_p->clk_ctrl.mac_req_num;
+ }
+
+ ogma_set_clk_en_reg( ctrl_p);
+
+ pfdep_release_hard_lock(
+ &ctrl_p->clk_ctrl_hard_lock,
+ &clk_ctrl_hard_lock_ctx);
+}
+
+/* Internal function */
+STATIC void ogma_global_init ( void)
+{
+ ogma_global.valid_flag = OGMA_TRUE;
+}
+
+STATIC ogma_err_t ogma_probe_hardware (
+ void *base_addr
+ )
+{
+
+ ogma_uint32 value;
+
+ /* Read HW_VER Register */
+ value = pfdep_iomem_read((void *)
+ ((pfdep_cpu_addr_t)base_addr +
+ (OGMA_REG_ADDR_HW_VER << 2)));
+
+ if ( value != OGMA_VER_NETSEC) {
+ pfdep_print(PFDEP_DEBUG_LEVEL_WARNING,
+ "Hardware version check warning. Actual:0x%08x, Expected:0x%08x\n",
+ (unsigned int)value,
+ (unsigned int)OGMA_VER_NETSEC);
+ }
+
+ if ( OGMA_VER_MAJOR_NUM(value) != OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) ) {
+ pfdep_print(PFDEP_DEBUG_LEVEL_FATAL,
+ "Hardware Major version check failed. Actual:0x%08x, Expected:0x%08x\n",
+ (unsigned int)OGMA_VER_MAJOR_NUM(value),
+ (unsigned int)OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) );
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Print hardware version information. */
+ pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+ "NETSEC found. Hardware version: %08x\n",
+ value);
+
+
+ return OGMA_ERR_OK;
+}
+
+STATIC void ogma_reset_hardware (
+ ogma_ctrl_t *ctrl_p
+ )
+{
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_CLK_EN,
+ OGMA_CLK_EN_REG_DOM_ALL);
+
+
+ /*
+ * Stop dma engines if cores are enabled
+ */
+ if (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_DIS_CORE) == 0) {
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_DMA_HM_CTRL,
+ OGMA_DMA_CTRL_REG_STOP);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_DMA_MH_CTRL,
+ OGMA_DMA_CTRL_REG_STOP);
+
+ while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_HM_CTRL)
+ & OGMA_DMA_CTRL_REG_STOP) != 0) {
+ ;
+ }
+
+ while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_MH_CTRL)
+ & OGMA_DMA_CTRL_REG_STOP) != 0) {
+ ;
+ }
+ }
+
+ if ( ctrl_p->param.use_gmac_flag) {
+
+ /* Reset F_GMAC4MT */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_BMR,
+ OGMA_GMAC_BMR_REG_RESET);
+
+ }
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_SOFT_RST,
+ OGMA_SOFT_RST_REG_RESET);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_SOFT_RST,
+ OGMA_SOFT_RST_REG_RUN);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_COM_INIT,
+ OGMA_COM_INIT_REG_ALL);
+
+ while (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_COM_INIT) != 0) {
+ ;
+ }
+
+ if ( ctrl_p->param.use_gmac_flag) {
+
+
+ /* MAC desc init */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_DESC_INIT,
+ OGMA_MAC_DESC_INIT_REG_INIT);
+
+ /* Wait MAC desc init done */
+ while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT)
+ & OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
+ ;
+ }
+
+
+ /* set MAC_INTF_SEL */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_INTF_SEL,
+ ctrl_p->param.gmac_config.phy_interface);
+
+
+ }
+}
+
+#define OGMA_ROUND_UP(numerator,denominator) (((numerator) + (denominator)) - 1 / (denominator))
+
+STATIC void ogma_set_microcode (
+ ogma_ctrl_t *ctrl_p,
+ const void *dma_hm_mc_addr,
+ ogma_uint32 dma_hm_mc_len,
+ const void *dma_mh_mc_addr,
+ ogma_uint32 dma_mh_mc_len,
+ const void *pktc_mc_addr,
+ ogma_uint32 pktc_mc_len
+ )
+{
+ ogma_uint i;
+
+ const UINT32 *dmac_hm_cmd_data = (const UINT32 *)dma_hm_mc_addr;
+ const UINT32 *dmac_mh_cmd_data = (const UINT32 *)dma_mh_mc_addr;
+ const UINT32 *core_cmd_data = (const UINT32 *)pktc_mc_addr;
+
+ /* Loads microcodes to microengines. */
+ for( i = 0; i < dma_hm_mc_len; i++) {
+ UINT32 data = MmioRead32((UINTN)dmac_hm_cmd_data);
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_DMAC_HM_CMD_BUF,
+ data );
+ dmac_hm_cmd_data++;
+ }
+
+ for( i = 0; i < dma_mh_mc_len; i++) {
+ UINT32 data = MmioRead32((UINTN)dmac_mh_cmd_data);
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_DMAC_MH_CMD_BUF,
+ data );
+ dmac_mh_cmd_data++;
+ }
+
+ for( i = 0; i < pktc_mc_len; i++) {
+ UINT32 data = MmioRead32((UINTN)core_cmd_data);
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKTC_CMD_BUF,
+ data );
+ core_cmd_data++;
+ }
+
+}
+
+STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
+ const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
+ )
+{
+ ogma_uint32 param = 0;
+
+ if ( pkt_ctrl_param_p->log_chksum_er_flag) {
+ param |= OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER;
+ }
+
+ if ( pkt_ctrl_param_p->log_hd_imcomplete_flag) {
+ param |= OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE;
+ }
+
+ if ( pkt_ctrl_param_p->log_hd_er_flag) {
+ param |= OGMA_PKT_CTRL_REG_LOG_HD_ER;
+ }
+
+ if ( pkt_ctrl_param_p->drp_no_match_flag) {
+ param |= OGMA_PKT_CTRL_REG_DRP_NO_MATCH;
+ }
+
+ return param;
+}
+
+ogma_err_t ogma_init (
+ void *base_addr,
+ pfdep_dev_handle_t dev_handle,
+ const ogma_param_t *param_p,
+ const void *dma_hm_mc_addr,
+ ogma_uint32 dma_hm_mc_len,
+ const void *dma_mh_mc_addr,
+ ogma_uint32 dma_mh_mc_len,
+ const void *pktc_mc_addr,
+ ogma_uint32 pktc_mc_len,
+ ogma_handle_t *ogma_handle_p
+ )
+{
+ ogma_int i;
+ ogma_uint32 domain = 0, value;
+ ogma_err_t ogma_err;
+ ogma_ctrl_t *ctrl_p = NULL;
+
+ ogma_bool inten_reg_hard_lock_init_flag = OGMA_FALSE;
+ ogma_bool clk_ctrl_hard_lock_init_flag = OGMA_FALSE;
+
+ ogma_bool all_lock_init_done_flag = OGMA_FALSE;
+
+ pfdep_err_t pfdep_err;
+
+ if ( ( param_p == NULL) ||
+ ( ogma_handle_p == NULL) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ogma_global.list_entry_num + 1 > OGMA_INSTANCE_NUM_MAX) {
+ return OGMA_ERR_INVALID;
+ }
+
+ if ((! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag) &&
+ (! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag)) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Please set invalid packet desc_ring_param valid_flag.\n");
+ return OGMA_ERR_DATA;
+ }
+
+ if ( param_p->use_gmac_flag) {
+ if ( ( param_p->gmac_config.phy_interface !=
+ OGMA_PHY_INTERFACE_GMII) &&
+ ( param_p->gmac_config.phy_interface !=
+ OGMA_PHY_INTERFACE_RGMII) &&
+ ( param_p->gmac_config.phy_interface !=
+ OGMA_PHY_INTERFACE_RMII) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Please set phy_interface to valid value.\n");
+ return OGMA_ERR_DATA;
+ }
+ } else {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Please set use_gmac_flag OGMA_TRUE.\n");
+ return OGMA_ERR_DATA;
+ }
+
+ ogma_err = ogma_probe_hardware( base_addr);
+
+ if ( ogma_err != OGMA_ERR_OK) {
+ return ogma_err;
+ }
+
+ if ( !ogma_global.valid_flag) {
+ ogma_global_init();
+ }
+
+ if ( ( ctrl_p = pfdep_malloc( sizeof( ogma_ctrl_t) ) ) == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to ogma_handle memory allocation.\n");
+ return OGMA_ERR_ALLOC;
+ }
+
+ pfdep_memset( ctrl_p, 0, sizeof( ogma_ctrl_t) );
+
+ ctrl_p->base_addr = base_addr;
+
+ ctrl_p->dev_handle = dev_handle;
+
+ pfdep_memcpy( ( void *)&ctrl_p->param,
+ ( void *)param_p,
+ sizeof( ogma_param_t) );
+
+ /* Initialize hardware lock */
+ pfdep_err = pfdep_init_hard_lock( &ctrl_p->inten_reg_hard_lock);
+ if ( pfdep_err != PFDEP_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to inten_reg_hard_lock's initialization.\n");
+ ogma_err = OGMA_ERR_ALLOC;
+ goto err;
+ }
+ inten_reg_hard_lock_init_flag = OGMA_TRUE;
+
+ pfdep_err = pfdep_init_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
+ if ( pfdep_err != PFDEP_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to clk_ctrl_hard_lock's initialization.\n");
+ ogma_err = OGMA_ERR_ALLOC;
+ goto err;
+ }
+ clk_ctrl_hard_lock_init_flag = OGMA_TRUE;
+
+ all_lock_init_done_flag = OGMA_TRUE;
+
+ pfdep_err = pfdep_dma_malloc( dev_handle,
+ OGMA_DUMMY_DESC_ENTRY_LEN,
+ &ctrl_p->dummy_desc_entry_addr,
+ &ctrl_p->dummy_desc_entry_phys_addr);
+
+ if ( pfdep_err != PFDEP_ERR_OK) {
+ ogma_err = OGMA_ERR_ALLOC;
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to dummy_desc_entry's memory allocation.\n");
+ goto err;
+ }
+
+ /* clear dummy desc entry */
+ pfdep_memset( ctrl_p->dummy_desc_entry_addr,
+ 0,
+ OGMA_DUMMY_DESC_ENTRY_LEN);
+
+ ogma_reset_hardware( ctrl_p);
+
+ if ( param_p->use_gmac_flag) {
+ domain |= OGMA_CLK_EN_REG_DOM_G;
+ }
+
+ ogma_push_clk_req( ctrl_p, domain);
+
+ /* set PKT_CTRL */
+ value = ogma_calc_pkt_ctrl_reg_param( ¶m_p->pkt_ctrl_param);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_CTRL,
+ value);
+
+ if ( param_p->use_jumbo_pkt_flag) {
+
+ ctrl_p->rx_pkt_buf_len = OGMA_RX_JUMBO_PKT_BUF_LEN;
+
+ value = ogma_read_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_CTRL);
+
+ value |= OGMA_PKT_CTRL_REG_EN_JUMBO;
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_CTRL,
+ value);
+ } else {
+
+ ctrl_p->rx_pkt_buf_len = OGMA_RX_PKT_BUF_LEN;
+
+ }
+
+ /* set pkt desc ring config */
+ for ( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
+ if ( ctrl_p->param.desc_ring_param[i].valid_flag) {
+ value =
+ ( ctrl_p->param.desc_ring_param[i].tmr_mode_flag <<
+ OGMA_REG_DESC_RING_CONFIG_TMR_MODE) |
+ ( ctrl_p->param.desc_ring_param[i].little_endian_flag <<
+ OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN) ;
+
+ ogma_write_reg( ctrl_p,
+ desc_ring_config_reg_addr[i],
+ value);
+
+ }
+ }
+
+ /* set microengines */
+ ogma_set_microcode(ctrl_p,
+ dma_hm_mc_addr,
+ dma_hm_mc_len,
+ dma_mh_mc_addr,
+ dma_mh_mc_len,
+ pktc_mc_addr,
+ pktc_mc_len);
+
+ /* alloc desc_ring*/
+ for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
+ ogma_err = ogma_alloc_desc_ring( ctrl_p, (ogma_desc_ring_id_t)i);
+ if ( ogma_err != OGMA_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to ring id NO.%d memory allocation.\n",
+ i);
+ goto err;
+ }
+ }
+
+ if ( param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag) {
+ if ( ( ogma_err = ogma_setup_rx_desc_ring(
+ ctrl_p,
+ &ctrl_p->desc_ring[OGMA_DESC_RING_ID_NRM_RX] ) )
+ != OGMA_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to NRM_RX packet memory allocation.\n");
+ goto err;
+ }
+ }
+
+ /* microengines need domain G */
+ ogma_push_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+ /* set DMA tmr ctrl*/
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL,
+ ( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) - 1) );
+
+ /* start microengines */
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0);
+
+ if ( pfdep_msleep(1) != PFDEP_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to waiting for microcode initialize end.\n");
+ ogma_err = OGMA_ERR_INTERRUPT;
+ goto err;
+ }
+
+ /* check microcode load end & start core */
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
+
+ if ( ( value & OGMA_TOP_IRQ_REG_ME_START) == 0) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to microcode loading.\n");
+ ogma_err = OGMA_ERR_INVALID;
+ goto err;
+ }
+
+ /* clear microcode load end status */
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS,
+ OGMA_TOP_IRQ_REG_ME_START);
+
+ ogma_pop_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+ ctrl_p->core_enabled_flag = OGMA_TRUE;
+
+ ctrl_p->next_p = ogma_global.list_head_p;
+
+ ogma_global.list_head_p = ctrl_p;
+
+ ++ogma_global.list_entry_num;
+
+ *ogma_handle_p = ctrl_p;
+
+#if 1
+ {
+
+#define OGMA_PKT_CTRL_REG_MODE_TAIKI (1UL << 28)
+#define OGMA_DMA_MH_CTRL_REG_MODE_TRANS (1UL << 20)
+#define OGMA_TOP_IRQ_REG_MODE_TRANS_COMP (1UL << 4)
+#define OGMA_MODE_TRANS_COMP_IRQ_T2N (1UL << 19)
+
+ /* Read Pkt ctrl register */
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_CTRL);
+ value |= OGMA_PKT_CTRL_REG_MODE_TAIKI;
+
+ /* change to noromal mode */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_DMA_MH_CTRL,
+ OGMA_DMA_MH_CTRL_REG_MODE_TRANS);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_CTRL,
+ value);
+
+ while ((ogma_read_reg(ctrl_p, OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS) &
+ OGMA_MODE_TRANS_COMP_IRQ_T2N) == 0) {
+ ;
+ }
+
+ }
+#endif
+
+ /* Print microcode version information. */
+ pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+ "Microcode version: %08x\n",
+ ogma_read_reg( ctrl_p,
+ mc_ver_reg_addr) );
+
+ return OGMA_ERR_OK;
+
+err:
+ if ( !all_lock_init_done_flag) {
+
+
+ if ( clk_ctrl_hard_lock_init_flag) {
+ pfdep_uninit_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
+ }
+
+ if ( inten_reg_hard_lock_init_flag) {
+ pfdep_uninit_hard_lock( &ctrl_p->inten_reg_hard_lock);
+ }
+
+ } else {
+
+ ogma_internal_terminate( ctrl_p);
+
+ }
+
+ pfdep_free( ctrl_p);
+
+ return ogma_err;
+}
+
+STATIC void ogma_internal_terminate (
+ ogma_ctrl_t *ctrl_p
+ )
+{
+ ogma_int i;
+
+ ogma_reset_hardware( ctrl_p);
+
+ /* free desc_ring */
+ for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
+ ogma_free_desc_ring( ctrl_p, &ctrl_p->desc_ring[i] );
+ }
+
+ if ( ctrl_p->dummy_desc_entry_addr != NULL) {
+ pfdep_dma_free( ctrl_p->dev_handle,
+ OGMA_DUMMY_DESC_ENTRY_LEN,
+ ctrl_p->dummy_desc_entry_addr,
+ ctrl_p->dummy_desc_entry_phys_addr);
+ }
+
+ pfdep_uninit_hard_lock ( &ctrl_p->inten_reg_hard_lock);
+
+
+ pfdep_uninit_hard_lock ( &ctrl_p->clk_ctrl_hard_lock);
+
+}
+
+void ogma_terminate (
+ ogma_handle_t ogma_handle
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_ctrl_t *tmp_ctrl_p = NULL, *old_tmp_ctrl_p = NULL;
+ ogma_uint32 domain = 0;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ogma_global.list_entry_num == 0) ) {
+ return;
+ }
+
+ pfdep_assert( ogma_global.list_head_p != NULL);
+
+ if ( ctrl_p->param.use_gmac_flag) {
+ domain |= OGMA_CLK_EN_REG_DOM_G;
+ }
+
+ /* pop domain clock */
+ ogma_pop_clk_req( ctrl_p, domain);
+
+ tmp_ctrl_p = ogma_global.list_head_p;
+
+ while(1) {
+ if ( tmp_ctrl_p == NULL) {
+ /* Could not found ctrl_p specified from the list */
+ return;
+ }
+ if ( ctrl_p == tmp_ctrl_p) {
+ if ( old_tmp_ctrl_p != NULL) {
+ old_tmp_ctrl_p->next_p = ctrl_p->next_p;
+ } else {
+ ogma_global.list_head_p = ctrl_p->next_p;
+ }
+ break;
+ }
+ old_tmp_ctrl_p = tmp_ctrl_p;
+ tmp_ctrl_p = tmp_ctrl_p->next_p;
+ }
+
+ ogma_internal_terminate( ctrl_p);
+
+ --ogma_global.list_entry_num;
+
+ pfdep_free( ctrl_p);
+ return;
+}
+
+ogma_err_t ogma_enable_top_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ /* set irq_factor*/
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_SET, irq_factor);
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_disable_top_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ /* clear irq_factor*/
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_CLR, irq_factor);
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_enable_desc_ring_irq (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+
+ pfdep_err_t pfdep_err;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_enable_desc_ring_irq.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_enable_desc_ring_irq.\n"
+ "Please select ring id number between 0 and %d.\n",
+ OGMA_DESC_RING_ID_MAX);
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_enable_desc_ring_irq.\n"
+ "Please select valid desc ring.\n");
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ /* get soft lock */
+ pfdep_err = pfdep_acquire_soft_lock (
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ if ( pfdep_err != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ if ( !desc_ring_p->running_flag) {
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_enable_desc_ring_irq.\n"
+ "Please select running desc ring.\n");
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* set irq_factor*/
+ ogma_write_reg( ctrl_p,
+ desc_ring_irq_inten_set_reg_addr[ring_id],
+ irq_factor);
+
+ /* free soft_lock*/
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return ogma_err;
+}
+
+ogma_err_t ogma_disable_desc_ring_irq (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_disable_desc_ring_irq.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_disable_desc_ring_irq.\n"
+ "Please select ring id number between 0 and %d.\n",
+ OGMA_DESC_RING_ID_MAX);
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_disable_desc_ring_irq.\n"
+ "Please select valid desc ring.\n");
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Clear irq factor*/
+ ogma_write_reg( ctrl_p,
+ desc_ring_irq_inten_clr_reg_addr[ring_id],
+ irq_factor);
+
+ return ogma_err;
+}
+
+ogma_err_t ogma_enable_pkt_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ /* set irq_factor*/
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN_SET,
+ ( irq_factor & OGMA_PKT_IRQ_ALL) );
+
+ return ogma_err;
+}
+
+ogma_err_t ogma_disable_pkt_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ /* clear irq_factor*/
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_INTEN_CLR,
+ ( irq_factor & OGMA_PKT_IRQ_ALL) );
+
+ return ogma_err;
+}
+
+
+ogma_uint32 ogma_get_top_irq_enable (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_top_irq_enable.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
+
+ return value;
+
+}
+
+
+ogma_uint32 ogma_get_top_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_top_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
+
+ if ( mask_flag) {
+ value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
+ }
+
+ return value;
+}
+
+ogma_err_t ogma_clear_top_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_top_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ /* Write clear irq top status */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_TOP_STATUS,
+
+ ( value & OGMA_TOP_IRQ_REG_ME_START) );
+
+ return OGMA_ERR_OK;
+}
+
+ogma_uint32 ogma_get_desc_ring_irq_enable (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_enable.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_enable.\n"
+ "Please select ring id number between 0 and %d.\n",
+ OGMA_DESC_RING_ID_MAX);
+ return 0;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_enable.\n"
+ "Please select valid desc ring.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p,
+ desc_ring_irq_inten_reg_addr[ring_id] );
+
+ return value;
+}
+
+
+ogma_uint32 ogma_get_desc_ring_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_bool mask_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_status.\n"
+ "Please select ring id number between 0 and %d.\n",
+ OGMA_DESC_RING_ID_MAX);
+ return 0;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_status.\n"
+ "Please select valid desc ring.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p,
+ desc_ring_irq_status_reg_addr[ring_id] );
+
+ if ( mask_flag) {
+ value &= ogma_read_reg( ctrl_p,
+ desc_ring_irq_inten_reg_addr[ring_id] );
+ }
+
+ return value;
+}
+
+
+
+ogma_err_t ogma_clear_desc_ring_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 value
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_desc_ring_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_desc_ring_irq_status.\n"
+ "Please select ring id number between 0 and %d.\n",
+ OGMA_DESC_RING_ID_MAX);
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_desc_ring_irq_status.\n"
+ "Please select valid desc ring.\n");
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Write clear descring irq status */
+ ogma_write_reg( ctrl_p,
+ desc_ring_irq_status_reg_addr[ring_id],
+ ( value & ( OGMA_CH_IRQ_REG_EMPTY |
+ OGMA_CH_IRQ_REG_ERR) ) );
+
+ return OGMA_ERR_OK;
+
+}
+
+
+ogma_uint32 ogma_get_pkt_irq_enable (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_pkt_irq_enable.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
+
+ value &= OGMA_PKT_IRQ_ALL;
+
+ return value;
+
+}
+
+ogma_uint32 ogma_get_pkt_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_pkt_irq_statusnon_clear.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_STATUS);
+
+ if ( mask_flag) {
+ value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
+ }
+
+ return value;
+}
+
+ogma_err_t ogma_clear_pkt_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_pkt_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ /* Write clear irq pkt status */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_STATUS,
+ ( value & ( ( OGMA_PKT_IRQ_MAC_ER |
+ OGMA_PKT_IRQ_JUMBO_ER |
+ OGMA_PKT_IRQ_CHKSUM_ER |
+ OGMA_PKT_IRQ_HD_INCOMPLETE |
+ OGMA_PKT_IRQ_HD_ER |
+ OGMA_PKT_IRQ_DRP_NO_MATCH) ) ) );
+
+ return OGMA_ERR_OK;
+}
+
+#ifdef OGMA_CONFIG_REC_STAT
+ogma_err_t ogma_get_stat_info (
+ ogma_handle_t ogma_handle,
+ ogma_stat_info_t *stat_info_p,
+ ogma_bool clear_flag
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) || (stat_info_p == NULL) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ pfdep_memcpy( stat_info_p,
+ &ctrl_p->stat_info,
+ sizeof( ogma_stat_info_t) );
+
+
+ if ( clear_flag) {
+ pfdep_memset( &ctrl_p->stat_info, 0, sizeof( ogma_stat_info_t) );
+ }
+
+ return OGMA_ERR_OK;
+
+}
+#endif /* OGMA_CONFIG_REC_STAT */
+
+ogma_uint32 ogma_get_hw_ver (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p,
+ hw_ver_reg_addr);
+
+ return value;
+}
+
+
+ogma_uint32 ogma_get_mcr_ver (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p,
+ mc_ver_reg_addr);
+
+ return value;
+}
+
+ogma_uint32 ogma_get_mac_irq_enable (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_ogma_get_mac_irq_enable.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
+
+
+ return value;
+}
+
+ogma_uint32 ogma_get_mac_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_mac_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_STATUS);
+
+ if ( mask_flag) {
+ value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
+ }
+
+
+ return value;
+}
+
+ogma_err_t ogma_clear_mac_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_mac_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+
+ /* Commented out because no write-clear bit exists now. */
+#if 0
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_STATUS,
+ ( value & /* T.B.D. */) );
+#endif
+
+
+ return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_enable_mac_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_uint32 value;
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_enable_mac_irq.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ /* get inten_reg_hard_lock */
+ pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
+ &inten_reg_hard_lock_ctx);
+
+ value = ogma_read_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_INTEN);
+
+ value |= irq_factor;
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_INTEN,
+ value);
+
+
+ /* free inten_reg_hard_lock*/
+ pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
+ &inten_reg_hard_lock_ctx);
+ return ogma_err;
+}
+
+ogma_err_t ogma_disable_mac_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_uint32 value;
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
+
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_disable_mac_irq.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ /* get inten_reg_hard_lock */
+ pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
+ &inten_reg_hard_lock_ctx);
+
+ value = ogma_read_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_INTEN);
+
+ value &= (~irq_factor);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_INTEN,
+ value);
+
+
+ /* free inten_reg_hard_lock*/
+ pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
+ &inten_reg_hard_lock_ctx);
+ return ogma_err;
+
+}
new file mode 100644
@@ -0,0 +1,38 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_MISC_INTERNAL_H
+#define OGMA_MISC_INTERNAL_H
+
+#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
+#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
+
+#define OGMA_CLK_EN_REG_DOM_ALL 0x24
+
+#define OGMA_PKT_IRQ_ALL ( OGMA_PKT_IRQ_MAC_ER | OGMA_PKT_IRQ_JUMBO_ER | \
+ OGMA_PKT_IRQ_CHKSUM_ER | OGMA_PKT_IRQ_HD_INCOMPLETE | \
+ OGMA_PKT_IRQ_HD_ER | OGMA_PKT_IRQ_DRP_NO_MATCH)
+
+typedef struct ogma_global_s ogma_global_t;
+
+struct ogma_global_s{
+ ogma_uint valid_flag:1;
+
+ ogma_uint8 list_entry_num;
+
+ ogma_ctrl_t *list_head_p;
+};
+
+#endif /* OGMA_MISC_INTERNAL_H */
new file mode 100644
@@ -0,0 +1,219 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_REG_H
+#define OGMA_REG_H
+
+#include "ogma_reg_netsec.h"
+#include "ogma_reg_f_gmac_4mt.h"
+
+/* aliases */
+#define OGMA_REG_ADDR_TOP_INTEN OGMA_REG_ADDR_TOP_INTEN_A
+#define OGMA_REG_ADDR_TOP_INTEN_SET OGMA_REG_ADDR_TOP_INTEN_A_SET
+#define OGMA_REG_ADDR_TOP_INTEN_CLR OGMA_REG_ADDR_TOP_INTEN_A_CLR
+/* aliases end here */
+
+/* need fixing */
+#define OGMA_REG_ADDR_DMAC_MH_CMD_BUF (0x87)
+
+
+/*bit fields for PKT_CTRL*/
+#define OGMA_PKT_CTRL_REG_EN_JUMBO (1UL << 27)
+#define OGMA_PKT_CTRL_REG_EN_BITPATF (1UL << 4 )
+#define OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER (1UL << 3 )
+#define OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE (1UL << 2 )
+#define OGMA_PKT_CTRL_REG_LOG_HD_ER (1UL << 1 )
+#define OGMA_PKT_CTRL_REG_DRP_NO_MATCH (1UL << 0 )
+
+#define OGMA_CLK_EN_REG_DOM_G (1UL << 5)
+
+/************************************************************
+ * Bit fields
+ ************************************************************/
+/* bit fields for com_init */
+#define OGMA_COM_INIT_REG_DB (1UL << 2)
+#define OGMA_COM_INIT_REG_CLS (1UL << 1)
+#define OGMA_COM_INIT_REG_ALL ( OGMA_COM_INIT_REG_CLS | OGMA_COM_INIT_REG_DB)
+
+/* bit fields for soft_rst */
+#define OGMA_SOFT_RST_REG_RESET (0)
+#define OGMA_SOFT_RST_REG_RUN (1UL << 31)
+
+/* bit fields for dma_hm_ctrl */
+#define OGMA_DMA_CTRL_REG_STOP 1UL
+
+/* bit fields for gmac_cmd */
+#define OGMA_GMAC_CMD_ST_READ (0)
+#define OGMA_GMAC_CMD_ST_WRITE (1UL << 28)
+#define OGMA_GMAC_CMD_ST_BUSY (1UL << 31)
+
+/* bit fields for F_GMAC4MT BMR*/
+#define OGMA_GMAC_BMR_REG_COMMON (0x00412080)
+#define OGMA_GMAC_BMR_REG_RESET (0x00020181)
+#define OGMA_GMAC_BMR_REG_SWR (0x00000001)
+
+/* bit fields for F_GMAC4MT OMR*/
+#define OGMA_GMAC_OMR_REG_ST (1UL << 13)
+#define OGMA_GMAC_OMR_REG_SR (1UL << 1)
+
+/* bit fields for F_GMAC4MT MCR*/
+#define OGMA_GMAC_MCR_REG_CST (1UL << 25)
+#define OGMA_GMAC_MCR_REG_JE (1UL << 20)
+#define OGMA_GMAC_MCR_REG_PS (1UL << 15)
+#define OGMA_GMAC_MCR_REG_FES (1UL << 14)
+#define OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON (0x0000280c)
+#define OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON (0x0001a00c)
+
+#define OGMA_GMAC_MCR_1G_FULL ( OGMA_GMAC_MCR_REG_CST | \
+ OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_100M_FULL ( OGMA_GMAC_MCR_REG_CST | \
+ OGMA_GMAC_MCR_REG_PS | \
+ OGMA_GMAC_MCR_REG_FES | \
+ OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_100M_HALF ( OGMA_GMAC_MCR_REG_CST | \
+ OGMA_GMAC_MCR_REG_FES | \
+ OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_10M_FULL ( OGMA_GMAC_MCR_REG_CST | \
+ OGMA_GMAC_MCR_REG_PS | \
+ OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_10M_HALF ( OGMA_GMAC_MCR_REG_CST | \
+ OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
+
+/*bit fields for F_GMAC4MT FCR*/
+#define OGMA_GMAC_FCR_REG_RFE (1UL << 2)
+#define OGMA_GMAC_FCR_REG_TFE (1UL << 1)
+
+/* bit fields for F_GMAC4MT GAR */
+#define OGMA_GMAC_GAR_REG_GW (1UL << 1)
+#define OGMA_GMAC_GAR_REG_GB (1UL << 0)
+
+/* bit fields for F_GMAC4MT RDLAR*/
+#define OGMA_GMAC_RDLAR_REG_COMMON (0x00018000UL)
+
+/* bit fields for F_GMAC4MT TDLAR*/
+#define OGMA_GMAC_TDLAR_REG_COMMON (0x0001c000UL)
+
+
+#define OGMA_GMAC_GAR_REG_SHIFT_PA (11)
+#define OGMA_GMAC_GAR_REG_SHIFT_GR (6)
+#define OGMA_GMAC_GAR_REG_SHIFT_CR (2)
+
+#define OGMA_GMAC_GAR_REG_CR_25_35_MHZ (2)
+#define OGMA_GMAC_GAR_REG_CR_35_60_MHZ (3)
+#define OGMA_GMAC_GAR_REG_CR_60_100_MHZ (0)
+#define OGMA_GMAC_GAR_REG_CR_100_150_MHZ (1)
+#define OGMA_GMAC_GAR_REG_CR_150_250_MHZ (4)
+#define OGMA_GMAC_GAR_REG_CR_250_300_MHZ (5)
+
+/* bit fields for F_GMAC4MT LPITCR */
+#define OGMA_GMAC_LPITCR_REG_LIT (16)
+#define OGMA_GMAC_LPITCR_REG_TWT (0)
+
+/* bit fileds mask for F_GMAC4MT LPITCR */
+#define OGMA_GMAC_LPITCR_REG_MASK_LIT (0x3ffU)
+#define OGMA_GMAC_LPITCR_REG_MASK_TWT (0xffffU)
+
+/**
+ * PHY regtister Address
+ */
+#define OGMA_PHY_REG_ADDR_CONTROL 0
+#define OGMA_PHY_REG_ADDR_STATUS 1U
+#define OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY 4U
+#define OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY 5U
+#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL 9U
+#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS 10U
+#define OGMA_PHY_REG_ADDR_MMD_AC 13U
+#define OGMA_PHY_REG_ADDR_MMD_AAD 14U
+
+/* bit fields for PHY CONTROL Register */
+#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB (6)
+#define OGMA_PHY_CONTROL_REG_DUPLEX_MODE (8)
+#define OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE (12)
+#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB (13)
+
+/* bit fields for PHY STATUS Register */
+#define OGMA_PHY_STATUS_REG_LINK_STATUS (2)
+#define OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY (3)
+#define OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP (5)
+
+/* bit fields for PHY MASTER-SLAVE Control Register */
+#define OGMA_PHY_MSC_REG_1000BASE_FULL (9)
+#define OGMA_PHY_MSC_REG_1000BASE_HALF (8)
+
+/* bit fields for PHY MASTER-SLAVE Status Register */
+#define OGMA_PHY_MSS_REG_LP_1000BASE_FULL (11)
+#define OGMA_PHY_MSS_REG_LP_1000BASE_HALF (10)
+
+/* bit fields for PHY Auto-Negotiation Advertisement Register */
+#define OGMA_PHY_ANA_REG_TAF (5)
+
+/* bit fileds mask for F_GMAC4MT LPITCR */
+#define OGMA_PHY_ANA_REG_TAF_MASK (0x7fU)
+
+/* bit fields for PHY Technology Ability Field */
+#define OGMA_PHY_TAF_REG_100BASE_FULL (1U << 3)
+#define OGMA_PHY_TAF_REG_100BASE_HALF (1U << 2)
+#define OGMA_PHY_TAF_REG_10BASE_FULL (1U << 1)
+#define OGMA_PHY_TAF_REG_10BASE_HALF (1U << 0)
+
+/**
+ * PHY Device Address
+ */
+#define OGMA_PHY_DEV_ADDR_AUTO_NEGO (7U)
+
+/**
+ * PHY Register Address for Device Address 7
+ */
+#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE (60U)
+#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY (61U)
+
+/* bit fields for PHY AutoNegotiation Field */
+#define OGMA_PHY_AUTO_NEGO_1000BASE_EEE (1U << 2)
+#define OGMA_PHY_AUTO_NEGO_100BASE_EEE (1U << 1)
+
+/* bit fields for DESC RING CONFIG */
+#define OGMA_REG_DESC_RING_CONFIG_CFG_UP (31)
+#define OGMA_REG_DESC_RING_CONFIG_CH_RST (30)
+#define OGMA_REG_DESC_RING_CONFIG_TMR_MODE (4)
+#define OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN (0)
+
+
+/* bit fields for mac_desc_soft_rst */
+#define OGMA_MAC_DESC_SOFT_RST_SOFT_RST 1UL
+
+/* bit fields for mac_desc_init */
+#define OGMA_MAC_DESC_INIT_REG_INIT 1UL
+
+/* bit fields for dis_core */
+#define OGMA_DIS_CORE_REG_DIS_PCORE (1UL << 2)
+#define OGMA_DIS_CORE_REG_DIS_MHCORE (1UL << 1)
+#define OGMA_DIS_CORE_REG_DIS_HMCORE (1UL << 0)
+
+#define OGMA_DIS_CORE_REG_ALL ( OGMA_DIS_CORE_REG_DIS_HMCORE | \
+ OGMA_DIS_CORE_REG_DIS_MHCORE | \
+ OGMA_DIS_CORE_REG_DIS_PCORE)
+
+/* bit fields for dma_info */
+#define OGMA_DMA_INFO_REG_AXI_WRITE_BUSY (1UL << 3)
+#define OGMA_DMA_INFO_REG_AXI_READ_BUSY (1UL << 2)
+
+#define OGMA_DMA_INFO_REG_AXI_BUSY ( OGMA_DMA_INFO_REG_AXI_WRITE_BUSY | \
+ OGMA_DMA_INFO_REG_AXI_READ_BUSY)
+
+#endif /*OGMA_REG_H*/
new file mode 100644
@@ -0,0 +1,222 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_REG_F_GMAC_4MT_H
+#define OGMA_REG_F_GMAC_4MT_H
+
+/**
+ * GMAC register
+ */
+#define OGMA_GMAC_REG_ADDR_MCR (0x0000)
+#define OGMA_GMAC_REG_ADDR_MFFR (0x0004)
+#define OGMA_GMAC_REG_ADDR_MHTRH (0x0008)
+#define OGMA_GMAC_REG_ADDR_MHTRL (0x000c)
+#define OGMA_GMAC_REG_ADDR_GAR (0x0010)
+#define OGMA_GMAC_REG_ADDR_GDR (0x0014)
+#define OGMA_GMAC_REG_ADDR_FCR (0x0018)
+#define OGMA_GMAC_REG_ADDR_VTR (0x001c)
+#define OGMA_GMAC_REG_ADDR_RWFFR (0x0028)
+#define OGMA_GMAC_REG_ADDR_PMTR (0x002c)
+#define OGMA_GMAC_REG_ADDR_LPICSR (0x0030)
+#define OGMA_GMAC_REG_ADDR_LPITCR (0x0034)
+#define OGMA_GMAC_REG_ADDR_ISR (0x0038)
+#define OGMA_GMAC_REG_ADDR_IMR (0x003c)
+#define OGMA_GMAC_REG_ADDR_MAR0H (0x0040)
+#define OGMA_GMAC_REG_ADDR_MAR0L (0x0044)
+#define OGMA_GMAC_REG_ADDR_MAR1H (0x0048)
+#define OGMA_GMAC_REG_ADDR_MAR1L (0x004c)
+#define OGMA_GMAC_REG_ADDR_MAR2H (0x0050)
+#define OGMA_GMAC_REG_ADDR_MAR2L (0x0054)
+#define OGMA_GMAC_REG_ADDR_MAR3H (0x0058)
+#define OGMA_GMAC_REG_ADDR_MAR3L (0x005c)
+#define OGMA_GMAC_REG_ADDR_MAR4H (0x0060)
+#define OGMA_GMAC_REG_ADDR_MAR4L (0x0064)
+#define OGMA_GMAC_REG_ADDR_MAR5H (0x0068)
+#define OGMA_GMAC_REG_ADDR_MAR5L (0x006c)
+#define OGMA_GMAC_REG_ADDR_MAR6H (0x0070)
+#define OGMA_GMAC_REG_ADDR_MAR6L (0x0074)
+#define OGMA_GMAC_REG_ADDR_MAR7H (0x0078)
+#define OGMA_GMAC_REG_ADDR_MAR7L (0x007c)
+#define OGMA_GMAC_REG_ADDR_MAR8H (0x0080)
+#define OGMA_GMAC_REG_ADDR_MAR8L (0x0084)
+#define OGMA_GMAC_REG_ADDR_MAR9H (0x0088)
+#define OGMA_GMAC_REG_ADDR_MAR9L (0x008c)
+#define OGMA_GMAC_REG_ADDR_MAR10H (0x0090)
+#define OGMA_GMAC_REG_ADDR_MAR10L (0x0094)
+#define OGMA_GMAC_REG_ADDR_MAR11H (0x0098)
+#define OGMA_GMAC_REG_ADDR_MAR11L (0x009c)
+#define OGMA_GMAC_REG_ADDR_MAR12H (0x00a0)
+#define OGMA_GMAC_REG_ADDR_MAR12L (0x00a4)
+#define OGMA_GMAC_REG_ADDR_MAR13H (0x00a8)
+#define OGMA_GMAC_REG_ADDR_MAR13L (0x00ac)
+#define OGMA_GMAC_REG_ADDR_MAR14H (0x00b0)
+#define OGMA_GMAC_REG_ADDR_MAR14L (0x00b4)
+#define OGMA_GMAC_REG_ADDR_MAR15H (0x00b8)
+#define OGMA_GMAC_REG_ADDR_MAR15L (0x00bc)
+#define OGMA_GMAC_REG_ADDR_RSR (0x00d8)
+#define OGMA_GMAC_REG_ADDR_TSCR (0x0700)
+#define OGMA_GMAC_REG_ADDR_SSIR (0x0704)
+#define OGMA_GMAC_REG_ADDR_STSR (0x0708)
+#define OGMA_GMAC_REG_ADDR_STNR (0x070c)
+#define OGMA_GMAC_REG_ADDR_STSUR (0x0710)
+#define OGMA_GMAC_REG_ADDR_STNUR (0x0714)
+#define OGMA_GMAC_REG_ADDR_TSAR (0x0718)
+#define OGMA_GMAC_REG_ADDR_TTSR (0x071c)
+#define OGMA_GMAC_REG_ADDR_TTNR (0x0720)
+#define OGMA_GMAC_REG_ADDR_STHWSR (0x0724)
+#define OGMA_GMAC_REG_ADDR_TSR (0x0728)
+#define OGMA_GMAC_REG_ADDR_PPSCR (0x072c)
+#define OGMA_GMAC_REG_ADDR_ANTR (0x0730)
+#define OGMA_GMAC_REG_ADDR_ATSR (0x0734)
+#define OGMA_GMAC_REG_ADDR_MAR16H (0x0800)
+#define OGMA_GMAC_REG_ADDR_MAR16L (0x0804)
+#define OGMA_GMAC_REG_ADDR_MAR17H (0x0808)
+#define OGMA_GMAC_REG_ADDR_MAR17L (0x080c)
+#define OGMA_GMAC_REG_ADDR_MAR18H (0x0810)
+#define OGMA_GMAC_REG_ADDR_MAR18L (0x0814)
+#define OGMA_GMAC_REG_ADDR_MAR19H (0x0818)
+#define OGMA_GMAC_REG_ADDR_MAR19L (0x081c)
+#define OGMA_GMAC_REG_ADDR_MAR20H (0x0820)
+#define OGMA_GMAC_REG_ADDR_MAR20L (0x0824)
+#define OGMA_GMAC_REG_ADDR_MAR21H (0x0828)
+#define OGMA_GMAC_REG_ADDR_MAR21L (0x082c)
+#define OGMA_GMAC_REG_ADDR_MAR22H (0x0830)
+#define OGMA_GMAC_REG_ADDR_MAR22L (0x0834)
+#define OGMA_GMAC_REG_ADDR_MAR23H (0x0838)
+#define OGMA_GMAC_REG_ADDR_MAR23L (0x083c)
+#define OGMA_GMAC_REG_ADDR_MAR24H (0x0840)
+#define OGMA_GMAC_REG_ADDR_MAR24L (0x0844)
+#define OGMA_GMAC_REG_ADDR_MAR25H (0x0848)
+#define OGMA_GMAC_REG_ADDR_MAR25L (0x084c)
+#define OGMA_GMAC_REG_ADDR_MAR26H (0x0850)
+#define OGMA_GMAC_REG_ADDR_MAR26L (0x0854)
+#define OGMA_GMAC_REG_ADDR_MAR27H (0x0858)
+#define OGMA_GMAC_REG_ADDR_MAR27L (0x085c)
+#define OGMA_GMAC_REG_ADDR_MAR28H (0x0860)
+#define OGMA_GMAC_REG_ADDR_MAR28L (0x0864)
+#define OGMA_GMAC_REG_ADDR_MAR29H (0x0868)
+#define OGMA_GMAC_REG_ADDR_MAR29L (0x086c)
+#define OGMA_GMAC_REG_ADDR_MAR30H (0x0870)
+#define OGMA_GMAC_REG_ADDR_MAR30L (0x0874)
+#define OGMA_GMAC_REG_ADDR_MAR31H (0x0878)
+#define OGMA_GMAC_REG_ADDR_MAR31L (0x087c)
+
+/**
+ * GMAC MAC Management Counters(Option) register
+ */
+#define OGMA_GMAC_REG_ADDR_MMC_CNTL (0x0100)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_RX (0x0104)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_TX (0x0108)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX (0x010c)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX (0x0110)
+#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB (0x0114)
+#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB (0x0118)
+#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G (0x011c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G (0x0120)
+#define OGMA_GMAC_REG_ADDR_TX64OCTETS_GB (0x0124)
+#define OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB (0x0128)
+#define OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB (0x012c)
+#define OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB (0x0130)
+#define OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB (0x0134)
+#define OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB (0x0138)
+#define OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB (0x013c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB (0x0140)
+#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB (0x0144)
+#define OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR (0x0148)
+#define OGMA_GMAC_REG_ADDR_TXSINGLECOL_G (0x014c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICOL_G (0x0150)
+#define OGMA_GMAC_REG_ADDR_TXDEFERRED (0x0154)
+#define OGMA_GMAC_REG_ADDR_TXLATECOL (0x0158)
+#define OGMA_GMAC_REG_ADDR_TXEXESSCOL (0x015c)
+#define OGMA_GMAC_REG_ADDR_TXCARRIERERRROR (0x0160)
+#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G (0x0164)
+#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G (0x0168)
+#define OGMA_GMAC_REG_ADDR_TXEXECESSDEF (0x016c)
+#define OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES (0x0170)
+#define OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G (0x0174)
+#define OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB (0x0180)
+#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB (0x0184)
+#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G (0x0188)
+#define OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G (0x018c)
+#define OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G (0x0190)
+#define OGMA_GMAC_REG_ADDR_RXCRCERROR (0x0194)
+#define OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR (0x0198)
+#define OGMA_GMAC_REG_ADDR_RXRUNTERROR (0x019c)
+#define OGMA_GMAC_REG_ADDR_RXJABBERERROR (0x01a0)
+#define OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G (0x01a4)
+#define OGMA_GMAC_REG_ADDR_RXOVERSIZE_G (0x01a8)
+#define OGMA_GMAC_REG_ADDR_RX64OCTETS_GB (0x01ac)
+#define OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB (0x01b0)
+#define OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB (0x01b4)
+#define OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB (0x01b8)
+#define OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB (0x01bc)
+#define OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB (0x01c0)
+#define OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G (0x01c4)
+#define OGMA_GMAC_REG_ADDR_RXLENGTHERROR (0x01c8)
+#define OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE (0x01cc)
+#define OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES (0x01d0)
+#define OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW (0x01d4)
+#define OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB (0x01d8)
+#define OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR (0x01dc)
+#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX (0x0200)
+#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX (0x0208)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS (0x0210)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS (0x0214)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS (0x0218)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS (0x021c)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS (0x0220)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS (0x0224)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS (0x0228)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS (0x022c)
+#define OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS (0x0230)
+#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS (0x0234)
+#define OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS (0x0238)
+#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS (0x023c)
+#define OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS (0x0240)
+#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS (0x0244)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS (0x0250)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS (0x0254)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS (0x0258)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS (0x025c)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS (0x0260)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS (0x0264)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS (0x0268)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS (0x026c)
+#define OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS (0x0270)
+#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS (0x0274)
+#define OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS (0x0278)
+#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS (0x027c)
+#define OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS (0x0280)
+#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS (0x0284)
+/**
+ * GMAC DMA register
+ */
+#define OGMA_GMAC_REG_ADDR_BMR (0x1000)
+#define OGMA_GMAC_REG_ADDR_TPDR (0x1004)
+#define OGMA_GMAC_REG_ADDR_RPDR (0x1008)
+#define OGMA_GMAC_REG_ADDR_RDLAR (0x100c)
+#define OGMA_GMAC_REG_ADDR_TDLAR (0x1010)
+#define OGMA_GMAC_REG_ADDR_SR (0x1014)
+#define OGMA_GMAC_REG_ADDR_OMR (0x1018)
+#define OGMA_GMAC_REG_ADDR_IER (0x101c)
+#define OGMA_GMAC_REG_ADDR_MFOCR (0x1020)
+#define OGMA_GMAC_REG_ADDR_RIWTR (0x1024)
+#define OGMA_GMAC_REG_ADDR_AHBSR (0x102c)
+#define OGMA_GMAC_REG_ADDR_CHTDR (0x1048)
+#define OGMA_GMAC_REG_ADDR_CHRDR (0x104c)
+#define OGMA_GMAC_REG_ADDR_CHTBAR (0x1050)
+#define OGMA_GMAC_REG_ADDR_CHRBAR (0x1054)
+
+#endif /* OGMA_REG_F_GMAC_4MT_H */
new file mode 100644
@@ -0,0 +1,368 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_REG_NETSEC_H
+#define OGMA_REG_NETSEC_H
+
+#define OGMA_REG_ADDR_SOFT_RST (0x41)
+#define OGMA_REG_ADDR_COM_INIT (0x48)
+#define OGMA_REG_ADDR_MC_BASE_ADDR (0x97)
+#define OGMA_REG_ADDR_DMAC_HM_CMD_BUF (0x84)
+#define OGMA_REG_ADDR_DMAC_MC_ADDR_MH (0x89)
+#define OGMA_REG_ADDR_DMAC_MC_SIZE_MH (0x8A)
+#define OGMA_REG_ADDR_PKTC_CMD_BUF (0x34)
+#define OGMA_REG_ADDR_PKTC_MC_ADDR (0x5C)
+#define OGMA_REG_ADDR_PKTC_MC_SIZE (0x5D)
+#define OGMA_REG_ADDR_DIS_CORE (0x86)
+#define OGMA_REG_ADDR_DMA_HM_CTRL (0x85)
+#define OGMA_REG_ADDR_DMA_MH_CTRL (0x88)
+#define OGMA_REG_ADDR_CLK_EN_0 (0x40)
+#define OGMA_REG_ADDR_CLK_EN_1 (0x64)
+#define OGMA_REG_ADDR_PKT_CTRL (0x50)
+#define OGMA_REG_ADDR_NRM_TX_DESC_START_UP (0x10D)
+#define OGMA_REG_ADDR_NRM_TX_DESC_START_LW (0x102)
+#define OGMA_REG_ADDR_NRM_RX_DESC_START_UP (0x11D)
+#define OGMA_REG_ADDR_NRM_RX_DESC_START_LW (0x112)
+#define OGMA_REG_ADDR_TAIKI_RX_DESC_START_UP (0x12D)
+#define OGMA_REG_ADDR_TAIKI_RX_DESC_START_LW (0x122)
+#define OGMA_REG_ADDR_TAIKI_TX_DESC_START_UP (0x13D)
+#define OGMA_REG_ADDR_TAIKI_TX_DESC_START_LW (0x132)
+#define OGMA_REG_ADDR_MISC_RX_DESC_START_UP (0x14D)
+#define OGMA_REG_ADDR_MISC_RX_DESC_START_LW (0x142)
+#define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_UP (0x15D)
+#define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_LW (0x152)
+#define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_UP (0x16D)
+#define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_LW (0x162)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_UP (0x17D)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_LW (0x172)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_UP (0x18D)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_LW (0x182)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_UP (0x19D)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_LW (0x192)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_UP (0x1AD)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_LW (0x1A2)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_UP (0x1BD)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_LW (0x1B2)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_UP (0x1CD)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_LW (0x1C2)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_UP (0x1DD)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_LW (0x1D2)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_UP (0x1ED)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_LW (0x1E2)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_UP (0x20D)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_LW (0x202)
+#define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_UP (0x21D)
+#define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_LW (0x212)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_UP (0x22D)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_LW (0x222)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_UP (0x23D)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_LW (0x232)
+#define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_UP (0x24D)
+#define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_LW (0x242)
+#define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_UP (0x25D)
+#define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_LW (0x252)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_UP (0x26D)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_LW (0x262)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_UP (0x27D)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_LW (0x272)
+#define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_UP (0x28D)
+#define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_LW (0x282)
+#define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_UP (0x29D)
+#define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_LW (0x292)
+#define OGMA_REG_ADDR_NRM_TX_CONFIG (0x10C)
+#define OGMA_REG_ADDR_NRM_RX_CONFIG (0x11C)
+#define OGMA_REG_ADDR_TAIKI_RX_CONFIG (0x12C)
+#define OGMA_REG_ADDR_TAIKI_TX_CONFIG (0x13C)
+#define OGMA_REG_ADDR_MISC_RX_CONFIG (0x14C)
+#define OGMA_REG_ADDR_WL_NRM_TX_CONFIG (0x15C)
+#define OGMA_REG_ADDR_WL_NRM_RX_CONFIG (0x16C)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_CONFIG (0x17C)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_CONFIG (0x18C)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_CONFIG (0x19C)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_CONFIG (0x1AC)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_CONFIG (0x1BC)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_CONFIG (0x1CC)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_CONFIG (0x1DC)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_CONFIG (0x1EC)
+#define OGMA_REG_ADDR_DEC_PKT_TX_CONFIG (0x20C)
+#define OGMA_REG_ADDR_ENC_PKT_RX_CONFIG (0x21C)
+#define OGMA_REG_ADDR_ENC_TLS_TX_CONFIG (0x22C)
+#define OGMA_REG_ADDR_DEC_TLS_TX_CONFIG (0x23C)
+#define OGMA_REG_ADDR_ENC_TLS_RX_CONFIG (0x24C)
+#define OGMA_REG_ADDR_DEC_TLS_RX_CONFIG (0x25C)
+#define OGMA_REG_ADDR_ENC_RAW_TX_CONFIG (0x26C)
+#define OGMA_REG_ADDR_DEC_RAW_TX_CONFIG (0x27C)
+#define OGMA_REG_ADDR_ENC_RAW_RX_CONFIG (0x28C)
+#define OGMA_REG_ADDR_DEC_RAW_RX_CONFIG (0x29C)
+#define OGMA_REG_ADDR_DMA_TMR_CTRL (0x83)
+#define OGMA_REG_ADDR_TOP_STATUS (0x80)
+#define OGMA_REG_ADDR_TOP_INTEN_A (0x81)
+#define OGMA_REG_ADDR_TOP_INTEN_A_SET (0x8D)
+#define OGMA_REG_ADDR_TOP_INTEN_A_CLR (0x8E)
+#define OGMA_REG_ADDR_TOP_INTEN_B (0x8F)
+#define OGMA_REG_ADDR_TOP_INTEN_B_SET (0x90)
+#define OGMA_REG_ADDR_TOP_INTEN_B_CLR (0x91)
+#define OGMA_REG_ADDR_PKT_STATUS (0x3)
+#define OGMA_REG_ADDR_PKT_INTEN (0x4)
+#define OGMA_REG_ADDR_PKT_INTEN_SET (0x7)
+#define OGMA_REG_ADDR_PKT_INTEN_CLR (0x8)
+#define OGMA_REG_ADDR_TLS_STATUS (0x5)
+#define OGMA_REG_ADDR_TLS_INTEN (0x6)
+#define OGMA_REG_ADDR_TLS_INTEN_SET (0x9)
+#define OGMA_REG_ADDR_TLS_INTEN_CLR (0xA)
+#define OGMA_REG_ADDR_SLAVE_0_STATUS (0xB)
+#define OGMA_REG_ADDR_SLAVE_0_INTEN (0xC)
+#define OGMA_REG_ADDR_SLAVE_0_INTEN_SET (0xD)
+#define OGMA_REG_ADDR_SLAVE_0_INTEN_CLR (0xE)
+#define OGMA_REG_ADDR_SLAVE_1_STATUS (0xF)
+#define OGMA_REG_ADDR_SLAVE_1_INTEN (0x10)
+#define OGMA_REG_ADDR_SLAVE_1_INTEN_SET (0x11)
+#define OGMA_REG_ADDR_SLAVE_1_INTEN_CLR (0x12)
+#define OGMA_REG_ADDR_MAC_STATUS (0x409)
+#define OGMA_REG_ADDR_MAC_INTEN (0x40A)
+#define OGMA_REG_ADDR_MAC_TX_RX_INFO_STATUS (0x486)
+#define OGMA_REG_ADDR_MAC_TX_RX_INFO_INTEN (0x487)
+#define OGMA_REG_ADDR_NRM_TX_STATUS (0x100)
+#define OGMA_REG_ADDR_NRM_TX_INTEN (0x101)
+#define OGMA_REG_ADDR_NRM_TX_INTEN_SET (0x10A)
+#define OGMA_REG_ADDR_NRM_TX_INTEN_CLR (0x10B)
+#define OGMA_REG_ADDR_NRM_RX_STATUS (0x110)
+#define OGMA_REG_ADDR_NRM_RX_INTEN (0x111)
+#define OGMA_REG_ADDR_NRM_RX_INTEN_SET (0x11A)
+#define OGMA_REG_ADDR_NRM_RX_INTEN_CLR (0x11B)
+#define OGMA_REG_ADDR_TAIKI_RX_STATUS (0x120)
+#define OGMA_REG_ADDR_TAIKI_RX_INTEN (0x121)
+#define OGMA_REG_ADDR_TAIKI_RX_INTEN_SET (0x12A)
+#define OGMA_REG_ADDR_TAIKI_RX_INTEN_CLR (0x12B)
+#define OGMA_REG_ADDR_TAIKI_TX_STATUS (0x130)
+#define OGMA_REG_ADDR_TAIKI_TX_INTEN (0x131)
+#define OGMA_REG_ADDR_TAIKI_TX_INTEN_SET (0x13A)
+#define OGMA_REG_ADDR_TAIKI_TX_INTEN_CLR (0x13B)
+#define OGMA_REG_ADDR_MISC_RX_STATUS (0x140)
+#define OGMA_REG_ADDR_MISC_RX_INTEN (0x141)
+#define OGMA_REG_ADDR_MISC_RX_INTEN_SET (0x14A)
+#define OGMA_REG_ADDR_MISC_RX_INTEN_CLR (0x14B)
+#define OGMA_REG_ADDR_WL_NRM_TX_STATUS (0x150)
+#define OGMA_REG_ADDR_WL_NRM_TX_INTEN (0x151)
+#define OGMA_REG_ADDR_WL_NRM_TX_INTEN_SET (0x15A)
+#define OGMA_REG_ADDR_WL_NRM_TX_INTEN_CLR (0x15B)
+#define OGMA_REG_ADDR_WL_NRM_RX_STATUS (0x160)
+#define OGMA_REG_ADDR_WL_NRM_RX_INTEN (0x161)
+#define OGMA_REG_ADDR_WL_NRM_RX_INTEN_SET (0x16A)
+#define OGMA_REG_ADDR_WL_NRM_RX_INTEN_CLR (0x16B)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_STATUS (0x170)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN (0x171)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_SET (0x17A)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_CLR (0x17B)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_STATUS (0x180)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN (0x181)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_SET (0x18A)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_CLR (0x18B)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_STATUS (0x190)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN (0x191)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_SET (0x19A)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_CLR (0x19B)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_STATUS (0x1A0)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN (0x1A1)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_SET (0x1AA)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_CLR (0x1AB)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_STATUS (0x1B0)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN (0x1B1)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_SET (0x1BA)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_CLR (0x1BB)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_STATUS (0x1C0)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN (0x1C1)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_SET (0x1CA)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_CLR (0x1CB)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_STATUS (0x1D0)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN (0x1D1)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_SET (0x1DA)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_CLR (0x1DB)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_STATUS (0x1E0)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN (0x1E1)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_SET (0x1EA)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_CLR (0x1EB)
+#define OGMA_REG_ADDR_DEC_TX_STATUS (0x200)
+#define OGMA_REG_ADDR_DEC_TX_INTEN (0x201)
+#define OGMA_REG_ADDR_DEC_TX_INTEN_SET (0x20A)
+#define OGMA_REG_ADDR_DEC_TX_INTEN_CLR (0x20B)
+#define OGMA_REG_ADDR_ENC_RX_STATUS (0x210)
+#define OGMA_REG_ADDR_ENC_RX_INTEN (0x211)
+#define OGMA_REG_ADDR_ENC_RX_INTEN_SET (0x21A)
+#define OGMA_REG_ADDR_ENC_RX_INTEN_CLR (0x21B)
+#define OGMA_REG_ADDR_ENC_TLS_TX_STATUS (0x220)
+#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN (0x221)
+#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_SET (0x22A)
+#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_CLR (0x22B)
+#define OGMA_REG_ADDR_DEC_TLS_TX_STATUS (0x230)
+#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN (0x231)
+#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_SET (0x23A)
+#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_CLR (0x23B)
+#define OGMA_REG_ADDR_ENC_TLS_RX_STATUS (0x240)
+#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN (0x241)
+#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_SET (0x24A)
+#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_CLR (0x24B)
+#define OGMA_REG_ADDR_DEC_TLS_RX_STATUS (0x250)
+#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN (0x251)
+#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_SET (0x25A)
+#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_CLR (0x25B)
+#define OGMA_REG_ADDR_ENC_RAW_TX_STATUS (0x260)
+#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN (0x261)
+#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_SET (0x26A)
+#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_CLR (0x26B)
+#define OGMA_REG_ADDR_DEC_RAW_TX_STATUS (0x270)
+#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN (0x271)
+#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_SET (0x27A)
+#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_CLR (0x27B)
+#define OGMA_REG_ADDR_ENC_RAW_RX_STATUS (0x280)
+#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN (0x281)
+#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_SET (0x28A)
+#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_CLR (0x28B)
+#define OGMA_REG_ADDR_DEC_RAW_RX_STATUS (0x290)
+#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN (0x291)
+#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_SET (0x29A)
+#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_CLR (0x29B)
+#define OGMA_REG_ADDR_NRM_TX_PKTCNT (0x104)
+#define OGMA_REG_ADDR_TAIKI_TX_PKTCNT (0x134)
+#define OGMA_REG_ADDR_WL_NRM_TX_PKTCNT (0x154)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_PKTCNT (0x1A4)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_PKTCNT (0x174)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_PKTCNT (0x1C4)
+#define OGMA_REG_ADDR_DEC_PKT_TX_PKTCNT (0x204)
+#define OGMA_REG_ADDR_ENC_TLS_TX_PKTCNT (0x224)
+#define OGMA_REG_ADDR_DEC_TLS_TX_PKTCNT (0x234)
+#define OGMA_REG_ADDR_ENC_RAW_TX_PKTCNT (0x264)
+#define OGMA_REG_ADDR_DEC_RAW_TX_PKTCNT (0x274)
+#define OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT (0x105)
+#define OGMA_REG_ADDR_TAIKI_TX_DONE_PKTCNT (0x135)
+#define OGMA_REG_ADDR_WL_NRM_TX_DONE_PKTCNT (0x155)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_PKTCNT (0x1A5)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_PKTCNT (0x175)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_PKTCNT (0x1C5)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DONE_PKTCNT (0x205)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DONE_PKTCNT (0x225)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DONE_PKTCNT (0x235)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DONE_PKTCNT (0x265)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DONE_PKTCNT (0x275)
+#define OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT (0x106)
+#define OGMA_REG_ADDR_TAIKI_TX_DONE_TXINT_PKTCNT (0x136)
+#define OGMA_REG_ADDR_WL_NRM_TX_DONE_TXINT_PKTCNT (0x156)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_TXINT_PKTCNT (0x1A6)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_TXINT_PKTCNT (0x176)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_TXINT_PKTCNT (0x1C6)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DONE_TXINT_PKTCNT (0x206)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DONE_TXINT_PKTCNT (0x226)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DONE_TXINT_PKTCNT (0x236)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DONE_TXINT_PKTCNT (0x266)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DONE_TXINT_PKTCNT (0x276)
+#define OGMA_REG_ADDR_NRM_TX_TMR (0x107)
+#define OGMA_REG_ADDR_TAIKI_TX_TMR (0x137)
+#define OGMA_REG_ADDR_WL_NRM_TX_TMR (0x157)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_TMR (0x177)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_TMR (0x1A7)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TMR (0x1C7)
+#define OGMA_REG_ADDR_DEC_TX_TMR (0x207)
+#define OGMA_REG_ADDR_NRM_TX_TXINT_TMR (0x108)
+#define OGMA_REG_ADDR_TAIKI_TX_TXINT_TMR (0x138)
+#define OGMA_REG_ADDR_WL_NRM_TX_TXINT_TMR (0x158)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_TXINT_TMR (0x178)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_TXINT_TMR (0x1A8)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TXINT_TMR (0x1C8)
+#define OGMA_REG_ADDR_DEC_TX_TXINT_TMR (0x208)
+#define OGMA_REG_ADDR_NRM_RX_PKTCNT (0x115)
+#define OGMA_REG_ADDR_TAIKI_RX_PKTCNT (0x125)
+#define OGMA_REG_ADDR_MISC_RX_PKTCNT (0x145)
+#define OGMA_REG_ADDR_WL_NRM_RX_PKTCNT (0x165)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_PKTCNT (0x185)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_PKTCNT (0x195)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_PKTCNT (0x1B5)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_PKTCNT (0x1D5)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_PKTCNT (0x1E5)
+#define OGMA_REG_ADDR_ENC_PKT_RX_PKTCNT (0x215)
+#define OGMA_REG_ADDR_ENC_TLS_RX_PKTCNT (0x245)
+#define OGMA_REG_ADDR_DEC_TLS_RX_PKTCNT (0x255)
+#define OGMA_REG_ADDR_ENC_RAW_RX_PKTCNT (0x285)
+#define OGMA_REG_ADDR_DEC_RAW_RX_PKTCNT (0x295)
+#define OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT (0x116)
+#define OGMA_REG_ADDR_TAIKI_RXINT_PKTCNT (0x126)
+#define OGMA_REG_ADDR_MISC_RXINT_PKTCNT (0x146)
+#define OGMA_REG_ADDR_WL_NRM_RXINT_PKTCNT (0x166)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RXINT_PKTCNT (0x186)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RXINT_PKTCNT (0x196)
+#define OGMA_REG_ADDR_WL_TAIKI_RXINT_PKTCNT (0x1B6)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RXINT_PKTCNT (0x1D6)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RXINT_PKTCNT (0x1E6)
+#define OGMA_REG_ADDR_ENC_PKT_RXINT_PKTCNT (0x216)
+#define OGMA_REG_ADDR_ENC_TLS_RXINT_PKTCNT (0x246)
+#define OGMA_REG_ADDR_DEC_TLS_RXINT_PKTCNT (0x256)
+#define OGMA_REG_ADDR_ENC_RAW_RXINT_PKTCNT (0x286)
+#define OGMA_REG_ADDR_DEC_RAW_RXINT_PKTCNT (0x296)
+#define OGMA_REG_ADDR_NRM_RX_TMR (0x117)
+#define OGMA_REG_ADDR_TAIKI_RX_TMR (0x127)
+#define OGMA_REG_ADDR_MISC_RX_TMR (0x147)
+#define OGMA_REG_ADDR_WL_NRM_RX_TMR (0x167)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_TMR (0x187)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_TMR (0x197)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_TMR (0x1B7)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_TMR (0x1D7)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_TMR (0x1E7)
+#define OGMA_REG_ADDR_NRM_RX_RXINT_TMR (0x118)
+#define OGMA_REG_ADDR_TAIKI_RX_RXINT_TMR (0x128)
+#define OGMA_REG_ADDR_MISC_RX_RXINT_TMR (0x148)
+#define OGMA_REG_ADDR_WL_NRM_RX_RXINT_TMR (0x168)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_RXINT_TMR (0x188)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_RXINT_TMR (0x198)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_RXINT_TMR (0x1B8)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_RXINT_TMR (0x1D8)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_RXINT_TMR (0x1E8)
+#define OGMA_REG_ADDR_PODB_CMD_ST (0x20)
+#define OGMA_REG_ADDR_PODB_DATA (0x21)
+#define OGMA_REG_ADDR_CLS_VAL_CMD (0x2A)
+#define OGMA_REG_ADDR_CLS_VAL_DATA (0x2B)
+#define OGMA_REG_ADDR_CLS_CMD_ST (0x2C)
+#define OGMA_REG_ADDR_CLS_DATA (0x2D)
+#define OGMA_REG_ADDR_SADB_CMD_ST (0x2E)
+#define OGMA_REG_ADDR_SADB_DATA (0x2F)
+#define OGMA_REG_ADDR_MAC_CMD (0x471)
+#define OGMA_REG_ADDR_MAC_DATA (0x470)
+#define OGMA_REG_ADDR_MAC_FLOW_TH (0x473)
+#define OGMA_REG_ADDR_MAC_INTF_SEL (0x475)
+#define OGMA_REG_ADDR_MAC_TX_TSTAMP_LW (0x476)
+#define OGMA_REG_ADDR_MAC_TX_TSTAMP_UP (0x477)
+#define OGMA_REG_ADDR_MAC_CAP_TSTAMP_UP (0x478)
+#define OGMA_REG_ADDR_MAC_CAP_TSTAMP_LW (0x479)
+#define OGMA_REG_ADDR_MAC_TSTAM_CAP (0x47A)
+#define OGMA_REG_ADDR_MAC_SNAP_TRIG (0x47B)
+#define OGMA_REG_ADDR_MAC_SEC_CNT (0x47C)
+#define OGMA_REG_ADDR_MAC_DESC_INIT (0x47F)
+#define OGMA_REG_ADDR_MAC_TX_TS_GET (0x480)
+#define OGMA_REG_ADDR_MAC_DESC_SOFT_RST (0x481)
+#define OGMA_REG_ADDR_IV_INIT_VAL (0x45)
+#define OGMA_REG_ADDR_MAC_ADD_UP (0x43)
+#define OGMA_REG_ADDR_MAC_ADD_LW (0x44)
+#define OGMA_REG_ADDR_ST_INFO_ST_UP (0x65)
+#define OGMA_REG_ADDR_ST_INFO_ST_LW (0x66)
+#define OGMA_REG_ADDR_ST_INFO_SIZE (0x67)
+#define OGMA_REG_ADDR_ST_INFO_TX_ST (0x68)
+#define OGMA_REG_ADDR_LOGIC_GR_ID (0x69)
+#define OGMA_REG_ADDR_ST_FOR_PBC (0x6A)
+#define OGMA_REG_ADDR_ALARM_INFO (0x6B)
+#define OGMA_REG_ADDR_MC_VER (0x8B)
+#define OGMA_REG_ADDR_HW_VER (0x8C)
+
+#define OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS (0x140)
+
+#endif /* OGMA_REG_F_TAIKI_H */
+
new file mode 100644
@@ -0,0 +1,25 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_CONFIG_H
+#define OGMA_CONFIG_H
+
+#define OGMA_CONFIG_CLK_HZ 125000000UL
+#define OGMA_CONFIG_GMAC_CLK_HZ 125000000UL
+#define OGMA_CONFIG_CHECK_CLK_SUPPLY
+
+#define OGMA_CONFIG_USE_READ_GMAC_STAT
+
+#endif /* OGMA_CONFIG_H */
new file mode 100644
@@ -0,0 +1,263 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PFDEP_H
+#define PFDEP_H
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+
+#include <Protocol/Cpu.h>
+
+extern EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+/**********************************************************************
+ * Constant definitions
+ **********************************************************************/
+#define PFDEP_INT64_AVAILABLE
+
+/**********************************************************************
+ * Elementary type definitions
+ **********************************************************************/
+typedef INT8 pfdep_int8;
+typedef UINT8 pfdep_uint8;
+typedef INT16 pfdep_int16;
+typedef UINT16 pfdep_uint16;
+typedef INT32 pfdep_int32;
+typedef UINT32 pfdep_uint32;
+typedef INT64 pfdep_int64;
+typedef UINT64 pfdep_uint64;
+typedef BOOLEAN pfdep_bool;
+typedef CHAR8 pfdep_char;
+
+#define PFDEP_TRUE ((pfdep_bool)1)
+#define PFDEP_FALSE ((pfdep_bool)0)
+
+
+/**********************************************************************
+ * Complex type definitions
+ **********************************************************************/
+
+typedef enum pfdep_err_e {
+ PFDEP_ERR_OK = 0,
+ PFDEP_ERR_PARAM,
+ PFDEP_ERR_ALLOC,
+ PFDEP_ERR_INTERRUPT
+} pfdep_err_t;
+
+
+typedef struct {
+ LIST_ENTRY Link;
+ VOID *Buffer;
+ VOID *Mapping;
+ BOOLEAN RecycleForTx;
+ BOOLEAN Released;
+} PACKET_HANDLE;
+
+typedef VOID *pfdep_dev_handle_t;
+typedef PACKET_HANDLE *pfdep_pkt_handle_t;
+typedef EFI_PHYSICAL_ADDRESS pfdep_phys_addr_t;
+typedef UINT64 pfdep_cpu_addr_t;
+
+typedef int pfdep_hard_lock_t;
+typedef int pfdep_soft_lock_t;
+
+typedef BOOLEAN pfdep_hard_lock_ctx_t;
+typedef int pfdep_soft_lock_ctx_t;
+
+typedef unsigned int pfdep_debug_level_t;
+
+#define PFDEP_DEBUG_LEVEL_FATAL ((pfdep_debug_level_t)1)
+#define PFDEP_DEBUG_LEVEL_WARNING ((pfdep_debug_level_t)2)
+#define PFDEP_DEBUG_LEVEL_NOTICE ((pfdep_debug_level_t)3)
+#define PFDEP_DEBUG_LEVEL_DEBUG ((pfdep_debug_level_t)4)
+#define PFDEP_DEBUG_LEVEL_DEBUG_DETAILED ((pfdep_debug_level_t)5)
+#define PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED ((pfdep_debug_level_t)6)
+
+/**********************************************************************
+ * Variable declarations
+ **********************************************************************/
+extern pfdep_debug_level_t pfdep_debug_level; /* defined in pfdep_uefi.c */
+
+
+/**********************************************************************
+ * Function declarations
+ **********************************************************************/
+
+static __inline pfdep_uint32 pfdep_iomem_read(void *addr)
+{
+ return *((volatile pfdep_uint32 *)(addr));
+}
+
+static __inline void pfdep_iomem_write(void *addr, pfdep_uint32 val)
+{
+ *((volatile pfdep_uint32 *)(addr)) = val;
+
+
+}
+
+#define pfdep_read_mem_barrier() MemoryFence()
+#define pfdep_write_mem_barrier() MemoryFence()
+#define pfdep_mem_barrier() MemoryFence()
+
+void *pfdep_malloc(pfdep_uint32 len);
+
+void pfdep_free(void *addr);
+
+pfdep_err_t pfdep_dma_malloc (
+ pfdep_dev_handle_t dev_handle,
+ pfdep_uint32 len,
+ void **addr_p,
+ pfdep_phys_addr_t *phys_addr_p
+ );
+
+void pfdep_dma_free (
+ pfdep_dev_handle_t dev_handle,
+ pfdep_uint32 len,
+ void *addr,
+ pfdep_phys_addr_t phys_addr
+ );
+
+pfdep_err_t pfdep_alloc_pkt_buf (
+ pfdep_dev_handle_t dev_handle,
+ pfdep_uint16 len,
+ void **addr_p,
+ pfdep_phys_addr_t *phys_addr_p,
+ pfdep_pkt_handle_t *pkt_handle_p
+ );
+
+void pfdep_free_pkt_buf (
+ pfdep_dev_handle_t dev_handle,
+ pfdep_uint16 len,
+ void *addr,
+ pfdep_phys_addr_t phys_addr,
+ pfdep_bool last_flag,
+ pfdep_pkt_handle_t pkt_handle
+ );
+
+static __inline pfdep_err_t pfdep_init_hard_lock(pfdep_hard_lock_t *hard_lock_p)
+{
+ (void)hard_lock_p; /* suppress compiler warning */
+ return PFDEP_ERR_OK;
+}
+
+static __inline void pfdep_uninit_hard_lock(pfdep_hard_lock_t *hard_lock_p)
+{
+ (void)hard_lock_p; /* suppress compiler warning */
+ return;
+}
+
+static __inline void pfdep_acquire_hard_lock (
+ pfdep_hard_lock_t *hard_lock_p, /* not used */
+ pfdep_hard_lock_ctx_t *ctx_p
+ )
+{
+ (void)hard_lock_p; /* suppress compiler warning */
+
+ *ctx_p = SaveAndDisableInterrupts();
+}
+
+
+static __inline void pfdep_release_hard_lock (
+ pfdep_hard_lock_t *hard_lock_p, /* not used */
+ pfdep_hard_lock_ctx_t *ctx_p
+ )
+{
+ (void)hard_lock_p; /* suppress compiler warning */
+
+ SetInterruptState(*ctx_p);
+}
+
+static __inline pfdep_err_t pfdep_init_soft_lock (
+ pfdep_soft_lock_t *soft_lock_p
+ )
+{
+ *soft_lock_p = 0; /* suppress compiler warning */
+
+ return PFDEP_ERR_OK;
+}
+
+static __inline void pfdep_uninit_soft_lock (
+ pfdep_soft_lock_t *soft_lock_p
+ )
+{
+ (void)soft_lock_p; /* suppress compiler warning */
+
+ return;
+}
+
+static __inline pfdep_err_t pfdep_acquire_soft_lock (
+ pfdep_soft_lock_t *soft_lock_p,
+ pfdep_soft_lock_ctx_t *ctx_p
+ )
+{
+ (void)soft_lock_p; /* suppress compiler warning */
+ (void)ctx_p; /* suppress compiler warning */
+
+ return PFDEP_ERR_OK;
+}
+
+static __inline void pfdep_release_soft_lock (
+ pfdep_soft_lock_t *soft_lock_p,
+ pfdep_soft_lock_ctx_t *ctx_p
+ )
+{
+ (void)soft_lock_p; /* suppress compiler warning */
+ (void)ctx_p; /* suppress compiler warning */
+}
+
+
+static __inline void pfdep_memcpy(void *dst_p, const void *src_p, pfdep_uint32 len)
+{
+ CopyMem (dst_p, src_p, (UINTN)len);
+}
+
+static __inline void pfdep_memset(void *dst_p, pfdep_uint8 c, pfdep_uint32 len)
+{
+ SetMem (dst_p, (UINTN)len, c);
+}
+
+static __inline pfdep_err_t pfdep_msleep(pfdep_uint32 wait_ms)
+{
+
+ MicroSecondDelay ((UINTN)wait_ms * 1000);
+
+ return PFDEP_ERR_OK;
+}
+
+#define pfdep_print(level,...) \
+do { \
+ if (level <= pfdep_debug_level) { \
+ DEBUG ((DEBUG_INFO, "[NETSEC] " __VA_ARGS__)); \
+ } \
+} while (0)
+
+
+static __inline pfdep_debug_level_t pfdep_get_debug_level(void)
+{
+ return pfdep_debug_level;
+}
+
+static __inline void pfdep_set_debug_level(pfdep_debug_level_t level)
+{
+ pfdep_debug_level = level;
+}
+
+
+#define pfdep_assert(cond) ASSERT(cond)
+
+#endif /* PFDEP_H */
new file mode 100644
@@ -0,0 +1,176 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "pfdep.h"
+
+#include <Library/DebugLib.h>
+#include <Library/DmaLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NetLib.h>
+#include <Library/SynchronizationLib.h>
+
+/**********************************************************************
+ * Variable definitions
+ **********************************************************************/
+pfdep_debug_level_t pfdep_debug_level = PFDEP_DEBUG_LEVEL_NOTICE;
+
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+VOID*
+pfdep_malloc (
+ IN pfdep_uint32 len
+ )
+{
+ return AllocatePool (len);
+}
+
+VOID
+pfdep_free (
+ IN VOID *addr
+ )
+{
+ FreePool (addr);
+}
+
+pfdep_err_t
+pfdep_dma_malloc (
+ IN pfdep_dev_handle_t dev_handle,
+ IN pfdep_uint32 len,
+ OUT VOID **addr_p,
+ OUT pfdep_phys_addr_t *phys_addr_p
+ )
+{
+ EFI_STATUS Status;
+ UINTN NumPages;
+ UINTN NumBytes;
+ VOID **Mapping;
+
+ NumPages = EFI_SIZE_TO_PAGES (ALIGN_VARIABLE(len) + sizeof *Mapping);
+ Status = DmaAllocateBuffer (EfiBootServicesData, NumPages, addr_p);
+ if (EFI_ERROR (Status)) {
+ return PFDEP_ERR_ALLOC;
+ }
+
+ //
+ // Stash the address of the MAPINFO struct at the end of the buffer,
+ // but make sure it appears aligned (the memory may be mapped uncached)
+ //
+ Mapping = (VOID **)((UINTN)*addr_p + ALIGN_VARIABLE(len));
+
+ NumBytes = EFI_PAGES_TO_SIZE (NumPages);
+ Status = DmaMap (MapOperationBusMasterCommonBuffer, *addr_p, &NumBytes,
+ phys_addr_p, Mapping);
+
+ if (EFI_ERROR (Status) || NumBytes < len) {
+ DmaFreeBuffer (NumPages, *addr_p);
+ return PFDEP_ERR_ALLOC;
+ }
+
+ return PFDEP_ERR_OK;
+}
+
+VOID
+pfdep_dma_free (
+ IN pfdep_dev_handle_t dev_handle,
+ IN pfdep_uint32 len,
+ IN VOID *addr,
+ IN pfdep_phys_addr_t phys_addr
+ )
+{
+ VOID *Mapping;
+
+ Mapping = *(VOID **)((UINTN)addr + ALIGN_VARIABLE(len));
+
+ DmaUnmap (Mapping);
+ DmaFreeBuffer (EFI_SIZE_TO_PAGES (ALIGN_VARIABLE(len) + sizeof Mapping),
+ addr);
+}
+
+//
+// On the receive path, we allocate a new packet and link it into the RX ring
+// before returning the received packet to the caller. This means we perform
+// one allocation and one free operation for each buffer received.
+// So let's cache a single packet, and get rid of most of the alloc/free
+// overhead on the RX path.
+//
+STATIC pfdep_pkt_handle_t mSparePacketBuffer;
+STATIC UINT32 mSparePacketBufferSize;
+
+pfdep_err_t
+pfdep_alloc_pkt_buf (
+ IN pfdep_dev_handle_t dev_handle,
+ IN pfdep_uint16 len,
+ OUT VOID **addr_p,
+ OUT pfdep_phys_addr_t *phys_addr_p,
+ OUT pfdep_pkt_handle_t *pkt_handle_p
+ )
+{
+ EFI_STATUS Status;
+ UINTN NumBytes;
+
+ NumBytes = ALIGN_VALUE (len, mCpu->DmaBufferAlignment);
+
+ if (InterlockedCompareExchange32 (&mSparePacketBufferSize, len, 0) == len) {
+ *pkt_handle_p = mSparePacketBuffer;
+ } else {
+ *pkt_handle_p = AllocateZeroPool (NumBytes + sizeof(PACKET_HANDLE) +
+ (mCpu->DmaBufferAlignment - 8));
+ if (*pkt_handle_p == NULL) {
+ return PFDEP_ERR_ALLOC;
+ }
+
+ (*pkt_handle_p)->Buffer = ALIGN_POINTER (*pkt_handle_p,
+ mCpu->DmaBufferAlignment);
+ }
+
+ *addr_p = (*pkt_handle_p)->Buffer;
+ Status = DmaMap (MapOperationBusMasterWrite, *addr_p, &NumBytes, phys_addr_p,
+ &(*pkt_handle_p)->Mapping);
+ if (EFI_ERROR (Status) || NumBytes < len) {
+ FreePool (*pkt_handle_p);
+ return PFDEP_ERR_ALLOC;
+ }
+ return PFDEP_ERR_OK;
+}
+
+VOID
+pfdep_free_pkt_buf (
+ IN pfdep_dev_handle_t dev_handle,
+ IN pfdep_uint16 len,
+ IN VOID *addr,
+ IN pfdep_phys_addr_t phys_addr,
+ IN pfdep_bool last_flag,
+ IN pfdep_pkt_handle_t pkt_handle
+ )
+{
+ if (last_flag != PFDEP_TRUE) {
+ return;
+ }
+
+ if (pkt_handle->Mapping != NULL) {
+ DmaUnmap (pkt_handle->Mapping);
+ }
+
+ if (pkt_handle->RecycleForTx) {
+ pkt_handle->Released = TRUE;
+ } else if (!InterlockedCompareExchange32 (&mSparePacketBufferSize, 0, len)) {
+ mSparePacketBuffer = pkt_handle;
+ } else {
+ FreePool (pkt_handle);
+ }
+}
This adds the NetSecDxe driver provided by Socionext, but reworked extensively to improve compliance with the SimpleNetworkProtocol API, and to avoid uncached allocations for streaming DMA. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c | 1005 ++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec | 47 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h | 83 ++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf | 69 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h | 736 ++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h | 45 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h | 24 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c | 88 ++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h | 52 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c | 1391 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h | 111 ++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c | 1454 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h | 210 +++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c | 1385 +++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h | 38 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h | 219 +++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h | 222 +++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h | 368 +++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 25 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h | 263 ++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c | 176 +++ 21 files changed, 8011 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel