Message ID | 20170916023417.14599-1-richard.henderson@linaro.org |
---|---|
Headers | show |
Series | TCG vectorization and example conversion | expand |
On 09/15/2017 07:34 PM, Richard Henderson wrote: > Now addressing the complex vector op issue. I now expose TCGv_vec > to target front-ends, but opaque wrt the vector size. One can thus > compose vector operations, as demonstrated in target/arm/. > > The actual host vector length now becomes an argument to the *_vec > opcodes. It's a little awkward, but does prevent an explosion of > opcode values. > > All R-b dropped because all patches rewritten or heavily modified. Bah. Forgot to mention that this depends on tcg-next. Full tree at git://github.com/rth7680/qemu.git native-vector-registers-3 r~
Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20170916023417.14599-1-richard.henderson@linaro.org Subject: [Qemu-devel] [PATCH v3 0/6] TCG vectorization and example conversion === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git log --oneline $BASE.. | wc -l) failed=0 git config --local diff.renamelimit 0 git config --local diff.renames True commits="$(git log --format=%H --reverse $BASE..)" for c in $commits; do echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..." if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then failed=1 echo fi n=$((n+1)) done exit $failed === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 7f8bff3639 tcg/aarch64: Add vector operations 107700b998 tcg/i386: Add vector operations 63c5d729cd target/arm: Use vector infrastructure for aa64 add/sub/logic 66bd1ba117 target/arm: Align vector registers bcf88636c0 tcg: Add vector expanders 00e32ea5b2 tcg: Add types and operations for host vectors === OUTPUT BEGIN === Checking PATCH 1/6: tcg: Add types and operations for host vectors... Checking PATCH 2/6: tcg: Add vector expanders... ERROR: spaces required around that '&' (ctx:WxO) #284: FILE: accel/tcg/tcg-runtime-gvec.c:241: + *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i); ^ ERROR: space prohibited after that '~' (ctx:OxW) #284: FILE: accel/tcg/tcg-runtime-gvec.c:241: + *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i); ^ ERROR: spaces required around that '|' (ctx:WxO) #295: FILE: accel/tcg/tcg-runtime-gvec.c:252: + *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i); ^ ERROR: space prohibited after that '~' (ctx:OxW) #295: FILE: accel/tcg/tcg-runtime-gvec.c:252: + *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i); ^ ERROR: trailing statements should be on next line #589: FILE: tcg/tcg-op-gvec.c:198: + } if (TCG_TARGET_REG_BITS == 64) { total: 5 errors, 0 warnings, 1342 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 3/6: target/arm: Align vector registers... Checking PATCH 4/6: target/arm: Use vector infrastructure for aa64 add/sub/logic... Checking PATCH 5/6: tcg/i386: Add vector operations... WARNING: architecture specific defines should be avoided #50: FILE: tcg/i386/tcg-target.h:93: +#ifdef __SSE2__ WARNING: architecture specific defines should be avoided #55: FILE: tcg/i386/tcg-target.h:98: +#ifdef __AVX2__ total: 0 errors, 2 warnings, 722 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 6/6: tcg/aarch64: Add vector operations... === OUTPUT END === Test command exited with code: 1 --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-devel@freelists.org