diff mbox series

[1/2] arm64: dts: uniphier: add AIDET nodes

Message ID 1503835387-9815-1-git-send-email-yamada.masahiro@socionext.com
State Accepted
Commit 3dfc6e982910c9fef4a924477b5f41a1257dd90f
Headers show
Series [1/2] arm64: dts: uniphier: add AIDET nodes | expand

Commit Message

Masahiro Yamada Aug. 27, 2017, 12:03 p.m. UTC
Add UniPhier AIDET (ARM Interrupt Detector) nodes to support
active low interrupts.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

---

 arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 7 +++++++
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 7 +++++++
 2 files changed, 14 insertions(+)

-- 
2.7.4

Comments

Masahiro Yamada Aug. 28, 2017, 3:03 p.m. UTC | #1
2017-08-27 21:03 GMT+09:00 Masahiro Yamada <yamada.masahiro@socionext.com>:
> Add UniPhier AIDET (ARM Interrupt Detector) nodes to support

> active low interrupts.

>

> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


Series, applied.


-- 
Best Regards
Masahiro Yamada
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 5537a457af97..ee4aff53a5f5 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -355,6 +355,13 @@ 
 			};
 		};
 
+		aidet: aidet@5fc20000 {
+			compatible = "socionext,uniphier-ld11-aidet";
+			reg = <0x5fc20000 0x200>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
 		gic: interrupt-controller@5fe00000 {
 			compatible = "arm,gic-v3";
 			reg = <0x5fe00000 0x10000>,	/* GICD */
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 304cb743d70c..f4948d0aa348 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -376,6 +376,13 @@ 
 			};
 		};
 
+		aidet: aidet@5fc20000 {
+			compatible = "socionext,uniphier-ld20-aidet";
+			reg = <0x5fc20000 0x200>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
 		gic: interrupt-controller@5fe00000 {
 			compatible = "arm,gic-v3";
 			reg = <0x5fe00000 0x10000>,	/* GICD */