| Message ID | 20170815145714.17635-2-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Fixup logic for exclusive pair | expand |
On 08/15/2017 11:57 AM, Richard Henderson wrote: > From: Alistair Francis <alistair.francis@xilinx.com> > > When we perform the atomic_cmpxchg operation we want to perform the > operation on a pair of 32-bit registers. Previously we were just passing > the register size in which was set to MO_32. This would result in the > high register to be ignored. To fix this issue we hardcode the size to > be 64-bits long when operating on 32-bit pairs. > > Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> > Message-Id: <bc18dddca56e8c2ea4a3def48d33ceb5d21d1fff.1502488636.git.alistair.francis@xilinx.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/arm/translate-a64.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 58ed4c6d05..113e2e172b 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -1913,7 +1913,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, > tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); > tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, > get_mem_index(s), > - size | MO_ALIGN | s->be_data); > + MO_64 | MO_ALIGN | s->be_data); > tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); > tcg_temp_free_i64(val); > } else if (s->be_data == MO_LE) { >
On Tue, Aug 15, 2017 at 8:41 AM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > On 08/15/2017 11:57 AM, Richard Henderson wrote: >> >> From: Alistair Francis <alistair.francis@xilinx.com> >> >> When we perform the atomic_cmpxchg operation we want to perform the >> operation on a pair of 32-bit registers. Previously we were just passing >> the register size in which was set to MO_32. This would result in the >> high register to be ignored. To fix this issue we hardcode the size to >> be 64-bits long when operating on 32-bit pairs. >> >> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> >> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> >> Message-Id: >> <bc18dddca56e8c2ea4a3def48d33ceb5d21d1fff.1502488636.git.alistair.francis@xilinx.com> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > > > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Can we keep this as well, it was posted for my entire series: Tested-by: Portia Stephens <portia.stephens@xilinx.com> Thanks, Alistair > > >> --- >> target/arm/translate-a64.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c >> index 58ed4c6d05..113e2e172b 100644 >> --- a/target/arm/translate-a64.c >> +++ b/target/arm/translate-a64.c >> @@ -1913,7 +1913,7 @@ static void gen_store_exclusive(DisasContext *s, int >> rd, int rt, int rt2, >> tcg_gen_concat32_i64(val, cpu_exclusive_val, >> cpu_exclusive_high); >> tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, >> get_mem_index(s), >> - size | MO_ALIGN | s->be_data); >> + MO_64 | MO_ALIGN | s->be_data); >> tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); >> tcg_temp_free_i64(val); >> } else if (s->be_data == MO_LE) { >> >
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 58ed4c6d05..113e2e172b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1913,7 +1913,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, get_mem_index(s), - size | MO_ALIGN | s->be_data); + MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); tcg_temp_free_i64(val); } else if (s->be_data == MO_LE) {