@@ -1590,6 +1590,27 @@ static int aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
return 0;
}
+static int aa64_daif_read(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t *value)
+{
+ if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
+ return EXCP_UDEF;
+ }
+ *value = pstate_read(env) & PSTATE_DAIF;
+ return 0;
+}
+
+static int aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
+ return EXCP_UDEF;
+ }
+ env->pstate &= ~PSTATE_DAIF;
+ env->pstate |= (value & PSTATE_DAIF);
+ return 0;
+}
+
static const ARMCPRegInfo v8_cp_reginfo[] = {
/* Minimal set of EL0-visible registers. This will need to be expanded
* significantly for system emulation of AArch64 CPUs.
@@ -1597,6 +1618,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "NZCV", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
.access = PL0_RW, .type = ARM_CP_NZCV },
+ { .name = "DAIF", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
+ .access = PL0_RW, .type = ARM_CP_NO_MIGRATE,
+ .readfn = aa64_daif_read, .writefn = aa64_daif_write },
{ .name = "FPCR", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
.access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
Implement the DAIF system register which is a view of the DAIF bits in PSTATE. TODO: include support for the MSR_i encodings? Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)