diff mbox

[v3,27/40] Subject: ARM: mm: proc-mohawk: Use the new processor struct macros

Message ID 1308851448-25139-28-git-send-email-dave.martin@linaro.org
State Superseded
Headers show

Commit Message

Dave Martin June 23, 2011, 5:50 p.m. UTC 
NOTE: Even with this patch, this CPU is still broken due the lack
of a suitable flush_icache_all function.

Without this patch, the entries in the cache functions struct are
off by one, which will result in the wrong functions being called
at run-time.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-mohawk.S |   50 ++++++--------------------------------------
 1 files changed, 7 insertions(+), 43 deletions(-)

Comments

Russell King - ARM Linux July 7, 2011, 9:11 a.m. UTC | #1 
On Thu, Jun 23, 2011 at 06:50:35PM +0100, Dave Martin wrote:
> NOTE: Even with this patch, this CPU is still broken due the lack
> of a suitable flush_icache_all function.

I assume that it now gets a build error rather than silently failing
at runtime?  If so, that's actually an improvement.
Dave Martin July 7, 2011, 10:21 a.m. UTC | #2 
On Thu, Jul 07, 2011 at 10:11:14AM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 23, 2011 at 06:50:35PM +0100, Dave Martin wrote:
> > NOTE: Even with this patch, this CPU is still broken due the lack
> > of a suitable flush_icache_all function.
> 
> I assume that it now gets a build error rather than silently failing
> at runtime?  If so, that's actually an improvement.

The answer should be yes.

In the branch referenced by Will's pull request, I've integrated a contribution
from Nico which supplies the missing flush function anyway ... so the combined
patch ought to fix that problem anyway:

+/*
+ *     flush_icache_all()
+ *
+ *     Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(mohawk_flush_icache_all)
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+       mov     pc, lr
+ENDPROC(mohawk_flush_icache_all)

Cheers
---Dave
diff mbox

Patch

diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 9d4f2ae..e1fad39 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -288,16 +288,8 @@  ENTRY(mohawk_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(mohawk_dma_unmap_area)
 
-ENTRY(mohawk_cache_fns)
-	.long	mohawk_flush_kern_cache_all
-	.long	mohawk_flush_user_cache_all
-	.long	mohawk_flush_user_cache_range
-	.long	mohawk_coherent_kern_range
-	.long	mohawk_coherent_user_range
-	.long	mohawk_flush_kern_dcache_area
-	.long	mohawk_dma_map_area
-	.long	mohawk_dma_unmap_area
-	.long	mohawk_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions mohawk, default=mohawk
 
 ENTRY(cpu_mohawk_dcache_clean_area)
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -373,42 +365,14 @@  mohawk_crval:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	mohawk_processor_functions, #object
-mohawk_processor_functions:
-	.word	v5t_early_abort
-	.word	legacy_pabort
-	.word	cpu_mohawk_proc_init
-	.word	cpu_mohawk_proc_fin
-	.word	cpu_mohawk_reset
-	.word	cpu_mohawk_do_idle
-	.word	cpu_mohawk_dcache_clean_area
-	.word	cpu_mohawk_switch_mm
-	.word	cpu_mohawk_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	mohawk_processor_functions, . - mohawk_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions mohawk, dabort=v5t_early_abort, pabort=legacy_pabort
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5te"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_mohawk_name, #object
-cpu_mohawk_name:
-	.asciz	"Marvell 88SV331x"
-	.size	cpu_mohawk_name, . - cpu_mohawk_name
+	string	cpu_arch_name, "armv5te"
+	string	cpu_elf_name, "v5"
+	string	cpu_mohawk_name, "Marvell 88SV331x"
 
 	.align