Message ID | 1480652017-31676-3-git-send-email-heyi.guo@linaro.org |
---|---|
State | Accepted |
Commit | b1e4f695b755ba307d8b9f36aef8faea380bef3f |
Headers | show |
On Fri, Dec 02, 2016 at 12:12:55PM +0800, Heyi Guo wrote: > phyDqsFallRiseDelay was spelt as phyDqs*Fail*RiseDelay; just fix the > typo,also update the related binaries. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > --- > .../PlatformSysCtrlLibHi1610.lib | Bin 273980 -> 305230 bytes > .../Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib | Bin 439708 -> 431524 bytes > Chips/Hisilicon/Include/Library/HwMemInitLib.h | 2 +- > .../Binary/D02/MemoryInitPei/MemoryInit.efi | Bin 159136 -> 160672 bytes > .../Binary/D03/MemoryInitPei/MemoryInit.efi | Bin 158944 -> 161280 bytes > 5 files changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib b/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib > index 1d9f248..ca78ae6 100644 > Binary files a/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib and b/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib differ > diff --git a/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib > index 6e9c41d..5f8ab73 100644 > Binary files a/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib and b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib differ > diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h > index 6bf323d..c24930f 100644 > --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h > +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h > @@ -254,7 +254,7 @@ typedef struct _DDR_Channel{ > UINT8 per_cs_training_en; > UINT32 phyRdDataEnIeDly; > UINT32 phyPadCalConfig; > - UINT32 phyDqsFailRiseDelay; > + UINT32 phyDqsFallRiseDelay; > UINT32 ddrcCfgDfiLat0; > UINT32 ddrcCfgDfiLat1; > UINT32 parityLatency; > diff --git a/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi > index ce63a5c..8d2a9f3 100644 > Binary files a/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi and b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi differ > diff --git a/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi > index cf6bb92..f335e5c 100644 > Binary files a/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi and b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi differ > -- > 1.9.1 >
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib b/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib index 1d9f248..ca78ae6 100644 Binary files a/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib and b/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib differ diff --git a/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib index 6e9c41d..5f8ab73 100644 Binary files a/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib and b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib differ diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 6bf323d..c24930f 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -254,7 +254,7 @@ typedef struct _DDR_Channel{ UINT8 per_cs_training_en; UINT32 phyRdDataEnIeDly; UINT32 phyPadCalConfig; - UINT32 phyDqsFailRiseDelay; + UINT32 phyDqsFallRiseDelay; UINT32 ddrcCfgDfiLat0; UINT32 ddrcCfgDfiLat1; UINT32 parityLatency;
phyDqsFallRiseDelay was spelt as phyDqs*Fail*RiseDelay; just fix the typo,also update the related binaries. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> --- .../PlatformSysCtrlLibHi1610.lib | Bin 273980 -> 305230 bytes .../Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib | Bin 439708 -> 431524 bytes Chips/Hisilicon/Include/Library/HwMemInitLib.h | 2 +- .../Binary/D02/MemoryInitPei/MemoryInit.efi | Bin 159136 -> 160672 bytes .../Binary/D03/MemoryInitPei/MemoryInit.efi | Bin 158944 -> 161280 bytes 5 files changed, 1 insertion(+), 1 deletion(-) diff --git a/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi index ce63a5c..8d2a9f3 100644 Binary files a/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi and b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi index cf6bb92..f335e5c 100644 Binary files a/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi and b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi differ