| Message ID | 7a1e72f6-db69-c930-0528-389eab7bc99d@foss.arm.com |
|---|---|
| State | New |
| Headers | show |
Hi Thomas, On 24/10/16 09:06, Thomas Preudhomme wrote: > Ping? > > Best regards, > > Thomas > > On 14/10/16 14:51, Thomas Preudhomme wrote: >> Ping? >> >> Best regards, >> >> Thomas >> >> On 03/10/16 17:46, Thomas Preudhomme wrote: >>> Ping? >>> >>> Best regards, >>> >>> Thomas >>> >>> On 22/09/16 14:50, Thomas Preudhomme wrote: >>>> Hi, >>>> >>>> This patch is part of a patch series to add support for atomic operations on >>>> ARMv8-M Baseline targets in GCC. This specific patch enables atomic and >>>> synchronization support added in previous patches of the series and adds tests. >>>> Enabling is done at the end of the patch series to ensure that no ICE is seen >>>> when in the middle of the patch series (eg. while doing a bisect). Enabling is >>>> done by enabling the exclusive and atomic loads and stores needed to implement >>>> all synchronization and atomic operations. >>>> >>>> ChangeLog entries are as follow: >>>> >>>> *** gcc/ChangeLog *** >>>> >>>> 2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com> >>>> >>>> * config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline. >>>> (TARGET_HAVE_LDREXBH): Likewise. >>>> (TARGET_HAVE_LDACQ): Likewise. >>>> >>>> >>>> *** gcc/testsuite/ChangeLog *** >>>> >>>> 2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com> >>>> >>>> * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test. >>>> * gcc.target/arm/atomic-op-acq_rel-3.c: Likewise. >>>> * gcc.target/arm/atomic-op-acquire-3.c: Likewise. >>>> * gcc.target/arm/atomic-op-char-3.c: Likewise. >>>> * gcc.target/arm/atomic-op-consume-3.c: Likewise. >>>> * gcc.target/arm/atomic-op-int-3.c: Likewise. >>>> * gcc.target/arm/atomic-op-relaxed-3.c: Likewise. >>>> * gcc.target/arm/atomic-op-release-3.c: Likewise. >>>> * gcc.target/arm/atomic-op-seq_cst-3.c: Likewise. >>>> * gcc.target/arm/atomic-op-short-3.c: Likewise. >>>> >>>> >>>> Testing: No code generation difference for ARMv7-A, ARMv7VE and ARMv8-A on all >>>> atomic and synchronization testcases in the testsuite [2]. Patchset was also >>>> bootstrapped with --enable-itm --enable-gomp on ARMv8-A in ARM and Thumb mode at >>>> optimization level -O1 and above [1] without any regression in the testsuite and >>>> no code generation difference in libitm and libgomp. >>>> >>>> Code generation for ARMv8-M Baseline has been manually examined and compared >>>> against ARMv8-A Thumb-2 for the following configuration without finding any >>>> issue: >>>> >>>> gcc.dg/atomic-op-2.c at -Os >>>> gcc.dg/atomic-compare-exchange-2.c at -Os >>>> gcc.dg/atomic-compare-exchange-3.c at -O3 >>>> >>>> >>>> Is this ok for trunk? >>>> This is ok. I'm not a fan of arm_arch_notm because we end up using a lot of double negatives (!arm_arch_notm) but that could be cleaned in the future separately in the whole backend. Thanks, Kyrill >>>> Best regards, >>>> >>>> Thomas >>>> >>>> [1] CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET were set to "-O1 -g", "-O3 -g" and >>>> undefined ("-O2 -g") >>>> [2] The exact list is: >>>> >>>> gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c >>>> gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c >>>> gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c >>>> gcc/testsuite/gcc.dg/atomic-exchange-1.c >>>> gcc/testsuite/gcc.dg/atomic-exchange-2.c >>>> gcc/testsuite/gcc.dg/atomic-exchange-3.c >>>> gcc/testsuite/gcc.dg/atomic-fence.c >>>> gcc/testsuite/gcc.dg/atomic-flag.c >>>> gcc/testsuite/gcc.dg/atomic-generic.c >>>> gcc/testsuite/gcc.dg/atomic-generic-aux.c >>>> gcc/testsuite/gcc.dg/atomic-invalid-2.c >>>> gcc/testsuite/gcc.dg/atomic-load-1.c >>>> gcc/testsuite/gcc.dg/atomic-load-2.c >>>> gcc/testsuite/gcc.dg/atomic-load-3.c >>>> gcc/testsuite/gcc.dg/atomic-lockfree.c >>>> gcc/testsuite/gcc.dg/atomic-lockfree-aux.c >>>> gcc/testsuite/gcc.dg/atomic-noinline.c >>>> gcc/testsuite/gcc.dg/atomic-noinline-aux.c >>>> gcc/testsuite/gcc.dg/atomic-op-1.c >>>> gcc/testsuite/gcc.dg/atomic-op-2.c >>>> gcc/testsuite/gcc.dg/atomic-op-3.c >>>> gcc/testsuite/gcc.dg/atomic-op-6.c >>>> gcc/testsuite/gcc.dg/atomic-store-1.c >>>> gcc/testsuite/gcc.dg/atomic-store-2.c >>>> gcc/testsuite/gcc.dg/atomic-store-3.c >>>> gcc/testsuite/g++.dg/ext/atomic-1.C >>>> gcc/testsuite/g++.dg/ext/atomic-2.C >>>> gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-acquire.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-char.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-consume.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-int.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-release.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c >>>> gcc/testsuite/gcc.target/arm/atomic-op-short.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c >>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c >>>> gcc/testsuite/gcc.target/arm/sync-1.c >>>> gcc/testsuite/gcc.target/arm/synchronize.c >>>> gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c >>>> gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c >>>> gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c >>>> gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c >>>> libstdc++-v3/testsuite/29_atomics/atomic/60658.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/62259.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/64658.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/65147.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/65913.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/70766.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/constexpr.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/copy_list.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/default.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/direct_list.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/single_value.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/user_pod.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/51811.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/56011.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_assignment.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_conversion.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/requirements/base_classes.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic/requirements/compare_exchange_lowering.cc >>>> >>>> >>>> libstdc++-v3/testsuite/29_atomics/atomic/requirements/explicit_instantiation/1.cc >>>> >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/clear/1.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/1.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/56012.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/aggregate.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/default.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/standard_layout.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/trivial.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/explicit.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/implicit.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/60940.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/65147.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/constexpr.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/copy_list.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/default.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/direct_list.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/single_value.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/bitwise.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/decrement.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/increment.cc >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_assignment.cc >>>> >>>> >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_conversion.cc >>>> >>>> >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/standard_layout.cc >>>> >>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/trivial.cc >>>> libstdc++-v3/testsuite/29_atomics/headers/atomic/functions_std_c++0x.cc >>>> libstdc++-v3/testsuite/29_atomics/headers/atomic/macros.cc >>>> libstdc++-v3/testsuite/29_atomics/headers/atomic/types_std_c++0x.cc
On 27/10/16 10:05, Kyrill Tkachov wrote: > Hi Thomas, > > On 24/10/16 09:06, Thomas Preudhomme wrote: >> Ping? >> >> Best regards, >> >> Thomas >> >> On 14/10/16 14:51, Thomas Preudhomme wrote: >>> Ping? >>> >>> Best regards, >>> >>> Thomas >>> >>> On 03/10/16 17:46, Thomas Preudhomme wrote: >>>> Ping? >>>> >>>> Best regards, >>>> >>>> Thomas >>>> >>>> On 22/09/16 14:50, Thomas Preudhomme wrote: >>>>> Hi, >>>>> >>>>> This patch is part of a patch series to add support for atomic operations on >>>>> ARMv8-M Baseline targets in GCC. This specific patch enables atomic and >>>>> synchronization support added in previous patches of the series and adds >>>>> tests. >>>>> Enabling is done at the end of the patch series to ensure that no ICE is seen >>>>> when in the middle of the patch series (eg. while doing a bisect). Enabling is >>>>> done by enabling the exclusive and atomic loads and stores needed to implement >>>>> all synchronization and atomic operations. >>>>> >>>>> ChangeLog entries are as follow: >>>>> >>>>> *** gcc/ChangeLog *** >>>>> >>>>> 2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com> >>>>> >>>>> * config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline. >>>>> (TARGET_HAVE_LDREXBH): Likewise. >>>>> (TARGET_HAVE_LDACQ): Likewise. >>>>> >>>>> >>>>> *** gcc/testsuite/ChangeLog *** >>>>> >>>>> 2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com> >>>>> >>>>> * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test. >>>>> * gcc.target/arm/atomic-op-acq_rel-3.c: Likewise. >>>>> * gcc.target/arm/atomic-op-acquire-3.c: Likewise. >>>>> * gcc.target/arm/atomic-op-char-3.c: Likewise. >>>>> * gcc.target/arm/atomic-op-consume-3.c: Likewise. >>>>> * gcc.target/arm/atomic-op-int-3.c: Likewise. >>>>> * gcc.target/arm/atomic-op-relaxed-3.c: Likewise. >>>>> * gcc.target/arm/atomic-op-release-3.c: Likewise. >>>>> * gcc.target/arm/atomic-op-seq_cst-3.c: Likewise. >>>>> * gcc.target/arm/atomic-op-short-3.c: Likewise. >>>>> >>>>> >>>>> Testing: No code generation difference for ARMv7-A, ARMv7VE and ARMv8-A on all >>>>> atomic and synchronization testcases in the testsuite [2]. Patchset was also >>>>> bootstrapped with --enable-itm --enable-gomp on ARMv8-A in ARM and Thumb >>>>> mode at >>>>> optimization level -O1 and above [1] without any regression in the >>>>> testsuite and >>>>> no code generation difference in libitm and libgomp. >>>>> >>>>> Code generation for ARMv8-M Baseline has been manually examined and compared >>>>> against ARMv8-A Thumb-2 for the following configuration without finding any >>>>> issue: >>>>> >>>>> gcc.dg/atomic-op-2.c at -Os >>>>> gcc.dg/atomic-compare-exchange-2.c at -Os >>>>> gcc.dg/atomic-compare-exchange-3.c at -O3 >>>>> >>>>> >>>>> Is this ok for trunk? >>>>> > > This is ok. > I'm not a fan of arm_arch_notm because we end up using a lot of double negatives > (!arm_arch_notm) but that could be cleaned in the future separately in the whole > backend. Agreed. It also feels backward to express the availability of ARM mode by saying we have non-Thumb instructions available. I'm guessing arm_arch_arm was considered even more confusing? Thanks. Best regards, Thomas
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index c7149d1f49738f9f01232cdcb610caca0e5f7e5d..34aca9ed0432afa8e855af5aecf6caa3ec1dd0e1 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -247,21 +247,25 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) /* Nonzero if this chip supports ldrex and strex */ -#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) +#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ + || arm_arch7 \ + || (arm_arch8 && !arm_arch_notm)) /* Nonzero if this chip supports LPAE. */ #define TARGET_HAVE_LPAE \ (arm_arch7 && ARM_FSET_HAS_CPU1 (insn_flags, FL_FOR_ARCH7VE)) /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ -#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) +#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ + || arm_arch7 \ + || (arm_arch8 && !arm_arch_notm)) /* Nonzero if this chip supports ldrexd and strexd. */ #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ || arm_arch7) && arm_arch_notm) /* Nonzero if this chip supports load-acquire and store-release. */ -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT) +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) /* Nonzero if this chip supports LDAEXD and STLEXD. */ #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ diff --git a/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c new file mode 100644 index 0000000000000000000000000000000000000000..0191f7af3a4656cb21c79c0f853f9e5a8aa44e86 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2 -fno-ipa-icf" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-comp-swap-release-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex" 4 } } */ +/* { dg-final { scan-assembler-times "stlex" 4 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c new file mode 100644 index 0000000000000000000000000000000000000000..f2ed32d01977466bd0afac013e8490beaf2a3691 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-acq_rel.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c new file mode 100644 index 0000000000000000000000000000000000000000..bba1c2709e74fd220275f35bda858aa805f8d080 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c new file mode 100644 index 0000000000000000000000000000000000000000..17117eebf70b99ca2651520366563dc7043b9ddf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-char.x" + +/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c new file mode 100644 index 0000000000000000000000000000000000000000..8352f0c3af81c9ad25d7c9cda7e92fdd0e3ba0fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-consume.x" + +/* Scan for ldaex is a PR59448 consume workaround. */ +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c new file mode 100644 index 0000000000000000000000000000000000000000..d4f1db34a1f1851b5d3bfa277ff106bb24e25f73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-int.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c new file mode 100644 index 0000000000000000000000000000000000000000..09b5ea9f6d3bf0c324ee532ccae002d41b687105 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-relaxed.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c new file mode 100644 index 0000000000000000000000000000000000000000..2b136f5ca2e7881cba218fa4980684f2ed082d30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-release.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c new file mode 100644 index 0000000000000000000000000000000000000000..7f38d42fa630819080171deee98fbc287e6957fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-seq_cst.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c new file mode 100644 index 0000000000000000000000000000000000000000..60ae42ebc34802391761d2e6cd286bbe475b646b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-short.x" + +/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */