| Message ID | 1477288523-10819-3-git-send-email-vijay.kilari@gmail.com |
|---|---|
| State | New |
| Headers | show |
* vijay.kilari@gmail.com (vijay.kilari@gmail.com) wrote: > From: Vijaya Kumar K <Vijaya.Kumar@cavium.com> > > Add helper API to read MIDR_EL1 registers to fetch > cpu identification information. This helps in > adding errata's and architecture specific features. > > This is implemented only for arm architecture. > > Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com> > --- > include/qemu/aarch64-cpuid.h | 9 +++++ > util/Makefile.objs | 1 + > util/aarch64-cpuid.c | 87 ++++++++++++++++++++++++++++++++++++++++++++ It feels like there should be somewhere else to put this very ARM specific thing that in util/ - not sure where though. > 3 files changed, 97 insertions(+) > > diff --git a/include/qemu/aarch64-cpuid.h b/include/qemu/aarch64-cpuid.h > new file mode 100644 > index 0000000..dbcb5ff > --- /dev/null > +++ b/include/qemu/aarch64-cpuid.h > @@ -0,0 +1,9 @@ > +#ifndef QEMU_AARCH64_CPUID_H > +#define QEMU_AARCH64_CPUID_H > + > +#if defined(__aarch64__) > +uint64_t get_aarch64_cpu_id(void); > +bool is_thunderx_pass2_cpu(void); > +#endif > + > +#endif > diff --git a/util/Makefile.objs b/util/Makefile.objs > index 36c7dcc..d14a455 100644 > --- a/util/Makefile.objs > +++ b/util/Makefile.objs > @@ -37,3 +37,4 @@ util-obj-y += log.o > util-obj-y += qdist.o > util-obj-y += qht.o > util-obj-y += range.o > +util-obj-y += aarch64-cpuid.o > diff --git a/util/aarch64-cpuid.c b/util/aarch64-cpuid.c > new file mode 100644 > index 0000000..a6352ad > --- /dev/null > +++ b/util/aarch64-cpuid.c > @@ -0,0 +1,87 @@ > +/* > + * Dealing with arm cpu identification information. > + * > + * Copyright (C) 2016 Cavium, Inc. > + * > + * Authors: > + * Vijaya Kumar K <Vijaya.Kumar@cavium.com> > + * > + * This work is licensed under the terms of the GNU LGPL, version 2.1 > + * or later. See the COPYING.LIB file in the top-level directory. > + */ > + > +#include <math.h> > +#include "qemu/osdep.h" > +#include "qemu-common.h" > +#include "qemu/cutils.h" > +#include "qemu/aarch64-cpuid.h" > + > +#if defined(__aarch64__) > +#define MIDR_IMPLEMENTER_SHIFT 24 > +#define MIDR_IMPLEMENTER_MASK (0xffULL << MIDR_IMPLEMENTER_SHIFT) > +#define MIDR_ARCHITECTURE_SHIFT 16 > +#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) > +#define MIDR_PARTNUM_SHIFT 4 > +#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) > + > +#define MIDR_CPU_PART(imp, partnum) \ > + (((imp) << MIDR_IMPLEMENTER_SHIFT) | \ > + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ > + ((partnum) << MIDR_PARTNUM_SHIFT)) > + > +#define ARM_CPU_IMP_CAVIUM 0x43 > +#define CAVIUM_CPU_PART_THUNDERX 0x0A1 > + > +#define MIDR_THUNDERX_PASS2 \ > + MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) > +#define CPU_MODEL_MASK (MIDR_IMPLEMENTER_MASK | MIDR_ARCHITECTURE_MASK | \ > + MIDR_PARTNUM_MASK) > + > +static uint64_t qemu_read_aarch64_midr_el1(void) > +{ > +#ifdef CONFIG_LINUX > + const char *file = "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1"; > + char *buf; > + uint64_t midr = 0; > + > +#define BUF_SIZE 32 > + buf = g_malloc0(BUF_SIZE); > + if (!buf) { > + return 0; > + } Do you need to do that? Isn't g_file_get_contents doing the allocation? Dave > + if (!g_file_get_contents(file, &buf, 0, NULL)) { > + goto out; > + } > + > + if (qemu_strtoull(buf, NULL, 0, &midr) < 0) { > + goto out; > + } > + > +out: > + g_free(buf); > + > + return midr; > +#else > + return 0; > +#endif > +} > + > +static uint64_t aarch64_midr_val; > +uint64_t get_aarch64_cpu_id(void) > +{ > +#ifdef CONFIG_LINUX > + aarch64_midr_val = qemu_read_aarch64_midr_el1(); > + aarch64_midr_val &= CPU_MODEL_MASK; > + > + return aarch64_midr_val; > +#else > + return 0; > +#endif > +} > + > +bool is_thunderx_pass2_cpu(void) > +{ > + return aarch64_midr_val == MIDR_THUNDERX_PASS2; > +} > +#endif > -- > 1.9.1 > > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
On Mon, Oct 24, 2016 at 3:09 PM, Dr. David Alan Gilbert <dgilbert@redhat.com> wrote: > * vijay.kilari@gmail.com (vijay.kilari@gmail.com) wrote: >> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com> >> >> Add helper API to read MIDR_EL1 registers to fetch >> cpu identification information. This helps in >> adding errata's and architecture specific features. >> >> This is implemented only for arm architecture. >> >> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com> >> --- >> include/qemu/aarch64-cpuid.h | 9 +++++ >> util/Makefile.objs | 1 + >> util/aarch64-cpuid.c | 87 ++++++++++++++++++++++++++++++++++++++++++++ > > It feels like there should be somewhere else to put this very ARM specific thing > that in util/ - not sure where though. IRC, I tried it. But libutil is built before arch code compilation. So cannot put outside of util folder
On 24/10/2016 11:39, Dr. David Alan Gilbert wrote: > * vijay.kilari@gmail.com (vijay.kilari@gmail.com) wrote: >> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com> >> >> Add helper API to read MIDR_EL1 registers to fetch >> cpu identification information. This helps in >> adding errata's and architecture specific features. >> >> This is implemented only for arm architecture. >> >> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com> >> --- >> include/qemu/aarch64-cpuid.h | 9 +++++ >> util/Makefile.objs | 1 + >> util/aarch64-cpuid.c | 87 ++++++++++++++++++++++++++++++++++++++++++++ > > It feels like there should be somewhere else to put this very ARM specific thing > that in util/ - not sure where though. It's okay I guess, the name is pretty clear. What's important is a clear split of arch-specific and generic code in bufferiszero.c. Paolo >> 3 files changed, 97 insertions(+) >> >> diff --git a/include/qemu/aarch64-cpuid.h b/include/qemu/aarch64-cpuid.h > >> new file mode 100644 >> index 0000000..dbcb5ff >> --- /dev/null >> +++ b/include/qemu/aarch64-cpuid.h >> @@ -0,0 +1,9 @@ >> +#ifndef QEMU_AARCH64_CPUID_H >> +#define QEMU_AARCH64_CPUID_H >> + >> +#if defined(__aarch64__) >> +uint64_t get_aarch64_cpu_id(void); >> +bool is_thunderx_pass2_cpu(void); >> +#endif >> + >> +#endif >> diff --git a/util/Makefile.objs b/util/Makefile.objs >> index 36c7dcc..d14a455 100644 >> --- a/util/Makefile.objs >> +++ b/util/Makefile.objs >> @@ -37,3 +37,4 @@ util-obj-y += log.o >> util-obj-y += qdist.o >> util-obj-y += qht.o >> util-obj-y += range.o >> +util-obj-y += aarch64-cpuid.o >> diff --git a/util/aarch64-cpuid.c b/util/aarch64-cpuid.c >> new file mode 100644 >> index 0000000..a6352ad >> --- /dev/null >> +++ b/util/aarch64-cpuid.c >> @@ -0,0 +1,87 @@ >> +/* >> + * Dealing with arm cpu identification information. >> + * >> + * Copyright (C) 2016 Cavium, Inc. >> + * >> + * Authors: >> + * Vijaya Kumar K <Vijaya.Kumar@cavium.com> >> + * >> + * This work is licensed under the terms of the GNU LGPL, version 2.1 >> + * or later. See the COPYING.LIB file in the top-level directory. >> + */ >> + >> +#include <math.h> >> +#include "qemu/osdep.h" >> +#include "qemu-common.h" >> +#include "qemu/cutils.h" >> +#include "qemu/aarch64-cpuid.h" >> + >> +#if defined(__aarch64__) >> +#define MIDR_IMPLEMENTER_SHIFT 24 >> +#define MIDR_IMPLEMENTER_MASK (0xffULL << MIDR_IMPLEMENTER_SHIFT) >> +#define MIDR_ARCHITECTURE_SHIFT 16 >> +#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) >> +#define MIDR_PARTNUM_SHIFT 4 >> +#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) >> + >> +#define MIDR_CPU_PART(imp, partnum) \ >> + (((imp) << MIDR_IMPLEMENTER_SHIFT) | \ >> + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ >> + ((partnum) << MIDR_PARTNUM_SHIFT)) >> + >> +#define ARM_CPU_IMP_CAVIUM 0x43 >> +#define CAVIUM_CPU_PART_THUNDERX 0x0A1 >> + >> +#define MIDR_THUNDERX_PASS2 \ >> + MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) >> +#define CPU_MODEL_MASK (MIDR_IMPLEMENTER_MASK | MIDR_ARCHITECTURE_MASK | \ >> + MIDR_PARTNUM_MASK) >> + >> +static uint64_t qemu_read_aarch64_midr_el1(void) >> +{ >> +#ifdef CONFIG_LINUX >> + const char *file = "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1"; >> + char *buf; >> + uint64_t midr = 0; >> + >> +#define BUF_SIZE 32 >> + buf = g_malloc0(BUF_SIZE); >> + if (!buf) { >> + return 0; >> + } > > Do you need to do that? Isn't g_file_get_contents doing the allocation? > > Dave > >> + if (!g_file_get_contents(file, &buf, 0, NULL)) { >> + goto out; >> + } >> + >> + if (qemu_strtoull(buf, NULL, 0, &midr) < 0) { >> + goto out; >> + } >> + >> +out: >> + g_free(buf); >> + >> + return midr; >> +#else >> + return 0; >> +#endif >> +} >> + >> +static uint64_t aarch64_midr_val; >> +uint64_t get_aarch64_cpu_id(void) >> +{ >> +#ifdef CONFIG_LINUX >> + aarch64_midr_val = qemu_read_aarch64_midr_el1(); >> + aarch64_midr_val &= CPU_MODEL_MASK; >> + >> + return aarch64_midr_val; >> +#else >> + return 0; >> +#endif >> +} >> + >> +bool is_thunderx_pass2_cpu(void) >> +{ >> + return aarch64_midr_val == MIDR_THUNDERX_PASS2; >> +} >> +#endif >> -- >> 1.9.1 >> >> > -- > Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK >
On 10/23/2016 10:55 PM, vijay.kilari@gmail.com wrote: > +static uint64_t aarch64_midr_val; > +uint64_t get_aarch64_cpu_id(void) > +{ > +#ifdef CONFIG_LINUX > + aarch64_midr_val = qemu_read_aarch64_midr_el1(); > + aarch64_midr_val &= CPU_MODEL_MASK; > + > + return aarch64_midr_val; > +#else > + return 0; > +#endif > +} > + > +bool is_thunderx_pass2_cpu(void) > +{ > + return aarch64_midr_val == MIDR_THUNDERX_PASS2; > +} Any particular reason why you want to keep midr_val and MIDR_THUNDERX private to this file? Seems like it would be cheaper to export those in the header. r~
diff --git a/include/qemu/aarch64-cpuid.h b/include/qemu/aarch64-cpuid.h new file mode 100644 index 0000000..dbcb5ff --- /dev/null +++ b/include/qemu/aarch64-cpuid.h @@ -0,0 +1,9 @@ +#ifndef QEMU_AARCH64_CPUID_H +#define QEMU_AARCH64_CPUID_H + +#if defined(__aarch64__) +uint64_t get_aarch64_cpu_id(void); +bool is_thunderx_pass2_cpu(void); +#endif + +#endif diff --git a/util/Makefile.objs b/util/Makefile.objs index 36c7dcc..d14a455 100644 --- a/util/Makefile.objs +++ b/util/Makefile.objs @@ -37,3 +37,4 @@ util-obj-y += log.o util-obj-y += qdist.o util-obj-y += qht.o util-obj-y += range.o +util-obj-y += aarch64-cpuid.o diff --git a/util/aarch64-cpuid.c b/util/aarch64-cpuid.c new file mode 100644 index 0000000..a6352ad --- /dev/null +++ b/util/aarch64-cpuid.c @@ -0,0 +1,87 @@ +/* + * Dealing with arm cpu identification information. + * + * Copyright (C) 2016 Cavium, Inc. + * + * Authors: + * Vijaya Kumar K <Vijaya.Kumar@cavium.com> + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 + * or later. See the COPYING.LIB file in the top-level directory. + */ + +#include <math.h> +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/cutils.h" +#include "qemu/aarch64-cpuid.h" + +#if defined(__aarch64__) +#define MIDR_IMPLEMENTER_SHIFT 24 +#define MIDR_IMPLEMENTER_MASK (0xffULL << MIDR_IMPLEMENTER_SHIFT) +#define MIDR_ARCHITECTURE_SHIFT 16 +#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) +#define MIDR_PARTNUM_SHIFT 4 +#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) + +#define MIDR_CPU_PART(imp, partnum) \ + (((imp) << MIDR_IMPLEMENTER_SHIFT) | \ + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ + ((partnum) << MIDR_PARTNUM_SHIFT)) + +#define ARM_CPU_IMP_CAVIUM 0x43 +#define CAVIUM_CPU_PART_THUNDERX 0x0A1 + +#define MIDR_THUNDERX_PASS2 \ + MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) +#define CPU_MODEL_MASK (MIDR_IMPLEMENTER_MASK | MIDR_ARCHITECTURE_MASK | \ + MIDR_PARTNUM_MASK) + +static uint64_t qemu_read_aarch64_midr_el1(void) +{ +#ifdef CONFIG_LINUX + const char *file = "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1"; + char *buf; + uint64_t midr = 0; + +#define BUF_SIZE 32 + buf = g_malloc0(BUF_SIZE); + if (!buf) { + return 0; + } + + if (!g_file_get_contents(file, &buf, 0, NULL)) { + goto out; + } + + if (qemu_strtoull(buf, NULL, 0, &midr) < 0) { + goto out; + } + +out: + g_free(buf); + + return midr; +#else + return 0; +#endif +} + +static uint64_t aarch64_midr_val; +uint64_t get_aarch64_cpu_id(void) +{ +#ifdef CONFIG_LINUX + aarch64_midr_val = qemu_read_aarch64_midr_el1(); + aarch64_midr_val &= CPU_MODEL_MASK; + + return aarch64_midr_val; +#else + return 0; +#endif +} + +bool is_thunderx_pass2_cpu(void) +{ + return aarch64_midr_val == MIDR_THUNDERX_PASS2; +} +#endif