[v2,for-2.5] target-arm/translate-a64.c: Correct unallocated checks for ldst_excl

The checks for the unallocated encodings in the ldst_excl group
(exclusives and load-acquire/store-release) were not correct. This
error meant that in turn we ended up with code attempting to handle
the non-existent case of "non-exclusive load-acquire/store-release
pair". Delete that broken and now unreachable code.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
The easiest way to validate that we have the unallocated
conditions correct now is to look at C4.4.6 "load/store exclusive"
in the v8 ARM ARM rev A.3h: our three conditions correspond
to the three "unallocated" rows in the decode table.

v2 changes: remove incorrect comment too.
---
 target-arm/translate-a64.c | 15 ++-------------
 1 file changed, 2 insertions(+), 13 deletions(-)

-- 
1.9.1

(Apologies if you got two copies of this -- I mangled the
--from argument to git send-email first time round and the list
servers rejected the mail. -- PMM)

On 24 November 2015 at 12:01, Peter Maydell <peter.maydell@linaro.org> wrote:
> The checks for the unallocated encodings in the ldst_excl group

> (exclusives and load-acquire/store-release) were not correct. This

> error meant that in turn we ended up with code attempting to handle

> the non-existent case of "non-exclusive load-acquire/store-release

> pair". Delete that broken and now unreachable code.

>

> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

> The easiest way to validate that we have the unallocated

> conditions correct now is to look at C4.4.6 "load/store exclusive"

> in the v8 ARM ARM rev A.3h: our three conditions correspond

> to the three "unallocated" rows in the decode table.

>

> v2 changes: remove incorrect comment too.

> ---

>  target-arm/translate-a64.c | 15 ++-------------

>  1 file changed, 2 insertions(+), 13 deletions(-)

>

> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c

> index fe485a4..14e8131 100644

> --- a/target-arm/translate-a64.c

> +++ b/target-arm/translate-a64.c

> @@ -1816,9 +1816,6 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,

>   *  o2: 0 -> exclusive, 1 -> not

>   *  o1: 0 -> single register, 1 -> register pair

>   *  o0: 1 -> load-acquire/store-release, 0 -> not

> - *

> - *  o0 == 0 AND o2 == 1 is un-allocated

> - *  o1 == 1 is un-allocated except for 32 and 64 bit sizes

>   */

>  static void disas_ldst_excl(DisasContext *s, uint32_t insn)

>  {

> @@ -1833,7 +1830,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)

>      int size = extract32(insn, 30, 2);

>      TCGv_i64 tcg_addr;

>

> -    if ((!is_excl && !is_lasr) ||

> +    if ((!is_excl && !is_pair && !is_lasr) ||

> +        (!is_excl && is_pair) ||

>          (is_pair && size < 2)) {

>          unallocated_encoding(s);

>          return;

> @@ -1862,15 +1860,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)

>          } else {

>              do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);

>          }

> -        if (is_pair) {

> -            TCGv_i64 tcg_rt2 = cpu_reg(s, rt);

> -            tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);

> -            if (is_store) {

> -                do_gpr_st(s, tcg_rt2, tcg_addr, size);

> -            } else {

> -                do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false);

> -            }

> -        }

>      }

>  }

>

> --

> 1.9.1