| Message ID | 1445883178-576-2-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Accepted |
| Headers | show |
Peter Maydell <peter.maydell@linaro.org> writes: > The AArch64 debug CPU display of PSTATE as "PSTATE=200003c5 (flags --C-)" > on the end of the same line as the last of the general purpose registers > is unnecessarily different from the AArch32 display of PSR as > "PSR=200001d3 --C- A svc32" on its own line. Update the AArch64 > code to put PSTATE in its own line and in the same format, including > printing the exception level (mode). > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target-arm/translate-a64.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index 19f9d8d..ccefa7b 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -126,6 +126,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, > CPUARMState *env = &cpu->env; > uint32_t psr = pstate_read(env); > int i; > + int el = arm_current_el(env); > > cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", > env->pc, env->xregs[31]); > @@ -137,13 +138,14 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, > cpu_fprintf(f, " "); > } > } > - cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n", > + cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n", > psr, > psr & PSTATE_N ? 'N' : '-', > psr & PSTATE_Z ? 'Z' : '-', > psr & PSTATE_C ? 'C' : '-', > - psr & PSTATE_V ? 'V' : '-'); > - cpu_fprintf(f, "\n"); > + psr & PSTATE_V ? 'V' : '-', > + el, > + psr & PSTATE_SP ? 'h' : 't'); > > if (flags & CPU_DUMP_FPU) { > int numvfpregs = 32; -- Alex Bennée
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 19f9d8d..ccefa7b 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -126,6 +126,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, CPUARMState *env = &cpu->env; uint32_t psr = pstate_read(env); int i; + int el = arm_current_el(env); cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", env->pc, env->xregs[31]); @@ -137,13 +138,14 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, " "); } } - cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n", + cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n", psr, psr & PSTATE_N ? 'N' : '-', psr & PSTATE_Z ? 'Z' : '-', psr & PSTATE_C ? 'C' : '-', - psr & PSTATE_V ? 'V' : '-'); - cpu_fprintf(f, "\n"); + psr & PSTATE_V ? 'V' : '-', + el, + psr & PSTATE_SP ? 'h' : 't'); if (flags & CPU_DUMP_FPU) { int numvfpregs = 32;
The AArch64 debug CPU display of PSTATE as "PSTATE=200003c5 (flags --C-)" on the end of the same line as the last of the general purpose registers is unnecessarily different from the AArch32 display of PSR as "PSR=200001d3 --C- A svc32" on its own line. Update the AArch64 code to put PSTATE in its own line and in the same format, including printing the exception level (mode). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/translate-a64.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 1.9.1