diff mbox

[2/2] arm64: cachetype: fix definitions of ICACHEF_* flags

Message ID 1445947555-2109-2-git-send-email-will.deacon@arm.com
State Accepted
Commit 59f2413573e4ee1e76062beef4a359156500db94
Headers show

Commit Message

Will Deacon Oct. 27, 2015, 12:05 p.m. UTC
test_bit and set_bit take the bit number to operate on, rather than a
mask. This patch fixes the ICACHEF_* definitions so that they represent
the bit index in __icache_flags as opposed to the mask returned by the
BIT macro.

Signed-off-by: Will Deacon <will.deacon@arm.com>

---
 arch/arm64/include/asm/cachetype.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
2.1.4


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Comments

Mark Rutland Oct. 27, 2015, 4:42 p.m. UTC | #1
On Tue, Oct 27, 2015 at 12:05:55PM +0000, Will Deacon wrote:
> test_bit and set_bit take the bit number to operate on, rather than a

> mask. This patch fixes the ICACHEF_* definitions so that they represent

> the bit index in __icache_flags as opposed to the mask returned by the

> BIT macro.

> 

> Signed-off-by: Will Deacon <will.deacon@arm.com>


At least they were used consistently, so this is a cleanup rather than a
fix.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>


Mark.

> ---

>  arch/arm64/include/asm/cachetype.h | 4 ++--

>  1 file changed, 2 insertions(+), 2 deletions(-)

> 

> diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h

> index da2fc9e3cedd..f5588692f1d4 100644

> --- a/arch/arm64/include/asm/cachetype.h

> +++ b/arch/arm64/include/asm/cachetype.h

> @@ -34,8 +34,8 @@

>  

>  #define CTR_L1IP(ctr)	(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)

>  

> -#define ICACHEF_ALIASING	BIT(0)

> -#define ICACHEF_AIVIVT		BIT(1)

> +#define ICACHEF_ALIASING	0

> +#define ICACHEF_AIVIVT		1

>  

>  extern unsigned long __icache_flags;

>  

> -- 

> 2.1.4

> 

> 

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> linux-arm-kernel mailing list

> linux-arm-kernel@lists.infradead.org

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> 


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diff mbox

Patch

diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h
index da2fc9e3cedd..f5588692f1d4 100644
--- a/arch/arm64/include/asm/cachetype.h
+++ b/arch/arm64/include/asm/cachetype.h
@@ -34,8 +34,8 @@ 
 
 #define CTR_L1IP(ctr)	(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
 
-#define ICACHEF_ALIASING	BIT(0)
-#define ICACHEF_AIVIVT		BIT(1)
+#define ICACHEF_ALIASING	0
+#define ICACHEF_AIVIVT		1
 
 extern unsigned long __icache_flags;