| Message ID | 1369834677-20312-3-git-send-email-vikas.sajjan@linaro.org |
|---|---|
| State | New |
| Headers | show |
Vikas / Yadwinder, On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan@linaro.org> wrote: > From: Yadwinder Singh Brar <yadi.brar@samsung.com> > > This patch defines a common rate_table which will contain recommended p, m, s, > k values for supported rates that needs to be changed for changing > corresponding PLL's rate. > > Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> > --- > drivers/clk/samsung/clk-exynos4.c | 8 ++++---- > drivers/clk/samsung/clk-exynos5250.c | 14 +++++++------- > drivers/clk/samsung/clk-pll.c | 14 ++++++++++++-- > drivers/clk/samsung/clk-pll.h | 33 +++++++++++++++++++++++++++++++-- > 4 files changed, 54 insertions(+), 15 deletions(-) I also reviewed this in our gerrit <https://gerrit.chromium.org/gerrit/#/c/56742/>, but I'll summarize here for the list... > struct clk * __init samsung_clk_register_pll35xx(const char *name, > - const char *pname, const void __iomem *base) > + const char *pname, const void __iomem *base, > + const struct samsung_pll_rate_table *rate_table, > + const unsigned int rate_count) Feels like you should document here that rate_table needs to be sorted and the sort order. > +struct samsung_pll_rate_table { > + unsigned int rate; nit: extra space before "int" should be removed. Also: you can include rate here if you need a convenient place to store it (which sadly means that this structure can't be const). ...but I do like Tomasz's idea of actually calculating it. You can't know it at compile time since the parent rate comes from the device tree. compatible = "samsung,clock-xxti"; clock-frequency = <24000000>; > + unsigned int pdiv; > + unsigned int mdiv; > + unsigned int sdiv; > + unsigned int kdiv; I think kdiv is signed. -Doug
Hi Doug, On Thu, May 30, 2013 at 5:14 AM, Doug Anderson <dianders@chromium.org> wrote: > Vikas / Yadwinder, > > On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan@linaro.org> wrote: >> From: Yadwinder Singh Brar <yadi.brar@samsung.com> >> >> This patch defines a common rate_table which will contain recommended p, m, s, >> k values for supported rates that needs to be changed for changing >> corresponding PLL's rate. >> >> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> >> --- >> drivers/clk/samsung/clk-exynos4.c | 8 ++++---- >> drivers/clk/samsung/clk-exynos5250.c | 14 +++++++------- >> drivers/clk/samsung/clk-pll.c | 14 ++++++++++++-- >> drivers/clk/samsung/clk-pll.h | 33 +++++++++++++++++++++++++++++++-- >> 4 files changed, 54 insertions(+), 15 deletions(-) > > I also reviewed this in our gerrit > <https://gerrit.chromium.org/gerrit/#/c/56742/>, but I'll summarize > here for the list... > >> struct clk * __init samsung_clk_register_pll35xx(const char *name, >> - const char *pname, const void __iomem *base) >> + const char *pname, const void __iomem *base, >> + const struct samsung_pll_rate_table *rate_table, >> + const unsigned int rate_count) > > Feels like you should document here that rate_table needs to be sorted > and the sort order. > sure, we will add comment to sort the table in descending order. >> +struct samsung_pll_rate_table { >> + unsigned int rate; > > nit: extra space before "int" should be removed. > ok > Also: you can include rate here if you need a convenient place to > store it (which sadly means that this structure can't be const). > ...but I do like Tomasz's idea of actually calculating it. You can't > know it at compile time since the parent rate comes from the device > tree. > > compatible = "samsung,clock-xxti"; > clock-frequency = <24000000>; > Actually this table should contain the recommended values and if we see the user manual, the input(parent) rate is also a part of recommended table of different output rate for a particular PLL for that SoC. So as Tomasz said input(parent) rate may change with board, then, do those corresponding recommended p, m, s, k will be valid? In case, input(parent) rate changes then we may need different set of p, m ,s, k values recommended for new input rate to get required(recommended to use) output rate. So, we think its better that the p, m, s and k along with the parent is known at the compile time ( or DT ?), as these p, m, s, k values are very much coupled with the parent rate to achieve the required(recommended to use) output rate. Also, since the sorted table is required (sorted based on "rate"), its better to have the rate in a const rate table. And the whole set of recommended values should come from same place(DT or static table), to keep the things simple and consistent. Moreover, practically for a particular SoC , we use the recommended input(parent) rate only for a PLL. So we should keep the things simple here presently. >> + unsigned int pdiv; >> + unsigned int mdiv; >> + unsigned int sdiv; >> + unsigned int kdiv; > > I think kdiv is signed. > No, as these values should be the recommended values to be written in corresponding register bits. So it should remain unsigned. K value should be considered as negative only while recalculating rate. As per exynos5250 user manual's section 7.3.2 : " K value description "Postive value (Negative value)": Postive values is that you should write EPLLCON/VPLLCON register. Negative value is that you can calculate PLL output frequency with it." > -Doug Regards, Yadwinder & Vikas.
Yadwinder and Vikas, On Wed, May 29, 2013 at 11:55 PM, Yadwinder Singh Brar <yadi.brar01@gmail.com> wrote: >> Also: you can include rate here if you need a convenient place to >> store it (which sadly means that this structure can't be const). >> ...but I do like Tomasz's idea of actually calculating it. You can't >> know it at compile time since the parent rate comes from the device >> tree. >> >> compatible = "samsung,clock-xxti"; >> clock-frequency = <24000000>; >> > > Actually this table should contain the recommended values > and if we see the user manual, the input(parent) rate is also a part > of recommended > table of different output rate for a particular PLL for that SoC. That's a reasonable point. It's not clear to me whether the recommended PMSK values would be the same or different if the input wasn't 24MHz. You're assuming that they would be different and that seems fair given my (limited) understanding of the electrical characteristics of PLLs. ...so if a given SoC needed to support multiple different parent clock frequencies the presumably it would have multiple tables and pick the right one to pass in. > So as Tomasz said input(parent) rate may change with board, > then, do those corresponding recommended p, m, s, k will be valid? > > In case, input(parent) rate changes then we may need different set of p, m ,s, k > values recommended for new input rate to get required(recommended to > use) output rate. > > So, we think its better that the p, m, s and k along with the parent > is known at the compile time ( or DT ?), > as these p, m, s, k values are very much coupled with the parent rate > to achieve the > required(recommended to use) output rate. Having the rate in the table definitely makes it easier to understand, too. We just have to hope someone doesn't mess up in their calculation. Worst case we could put some error checking somewhere. > Also, since the sorted table is required (sorted based on "rate"), > its better to have the rate in a const rate table. You _could_ still sort the table based on eventually rate even if the actual rate wasn't in the table. ...but I agree that it's harder to look at and figure out. > And the whole set of recommended values should come from same place(DT > or static table), > to keep the things simple and consistent. Agree that it's a little weird now that some bits of the clock code is in the device tree and some bits are just static tables in code. ...but I think that's OK for now. Perhaps a reasonable compromise is to include "24mhz" in the name of the tables (in later patches) and then give a WARN_ON if the xxti clock isn't 24MHz. Then you've effectively documented the plan of action should someone eventually need a different xxti clock. > Moreover, practically for a particular SoC , we use the recommended > input(parent) rate only for a PLL. > So we should keep the things simple here presently. From what I've seen so far I could totally believe Samsung releasing a new user manual in the future that provides instructions for using a non-24MHz xxti clock. ...but with all of the above I think we've got a reasonable story so I think we're good. >>> + unsigned int pdiv; >>> + unsigned int mdiv; >>> + unsigned int sdiv; >>> + unsigned int kdiv; >> >> I think kdiv is signed. >> > > No, as these values should be the recommended values to be written in > corresponding register bits. So it should remain unsigned. > > K value should be considered as negative only while recalculating rate. > > As per exynos5250 user manual's section 7.3.2 : > " K value description "Postive value (Negative value)": > Postive values is that you should write EPLLCON/VPLLCON register. > Negative value is that you can calculate PLL output frequency with it." OK, fair point. We can keep it unsigned in this table. To summarize where I think we are in this series, I'm hoping for one more version that: * Adds a comment about the rate table being sorted (and which direction) * Adds "24mhz" to the variable name for the PLL tables in future patch series * Adds a WARN_ON if the xxti clock isn't 24MHz Does that sound like a plan? Tomasz: any thoughts on the above? -Doug
Hi Yadwinder, On Thursday 30 of May 2013 12:25:40 Yadwinder Singh Brar wrote: > Hi Doug, > > On Thu, May 30, 2013 at 5:14 AM, Doug Anderson <dianders@chromium.org> wrote: > > Vikas / Yadwinder, > > > > On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan@linaro.org> wrote: > >> From: Yadwinder Singh Brar <yadi.brar@samsung.com> > >> > >> This patch defines a common rate_table which will contain recommended p, > >> m, s, k values for supported rates that needs to be changed for changing > >> corresponding PLL's rate. > >> > >> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> > >> --- > >> > >> drivers/clk/samsung/clk-exynos4.c | 8 ++++---- > >> drivers/clk/samsung/clk-exynos5250.c | 14 +++++++------- > >> drivers/clk/samsung/clk-pll.c | 14 ++++++++++++-- > >> drivers/clk/samsung/clk-pll.h | 33 > >> +++++++++++++++++++++++++++++++-- 4 files changed, 54 insertions(+), 15 > >> deletions(-) > > > > I also reviewed this in our gerrit > > <https://gerrit.chromium.org/gerrit/#/c/56742/>, but I'll summarize > > here for the list... > > > >> struct clk * __init samsung_clk_register_pll35xx(const char *name, > >> > >> - const char *pname, const void __iomem *base) > >> + const char *pname, const void __iomem *base, > >> + const struct samsung_pll_rate_table *rate_table, > >> + const unsigned int rate_count) > > > > Feels like you should document here that rate_table needs to be sorted > > and the sort order. > > sure, we will add comment to sort the table in descending order. > > >> +struct samsung_pll_rate_table { > >> + unsigned int rate; > > > > nit: extra space before "int" should be removed. > > ok > > > Also: you can include rate here if you need a convenient place to > > store it (which sadly means that this structure can't be const). > > ...but I do like Tomasz's idea of actually calculating it. You can't > > know it at compile time since the parent rate comes from the device > > tree. > > > > compatible = "samsung,clock-xxti"; > > clock-frequency = <24000000>; > > Actually this table should contain the recommended values > and if we see the user manual, the input(parent) rate is also a part > of recommended > table of different output rate for a particular PLL for that SoC. From what I understood in the documentation is that there is a set of recommended P, M, S (, K) tuples for each PLL and they are not dependent on input frequency - f_in and f_out are provided in the table just for reference to see the relation between output frequency and input frequency. I think we should ask some H/W engineer about that to make sure and choose the proper implementation, which will work properly for future cases, instead of ending with something that works just with current cases. Best regards,
Tomasz, On Mon, Jun 3, 2013 at 8:25 AM, Tomasz Figa <t.figa@samsung.com> wrote: > From what I understood in the documentation is that there is a set of > recommended P, M, S (, K) tuples for each PLL and they are not dependent on > input frequency - f_in and f_out are provided in the table just for reference > to see the relation between output frequency and input frequency. > > I think we should ask some H/W engineer about that to make sure and choose the > proper implementation, which will work properly for future cases, instead of > ending with something that works just with current cases. Hopefully you and Yadwinder can take this on? You probably have better access to the right people to ask. I did dig up my 4210 manual which actually has one place where it shows two options for FIN of VPLL: 24MHz and 27MHz. They don't seem to share any PMSK values that are the same. It seems like the tables were generated by choosing a bunch of frequencies that people would probably like to make and then finding the best way to make that frequency (probably backed up by a bunch of simulation and testing of that exact combination). We have landed most of this series of patches (with a few modifications to later patches to avoid adding a global alias).. ...but if you decided to go a different way we'll take your version of course (either now with a revert / re-pick or when we rebase later). :) -Doug
Hi Tomasz, On Mon, Jun 3, 2013 at 8:55 PM, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Yadwinder, > > On Thursday 30 of May 2013 12:25:40 Yadwinder Singh Brar wrote: >> Hi Doug, >> >> On Thu, May 30, 2013 at 5:14 AM, Doug Anderson <dianders@chromium.org> > wrote: >> > Vikas / Yadwinder, >> > >> > On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan@linaro.org> > wrote: >> >> From: Yadwinder Singh Brar <yadi.brar@samsung.com> >> >> >> >> This patch defines a common rate_table which will contain recommended p, >> >> m, s, k values for supported rates that needs to be changed for changing >> >> corresponding PLL's rate. >> >> >> >> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> >> >> --- >> >> >> >> drivers/clk/samsung/clk-exynos4.c | 8 ++++---- >> >> drivers/clk/samsung/clk-exynos5250.c | 14 +++++++------- >> >> drivers/clk/samsung/clk-pll.c | 14 ++++++++++++-- >> >> drivers/clk/samsung/clk-pll.h | 33 >> >> +++++++++++++++++++++++++++++++-- 4 files changed, 54 insertions(+), 15 >> >> deletions(-) >> > >> > I also reviewed this in our gerrit >> > <https://gerrit.chromium.org/gerrit/#/c/56742/>, but I'll summarize >> > here for the list... >> > >> >> struct clk * __init samsung_clk_register_pll35xx(const char *name, >> >> >> >> - const char *pname, const void __iomem *base) >> >> + const char *pname, const void __iomem *base, >> >> + const struct samsung_pll_rate_table *rate_table, >> >> + const unsigned int rate_count) >> > >> > Feels like you should document here that rate_table needs to be sorted >> > and the sort order. >> >> sure, we will add comment to sort the table in descending order. >> >> >> +struct samsung_pll_rate_table { >> >> + unsigned int rate; >> > >> > nit: extra space before "int" should be removed. >> >> ok >> >> > Also: you can include rate here if you need a convenient place to >> > store it (which sadly means that this structure can't be const). >> > ...but I do like Tomasz's idea of actually calculating it. You can't >> > know it at compile time since the parent rate comes from the device >> > tree. >> > >> > compatible = "samsung,clock-xxti"; >> > clock-frequency = <24000000>; >> >> Actually this table should contain the recommended values >> and if we see the user manual, the input(parent) rate is also a part >> of recommended >> table of different output rate for a particular PLL for that SoC. > > From what I understood in the documentation is that there is a set of > recommended P, M, S (, K) tuples for each PLL and they are not dependent on > input frequency - f_in and f_out are provided in the table just for reference > to see the relation between output frequency and input frequency. > If input rate(f_in) gets changed for PLL, then the corresponding output rates(f_out) will change by using same(common) set of recommended P, M, S (, K), and the new set of output rates(f_out) may not be the _required_ set of target rates. So we need different set of P, M, S (,K) values for different f_in. Table should contain set of P, M, S (,K) values for the _required_ target(f_out) rates for a particular input(f_in) rate. > I think we should ask some H/W engineer about that to make sure and choose the > proper implementation, which will work properly for future cases, instead of > ending with something that works just with current cases. > We already asked hardware engineer about PMS values for PLL, and we got a table containing recommended P, M ,S values for a given f_in(24 MHz) and required f_out rates. Please let me know, why you think we are specific to current cases only ? Regards, Yadwinder > Best regards, > -- > Tomasz Figa > Linux Kernel Developer > Samsung R&D Institute Poland > Samsung Electronics > >> So as Tomasz said input(parent) rate may change with board, >> then, do those corresponding recommended p, m, s, k will be valid? >> >> In case, input(parent) rate changes then we may need different set of p, m >> ,s, k values recommended for new input rate to get required(recommended to >> use) output rate. >> >> So, we think its better that the p, m, s and k along with the parent >> is known at the compile time ( or DT ?), >> as these p, m, s, k values are very much coupled with the parent rate >> to achieve the >> required(recommended to use) output rate. >> >> Also, since the sorted table is required (sorted based on "rate"), >> its better to have the rate in a const rate table. >> >> And the whole set of recommended values should come from same place(DT >> or static table), >> to keep the things simple and consistent. >> >> Moreover, practically for a particular SoC , we use the recommended >> input(parent) rate only for a PLL. >> So we should keep the things simple here presently. >> >> >> + unsigned int pdiv; >> >> + unsigned int mdiv; >> >> + unsigned int sdiv; >> >> + unsigned int kdiv; >> > >> > I think kdiv is signed. >> >> No, as these values should be the recommended values to be written in >> corresponding register bits. So it should remain unsigned. >> >> K value should be considered as negative only while recalculating rate. >> >> As per exynos5250 user manual's section 7.3.2 : >> " K value description "Postive value (Negative value)": >> Postive values is that you should write EPLLCON/VPLLCON register. >> Negative value is that you can calculate PLL output frequency with it." >> >> > -Doug >> >> Regards, >> Yadwinder & Vikas. >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" >> in the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Yadwinder, On Tuesday 04 of June 2013 17:02:48 Yadwinder Singh Brar wrote: > Hi Tomasz, > > On Mon, Jun 3, 2013 at 8:55 PM, Tomasz Figa <t.figa@samsung.com> wrote: > > Hi Yadwinder, > > > > On Thursday 30 of May 2013 12:25:40 Yadwinder Singh Brar wrote: > >> Hi Doug, > >> > >> On Thu, May 30, 2013 at 5:14 AM, Doug Anderson <dianders@chromium.org> > > > > wrote: > >> > Vikas / Yadwinder, > >> > > >> > On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan@linaro.org> > > > > wrote: > >> >> From: Yadwinder Singh Brar <yadi.brar@samsung.com> > >> >> > >> >> This patch defines a common rate_table which will contain recommended > >> >> p, > >> >> m, s, k values for supported rates that needs to be changed for > >> >> changing > >> >> corresponding PLL's rate. > >> >> > >> >> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> > >> >> --- > >> >> > >> >> drivers/clk/samsung/clk-exynos4.c | 8 ++++---- > >> >> drivers/clk/samsung/clk-exynos5250.c | 14 +++++++------- > >> >> drivers/clk/samsung/clk-pll.c | 14 ++++++++++++-- > >> >> drivers/clk/samsung/clk-pll.h | 33 > >> >> +++++++++++++++++++++++++++++++-- 4 files changed, 54 insertions(+), > >> >> 15 > >> >> deletions(-) > >> > > >> > I also reviewed this in our gerrit > >> > <https://gerrit.chromium.org/gerrit/#/c/56742/>, but I'll summarize > >> > here for the list... > >> > > >> >> struct clk * __init samsung_clk_register_pll35xx(const char *name, > >> >> > >> >> - const char *pname, const void __iomem *base) > >> >> + const char *pname, const void __iomem *base, > >> >> + const struct samsung_pll_rate_table > >> >> *rate_table, > >> >> + const unsigned int rate_count) > >> > > >> > Feels like you should document here that rate_table needs to be sorted > >> > and the sort order. > >> > >> sure, we will add comment to sort the table in descending order. > >> > >> >> +struct samsung_pll_rate_table { > >> >> + unsigned int rate; > >> > > >> > nit: extra space before "int" should be removed. > >> > >> ok > >> > >> > Also: you can include rate here if you need a convenient place to > >> > store it (which sadly means that this structure can't be const). > >> > ...but I do like Tomasz's idea of actually calculating it. You can't > >> > know it at compile time since the parent rate comes from the device > >> > tree. > >> > > >> > compatible = "samsung,clock-xxti"; > >> > clock-frequency = <24000000>; > >> > >> Actually this table should contain the recommended values > >> and if we see the user manual, the input(parent) rate is also a part > >> of recommended > >> table of different output rate for a particular PLL for that SoC. > > > > From what I understood in the documentation is that there is a set of > > recommended P, M, S (, K) tuples for each PLL and they are not dependent > > on > > input frequency - f_in and f_out are provided in the table just for > > reference to see the relation between output frequency and input > > frequency. > > If input rate(f_in) gets changed for PLL, then the corresponding > output rates(f_out) > will change by using same(common) set of recommended P, M, S (, K), > and the new set of output rates(f_out) may not be the _required_ set > of target rates. > So we need different set of P, M, S (,K) values for different f_in. > > Table should contain set of P, M, S (,K) values for the _required_ > target(f_out) rates > for a particular input(f_in) rate. I'm not sure what required rates you are talking about. For most PLLs the list of available frequencies seems to be defined by the set of supported PMS values and those are the frequencies that can be set by consumers, not the other way around. There are some cases when some particular frequency must be generated, like PLLs used for audio or video clock sources, but this just means that there must be an entry in PMS table that gives PLL configuration which produces such frequency with used PLL input clock. > > I think we should ask some H/W engineer about that to make sure and choose > > the proper implementation, which will work properly for future cases, > > instead of ending with something that works just with current cases. > > We already asked hardware engineer about PMS values for PLL, > and we got a table containing recommended P, M ,S values for a given > f_in(24 MHz) > and required f_out rates. This doesn't answer the question about using those PMS values with different input rate. Kukjin, maybe you can give some information on this or point to a person who could? > Please let me know, why you think we are specific to current cases only ? I don't like the idea of having separate tables for each input rate. Just imagine how much data would have to be added if boards with several different input rates showed up. Sure, if each input rate requires different set of PMS values by hardware design, it can't be helped, but if the same PMS values can be reused (even giving different output rates, but this is usually not important), one table can be used for all cases. Best regards,
On Wed, Jun 5, 2013 at 7:10 PM, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Yadwinder, > > On Tuesday 04 of June 2013 17:02:48 Yadwinder Singh Brar wrote: >> Hi Tomasz, >> >> On Mon, Jun 3, 2013 at 8:55 PM, Tomasz Figa <t.figa@samsung.com> wrote: >> > Hi Yadwinder, >> > >> > On Thursday 30 of May 2013 12:25:40 Yadwinder Singh Brar wrote: >> >> Hi Doug, >> >> >> >> On Thu, May 30, 2013 at 5:14 AM, Doug Anderson <dianders@chromium.org> >> > >> > wrote: >> >> > Vikas / Yadwinder, >> >> > >> >> > On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan <vikas.sajjan@linaro.org> >> > >> > wrote: >> >> >> From: Yadwinder Singh Brar <yadi.brar@samsung.com> >> >> >> >> >> >> This patch defines a common rate_table which will contain recommended >> >> >> p, >> >> >> m, s, k values for supported rates that needs to be changed for >> >> >> changing >> >> >> corresponding PLL's rate. >> >> >> >> >> >> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> >> >> >> --- >> >> >> >> >> >> drivers/clk/samsung/clk-exynos4.c | 8 ++++---- >> >> >> drivers/clk/samsung/clk-exynos5250.c | 14 +++++++------- >> >> >> drivers/clk/samsung/clk-pll.c | 14 ++++++++++++-- >> >> >> drivers/clk/samsung/clk-pll.h | 33 >> >> >> +++++++++++++++++++++++++++++++-- 4 files changed, 54 insertions(+), >> >> >> 15 >> >> >> deletions(-) >> >> > >> >> > I also reviewed this in our gerrit >> >> > <https://gerrit.chromium.org/gerrit/#/c/56742/>, but I'll summarize >> >> > here for the list... >> >> > >> >> >> struct clk * __init samsung_clk_register_pll35xx(const char *name, >> >> >> >> >> >> - const char *pname, const void __iomem *base) >> >> >> + const char *pname, const void __iomem *base, >> >> >> + const struct samsung_pll_rate_table >> >> >> *rate_table, >> >> >> + const unsigned int rate_count) >> >> > >> >> > Feels like you should document here that rate_table needs to be sorted >> >> > and the sort order. >> >> >> >> sure, we will add comment to sort the table in descending order. >> >> >> >> >> +struct samsung_pll_rate_table { >> >> >> + unsigned int rate; >> >> > >> >> > nit: extra space before "int" should be removed. >> >> >> >> ok >> >> >> >> > Also: you can include rate here if you need a convenient place to >> >> > store it (which sadly means that this structure can't be const). >> >> > ...but I do like Tomasz's idea of actually calculating it. You can't >> >> > know it at compile time since the parent rate comes from the device >> >> > tree. >> >> > >> >> > compatible = "samsung,clock-xxti"; >> >> > clock-frequency = <24000000>; >> >> >> >> Actually this table should contain the recommended values >> >> and if we see the user manual, the input(parent) rate is also a part >> >> of recommended >> >> table of different output rate for a particular PLL for that SoC. >> > >> > From what I understood in the documentation is that there is a set of >> > recommended P, M, S (, K) tuples for each PLL and they are not dependent >> > on >> > input frequency - f_in and f_out are provided in the table just for >> > reference to see the relation between output frequency and input >> > frequency. >> >> If input rate(f_in) gets changed for PLL, then the corresponding >> output rates(f_out) >> will change by using same(common) set of recommended P, M, S (, K), >> and the new set of output rates(f_out) may not be the _required_ set >> of target rates. >> So we need different set of P, M, S (,K) values for different f_in. >> >> Table should contain set of P, M, S (,K) values for the _required_ >> target(f_out) rates >> for a particular input(f_in) rate. > > I'm not sure what required rates you are talking about. For most PLLs the list > of available frequencies seems to be defined by the set of supported PMS values > and those are the frequencies that can be set by consumers, not the other way > around. > > There are some cases when some particular frequency must be generated, like > PLLs used for audio or video clock sources, but this just means that there > must be an entry in PMS table that gives PLL configuration which produces such > frequency with used PLL input clock. > Yes, I was talking about same cases. Perhaps,I think it holds true in general for PLLs, whose set_rate can be called. >> > I think we should ask some H/W engineer about that to make sure and choose >> > the proper implementation, which will work properly for future cases, >> > instead of ending with something that works just with current cases. >> >> We already asked hardware engineer about PMS values for PLL, >> and we got a table containing recommended P, M ,S values for a given >> f_in(24 MHz) >> and required f_out rates. > > This doesn't answer the question about using those PMS values with different > input rate. > > Kukjin, maybe you can give some information on this or point to a person who > could? > >> Please let me know, why you think we are specific to current cases only ? > > I don't like the idea of having separate tables for each input rate. Just > imagine how much data would have to be added if boards with several different > input rates showed up. > I think by declaring all these different table as __init, and creating a copy to be used while registering, we can save a little memory as well as the unnecessary cost which we have to bear while doing set_rate() and round_rate() by using single big table(for some time critical cases). > Sure, if each input rate requires different set of PMS values by hardware > design, it can't be helped, but if the same PMS values can be reused (even > giving different output rates, but this is usually not important), one table > can be used for all cases. > Its good to know whether same PMS values can be reused, from hardware guys. Using different tables we can always blindly stick to recommended values without bothering much every time, whether existing PMS can be reused or not while adding new cases. >> Regards, >> Yadwinder >> >> > Best regards, >> > -- >> > Tomasz Figa >> > Linux Kernel Developer >> > Samsung R&D Institute Poland >> > Samsung Electronics >> > >> >> So as Tomasz said input(parent) rate may change with board, >> >> then, do those corresponding recommended p, m, s, k will be valid? >> >> >> >> In case, input(parent) rate changes then we may need different set of p, >> >> m >> >> ,s, k values recommended for new input rate to get required(recommended >> >> to >> >> use) output rate. >> >> >> >> So, we think its better that the p, m, s and k along with the parent >> >> is known at the compile time ( or DT ?), >> >> as these p, m, s, k values are very much coupled with the parent rate >> >> to achieve the >> >> >> >> required(recommended to use) output rate. >> >> >> >> Also, since the sorted table is required (sorted based on "rate"), >> >> its better to have the rate in a const rate table. >> >> >> >> And the whole set of recommended values should come from same place(DT >> >> or static table), >> >> to keep the things simple and consistent. >> >> >> >> Moreover, practically for a particular SoC , we use the recommended >> >> input(parent) rate only for a PLL. >> >> So we should keep the things simple here presently. >> >> >> >> >> + unsigned int pdiv; >> >> >> + unsigned int mdiv; >> >> >> + unsigned int sdiv; >> >> >> + unsigned int kdiv; >> >> > >> >> > I think kdiv is signed. >> >> >> >> No, as these values should be the recommended values to be written in >> >> corresponding register bits. So it should remain unsigned. >> >> >> >> K value should be considered as negative only while recalculating rate. >> >> >> >> As per exynos5250 user manual's section 7.3.2 : >> >> " K value description "Postive value (Negative value)": >> >> Postive values is that you should write EPLLCON/VPLLCON register. >> >> Negative value is that you can calculate PLL output frequency with it." >> >> >> >> > -Doug >> >> >> >> Regards, >> >> Yadwinder & Vikas. >> >> -- >> >> To unsubscribe from this list: send the line "unsubscribe >> >> linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org >> >> More majordomo info at http://vger.kernel.org/majordomo-info.html >> >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" >> in the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thursday 06 of June 2013 14:31:56 Yadwinder Singh Brar wrote: > On Wed, Jun 5, 2013 at 7:10 PM, Tomasz Figa <t.figa@samsung.com> wrote: > > Hi Yadwinder, > > > > On Tuesday 04 of June 2013 17:02:48 Yadwinder Singh Brar wrote: > >> Hi Tomasz, > >> > >> On Mon, Jun 3, 2013 at 8:55 PM, Tomasz Figa <t.figa@samsung.com> wrote: > >> > Hi Yadwinder, > >> > > >> > On Thursday 30 of May 2013 12:25:40 Yadwinder Singh Brar wrote: > >> >> Hi Doug, > >> >> > >> >> On Thu, May 30, 2013 at 5:14 AM, Doug Anderson > >> >> <dianders@chromium.org> > >> > > >> > wrote: > >> >> > Vikas / Yadwinder, > >> >> > > >> >> > On Wed, May 29, 2013 at 6:37 AM, Vikas Sajjan > >> >> > <vikas.sajjan@linaro.org> > >> > > >> > wrote: > >> >> >> From: Yadwinder Singh Brar <yadi.brar@samsung.com> > >> >> >> > >> >> >> This patch defines a common rate_table which will contain > >> >> >> recommended > >> >> >> p, > >> >> >> m, s, k values for supported rates that needs to be changed for > >> >> >> changing > >> >> >> corresponding PLL's rate. > >> >> >> > >> >> >> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> > >> >> >> --- > >> >> >> > >> >> >> drivers/clk/samsung/clk-exynos4.c | 8 ++++---- > >> >> >> drivers/clk/samsung/clk-exynos5250.c | 14 +++++++------- > >> >> >> drivers/clk/samsung/clk-pll.c | 14 ++++++++++++-- > >> >> >> drivers/clk/samsung/clk-pll.h | 33 > >> >> >> +++++++++++++++++++++++++++++++-- 4 files changed, 54 > >> >> >> insertions(+), > >> >> >> 15 > >> >> >> deletions(-) > >> >> > > >> >> > I also reviewed this in our gerrit > >> >> > <https://gerrit.chromium.org/gerrit/#/c/56742/>, but I'll > >> >> > summarize > >> >> > here for the list... > >> >> > > >> >> >> struct clk * __init samsung_clk_register_pll35xx(const char > >> >> >> *name, > >> >> >> > >> >> >> - const char *pname, const void __iomem > >> >> >> *base) > >> >> >> + const char *pname, const void __iomem > >> >> >> *base, > >> >> >> + const struct samsung_pll_rate_table > >> >> >> *rate_table, > >> >> >> + const unsigned int rate_count) > >> >> > > >> >> > Feels like you should document here that rate_table needs to be > >> >> > sorted > >> >> > and the sort order. > >> >> > >> >> sure, we will add comment to sort the table in descending order. > >> >> > >> >> >> +struct samsung_pll_rate_table { > >> >> >> + unsigned int rate; > >> >> > > >> >> > nit: extra space before "int" should be removed. > >> >> > >> >> ok > >> >> > >> >> > Also: you can include rate here if you need a convenient place > >> >> > to > >> >> > store it (which sadly means that this structure can't be const). > >> >> > ...but I do like Tomasz's idea of actually calculating it. You > >> >> > can't > >> >> > know it at compile time since the parent rate comes from the > >> >> > device > >> >> > tree. > >> >> > > >> >> > compatible = "samsung,clock-xxti"; > >> >> > clock-frequency = <24000000>; > >> >> > >> >> Actually this table should contain the recommended values > >> >> and if we see the user manual, the input(parent) rate is also a > >> >> part > >> >> of recommended > >> >> table of different output rate for a particular PLL for that SoC. > >> > > >> > From what I understood in the documentation is that there is a set > >> > of > >> > recommended P, M, S (, K) tuples for each PLL and they are not > >> > dependent on > >> > input frequency - f_in and f_out are provided in the table just for > >> > reference to see the relation between output frequency and input > >> > frequency. > >> > >> If input rate(f_in) gets changed for PLL, then the corresponding > >> output rates(f_out) > >> will change by using same(common) set of recommended P, M, S (, K), > >> and the new set of output rates(f_out) may not be the _required_ set > >> of target rates. > >> So we need different set of P, M, S (,K) values for different f_in. > >> > >> Table should contain set of P, M, S (,K) values for the _required_ > >> target(f_out) rates > >> for a particular input(f_in) rate. > > > > I'm not sure what required rates you are talking about. For most PLLs > > the list of available frequencies seems to be defined by the set of > > supported PMS values and those are the frequencies that can be set by > > consumers, not the other way around. > > > > There are some cases when some particular frequency must be generated, > > like PLLs used for audio or video clock sources, but this just means > > that there must be an entry in PMS table that gives PLL configuration > > which produces such frequency with used PLL input clock. > > Yes, I was talking about same cases. Perhaps,I think it holds true in > general for PLLs, whose set_rate can be called. Not really. For PLLs used for general purpose clocking, like for CPU or GPU, there is usually no need to achieve certain frequency. Actually you might want to have as many as possible intermediate steps to improve frequency scaling efficiency. > >> > I think we should ask some H/W engineer about that to make sure and > >> > choose the proper implementation, which will work properly for > >> > future cases, instead of ending with something that works just > >> > with current cases.>> > >> We already asked hardware engineer about PMS values for PLL, > >> and we got a table containing recommended P, M ,S values for a given > >> f_in(24 MHz) > >> and required f_out rates. > > > > This doesn't answer the question about using those PMS values with > > different input rate. > > > > Kukjin, maybe you can give some information on this or point to a > > person who could? > > > >> Please let me know, why you think we are specific to current cases > >> only ?> > > I don't like the idea of having separate tables for each input rate. > > Just imagine how much data would have to be added if boards with > > several different input rates showed up. > > I think by declaring all these different table as __init, > and creating a copy to be used while registering, we can > save a little memory as well as the unnecessary cost which > we have to bear while doing set_rate() and round_rate() > by using single big table(for some time critical cases). Well, this is not really about memory, but rather the amount of code in the driver. The amount of memory needed for such setting table is rather insignificant. > > Sure, if each input rate requires different set of PMS values by > > hardware design, it can't be helped, but if the same PMS values can > > be reused (even giving different output rates, but this is usually > > not important), one table can be used for all cases. > > Its good to know whether same PMS values can be reused, from hardware > guys. Another thing worth knowing would be whether a different frequency of input clock is really allowed or the SoC supports only 24 MHz. If the latter is the case, then there is no need to bother supporting other frequencies. I'm waiting for some opinion from hardware engineers then. Best regards, Tomasz > Using different tables we can always blindly stick to recommended values > without bothering much every time, whether existing PMS can be reused > or not while adding new cases. > > >> Regards, > >> Yadwinder > >> > >> > Best regards, > >> > -- > >> > Tomasz Figa > >> > Linux Kernel Developer > >> > Samsung R&D Institute Poland > >> > Samsung Electronics > >> > > >> >> So as Tomasz said input(parent) rate may change with board, > >> >> then, do those corresponding recommended p, m, s, k will be valid? > >> >> > >> >> In case, input(parent) rate changes then we may need different set > >> >> of p, m > >> >> ,s, k values recommended for new input rate to get > >> >> required(recommended > >> >> to > >> >> use) output rate. > >> >> > >> >> So, we think its better that the p, m, s and k along with the > >> >> parent > >> >> is known at the compile time ( or DT ?), > >> >> as these p, m, s, k values are very much coupled with the parent > >> >> rate > >> >> to achieve the > >> >> > >> >> required(recommended to use) output rate. > >> >> > >> >> Also, since the sorted table is required (sorted based on "rate"), > >> >> its better to have the rate in a const rate table. > >> >> > >> >> And the whole set of recommended values should come from same > >> >> place(DT > >> >> or static table), > >> >> to keep the things simple and consistent. > >> >> > >> >> Moreover, practically for a particular SoC , we use the > >> >> recommended > >> >> input(parent) rate only for a PLL. > >> >> So we should keep the things simple here presently. > >> >> > >> >> >> + unsigned int pdiv; > >> >> >> + unsigned int mdiv; > >> >> >> + unsigned int sdiv; > >> >> >> + unsigned int kdiv; > >> >> > > >> >> > I think kdiv is signed. > >> >> > >> >> No, as these values should be the recommended values to be written > >> >> in > >> >> corresponding register bits. So it should remain unsigned. > >> >> > >> >> K value should be considered as negative only while recalculating > >> >> rate. > >> >> > >> >> As per exynos5250 user manual's section 7.3.2 : > >> >> " K value description "Postive value (Negative value)": > >> >> Postive values is that you should write EPLLCON/VPLLCON register. > >> >> Negative value is that you can calculate PLL output frequency with > >> >> it." > >> >> > >> >> > -Doug > >> >> > >> >> Regards, > >> >> Yadwinder & Vikas. > >> >> -- > >> >> To unsubscribe from this list: send the line "unsubscribe > >> >> linux-samsung-soc" in the body of a message to > >> >> majordomo@vger.kernel.org More majordomo info at > >> >> http://vger.kernel.org/majordomo-info.html>> > >> -- > >> To unsubscribe from this list: send the line "unsubscribe > >> linux-samsung-soc" in the body of a message to > >> majordomo@vger.kernel.org > >> More majordomo info at http://vger.kernel.org/majordomo-info.html > > -- > To unsubscribe from this list: send the line "unsubscribe > linux-samsung-soc" in the body of a message to > majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index cf7d4e7..beff8a1 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1021,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so reg_base + VPLL_CON0, pll_4650c); } else { apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", - reg_base + APLL_LOCK); + reg_base + APLL_LOCK, NULL, 0); mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", - reg_base + E4X12_MPLL_LOCK); + reg_base + E4X12_MPLL_LOCK, NULL, 0); epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", - reg_base + EPLL_LOCK); + reg_base + EPLL_LOCK, NULL, 0); vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll", - reg_base + VPLL_LOCK); + reg_base + VPLL_LOCK, NULL, 0); } samsung_clk_add_lookup(apll, fout_apll); diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 687b580..ddf10ca 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np) ext_clk_match); apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", - reg_base); + reg_base, NULL, 0); mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", - reg_base + 0x4000); + reg_base + 0x4000, NULL, 0); bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll", - reg_base + 0x20010); + reg_base + 0x20010, NULL, 0); gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll", - reg_base + 0x10050); + reg_base + 0x10050, NULL, 0); cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll", - reg_base + 0x10020); + reg_base + 0x10020, NULL, 0); epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", - reg_base + 0x10030); + reg_base + 0x10030, NULL, 0); vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc", - reg_base + 0x10040); + reg_base + 0x10040, NULL, 0); samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, ARRAY_SIZE(exynos5250_fixed_rate_clks)); diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 01f17cf..4b3b3f5 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -16,6 +16,8 @@ struct samsung_clk_pll { struct clk_hw hw; const void __iomem *base; + const struct samsung_pll_rate_table *rate_table; + unsigned int rate_count; }; #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw) @@ -62,7 +64,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = { }; struct clk * __init samsung_clk_register_pll35xx(const char *name, - const char *pname, const void __iomem *base) + const char *pname, const void __iomem *base, + const struct samsung_pll_rate_table *rate_table, + const unsigned int rate_count) { struct samsung_clk_pll *pll; struct clk *clk; @@ -82,6 +86,8 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name, pll->hw.init = &init; pll->base = base; + pll->rate_table = rate_table; + pll->rate_count = rate_count; clk = clk_register(NULL, &pll->hw); if (IS_ERR(clk)) { @@ -137,7 +143,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops = { }; struct clk * __init samsung_clk_register_pll36xx(const char *name, - const char *pname, const void __iomem *base) + const char *pname, const void __iomem *base, + const struct samsung_pll_rate_table *rate_table, + const unsigned int rate_count) { struct samsung_clk_pll *pll; struct clk *clk; @@ -157,6 +165,8 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name, pll->hw.init = &init; pll->base = base; + pll->rate_table = rate_table; + pll->rate_count = rate_count; clk = clk_register(NULL, &pll->hw); if (IS_ERR(clk)) { diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 1329522..a7c0f5a 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -12,6 +12,31 @@ #ifndef __SAMSUNG_CLK_PLL_H #define __SAMSUNG_CLK_PLL_H +#define PLL_35XX_RATE(_rate, _m, _p, _s) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + } + +#define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .kdiv = (_k), \ + } + +struct samsung_pll_rate_table { + unsigned int rate; + unsigned int pdiv; + unsigned int mdiv; + unsigned int sdiv; + unsigned int kdiv; +}; + enum pll45xx_type { pll_4500, pll_4502, @@ -25,9 +50,13 @@ enum pll46xx_type { }; extern struct clk * __init samsung_clk_register_pll35xx(const char *name, - const char *pname, const void __iomem *base); + const char *pname, const void __iomem *base, + const struct samsung_pll_rate_table *rate_table, + const unsigned int rate_count); extern struct clk * __init samsung_clk_register_pll36xx(const char *name, - const char *pname, const void __iomem *base); + const char *pname, const void __iomem *base, + const struct samsung_pll_rate_table *rate_table, + const unsigned int rate_count); extern struct clk * __init samsung_clk_register_pll45xx(const char *name, const char *pname, const void __iomem *con_reg, enum pll45xx_type type);