| Message ID | 1441731092-6513-1-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On 8 September 2015 at 17:51, Peter Maydell <peter.maydell@linaro.org> wrote: > > Another week, another pullreq... > > -- PMM > > The following changes since commit 8611280505119e296757a60711a881341603fa5a: > > target-microblaze: Use setcond for pcmp* (2015-09-08 08:49:33 +0200) > > are available in the git repository at: > > git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150908 > > for you to fetch changes up to 6fdf3282d16e7fb6e798824fb5f4f60c6a73067d: > > xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP (2015-09-08 17:38:45 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * Implement priority handling properly via GICC_APR > * Enable TZ extensions on the GIC if we're using them > * Minor preparatory patches for EL3 support > * cadence_gem: Correct Marvell PHY SPCFC reset value > * Support AHCI in ZynqMP Applied, thanks. -- PMM
Another week, another pullreq... -- PMM The following changes since commit 8611280505119e296757a60711a881341603fa5a: target-microblaze: Use setcond for pcmp* (2015-09-08 08:49:33 +0200) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150908 for you to fetch changes up to 6fdf3282d16e7fb6e798824fb5f4f60c6a73067d: xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP (2015-09-08 17:38:45 +0100) ---------------------------------------------------------------- target-arm queue: * Implement priority handling properly via GICC_APR * Enable TZ extensions on the GIC if we're using them * Minor preparatory patches for EL3 support * cadence_gem: Correct Marvell PHY SPCFC reset value * Support AHCI in ZynqMP ---------------------------------------------------------------- Alistair Francis (5): cadence_gem: Correct Marvell PHY SPCFC reset value ahci: Separate the AHCI state structure into the header ahci.c: Don't assume AHCIState's parent is AHCIPCIState xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP Edgar E. Iglesias (3): target-arm: Log the target EL when taking exceptions target-arm: Correct opc1 for AT_S12Exx target-arm: Add AArch64 access to PAR_EL1 Peter Crosthwaite (1): qom: Add recursive version of object_child_for_each Peter Maydell (10): armv7m_nvic: Implement ICSR without using internal GIC state hw/intc/arm_gic: Running priority is group priority, not full priority hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers hw/intc/arm_gic: Drop running_irq and last_active arrays hw/intc/arm_gic: Actually set the active bits for active interrupts hw/arm: new interface for devices which need to behave differently for kernel boot hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs hw/arm/virt: Default to not providing TrustZone support hw/arm/virt: Enable TZ extensions on the GIC if we are using them Sergey Sorokin (1): target-arm: Fix default_exception_el() function for the case when EL3 is not supported hw/arm/boot.c | 34 ++++++ hw/arm/virt.c | 14 ++- hw/arm/xlnx-zynqmp.c | 32 +++-- hw/cpu/a15mpcore.c | 13 +++ hw/cpu/a9mpcore.c | 11 ++ hw/ide/ahci.c | 26 ++--- hw/ide/ahci.h | 16 +++ hw/intc/arm_gic.c | 245 ++++++++++++++++++++++++++++++++++----- hw/intc/arm_gic_common.c | 59 ++++++++-- hw/intc/armv7m_nvic.c | 13 +-- hw/net/cadence_gem.c | 2 +- include/hw/arm/linux-boot-if.h | 43 +++++++ include/hw/arm/xlnx-zynqmp.h | 3 + include/hw/intc/arm_gic_common.h | 12 +- include/qom/object.h | 15 +++ qom/object.c | 25 +++- target-arm/helper-a64.c | 3 +- target-arm/helper.c | 14 ++- target-arm/translate-a64.c | 6 +- target-arm/translate.c | 6 +- target-arm/translate.h | 5 +- 21 files changed, 493 insertions(+), 104 deletions(-) create mode 100644 include/hw/arm/linux-boot-if.h