| Message ID | 1435137673-1629-3-git-send-email-vaibhav.hiremath@linaro.org |
|---|---|
| State | New |
| Headers | show |
On Thursday 25 June 2015 05:33 AM, Krzysztof Kozlowski wrote: > 2015-06-24 18:21 GMT+09:00 Vaibhav Hiremath <vaibhav.hiremath@linaro.org>: >> As per the spec, bit 1 (INT_CLEAR_MODE) of reg addr 0xe >> (page 0) controls the method of clearing interrupt >> status of 88pm800 family of devices; >> >> 0: clear on read >> 1: clear on write >> >> This patch allows to configure this field, through DT. >> >> Also, as suggested by "Lee Jones" renaming DT property and variable >> field to appropriate name. >> >> Signed-off-by: Zhao Ye <zhaoy@marvell.com> >> Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org> > > It does not look like a property of the board. Instead it looks like a > runtime configuration so it should not be part of DT bindings. > Why do you say that? It is very well feature of 88PM860 device, where you can control irq clear operation (either read/write). Thanks, Vaibhav > I understand that previously this was configured by platform data and > now you want to move everything to DT. But this does not belong to > DT... > Thats not completely true. I think DT is the right place for this configuration. Thanks, Vaibhav -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thursday 25 June 2015 11:02 AM, Krzysztof Kozlowski wrote: > On 25.06.2015 14:26, Vaibhav Hiremath wrote: >> >> >> On Thursday 25 June 2015 05:33 AM, Krzysztof Kozlowski wrote: >>> 2015-06-24 18:21 GMT+09:00 Vaibhav Hiremath >>> <vaibhav.hiremath@linaro.org>: >>>> As per the spec, bit 1 (INT_CLEAR_MODE) of reg addr 0xe >>>> (page 0) controls the method of clearing interrupt >>>> status of 88pm800 family of devices; >>>> >>>> 0: clear on read >>>> 1: clear on write >>>> >>>> This patch allows to configure this field, through DT. >>>> >>>> Also, as suggested by "Lee Jones" renaming DT property and variable >>>> field to appropriate name. >>>> >>>> Signed-off-by: Zhao Ye <zhaoy@marvell.com> >>>> Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org> >>> >>> It does not look like a property of the board. Instead it looks like a >>> runtime configuration so it should not be part of DT bindings. >>> >> >> Why do you say that? >> >> It is very well feature of 88PM860 device, where you can control irq >> clear operation (either read/write). >> >> >> Thanks, >> Vaibhav >> >>> I understand that previously this was configured by platform data and >>> now you want to move everything to DT. But this does not belong to >>> DT... >>> >> >> Thats not completely true. >> I think DT is the right place for this configuration. > > DT and its bindings describe the specific board or device. Let me quote: > <<The "Open Firmware Device Tree", or simply Device Tree (DT), is a data > structure and language for describing hardware. More specifically, it > is a description of hardware that is readable by an operating system...>> > > Whether you clear interrupts by writing or reading is configured during > runtime and it is completely independent to wiring. Each board with > 88pm800 would allow both methods. So this is not a property of hardware > in the terms of open firmware. This is a runtime configuration. > Yes, Fair enough... I see very little value in runtime configuration, why not just do it only way (either read or write)? I would prefer to just set it by default (during init), to clear irq on write. Thanks, Vaibhav -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c index 059f01a..c1a6306 100644 --- a/drivers/mfd/88pm800.c +++ b/drivers/mfd/88pm800.c @@ -376,7 +376,7 @@ static int device_irq_init_800(struct pm80x_chip *chip) { struct regmap *map = chip->regmap; unsigned long flags = IRQF_ONESHOT; - int data, mask, ret = -EINVAL; + int irq_clr_mode, mask, ret = -EINVAL; if (!map || !chip->irq) { dev_err(chip->dev, "incorrect parameters\n"); @@ -384,15 +384,16 @@ static int device_irq_init_800(struct pm80x_chip *chip) } /* - * irq_mode defines the way of clearing interrupt. it's read-clear by - * default. + * irq_clr_on_wr defines the way of clearing interrupt by + * read/write(0/1). It's read-clear by default. */ mask = PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR | PM800_WAKEUP2_INT_MASK; - data = PM800_WAKEUP2_INT_CLEAR; - ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data); + irq_clr_mode = (chip->irq_clr_on_wr) ? + PM800_WAKEUP2_INT_WRITE_CLEAR : PM800_WAKEUP2_INT_READ_CLEAR; + ret = regmap_update_bits(map, PM800_WAKEUP2, mask, irq_clr_mode); if (ret < 0) goto out; @@ -514,6 +515,7 @@ static int device_800_init(struct pm80x_chip *chip, } chip->regmap_irq_chip = &pm800_irq_chip; + chip->irq_clr_on_wr = pdata->irq_clr_on_wr; ret = device_irq_init_800(chip); if (ret < 0) { @@ -568,6 +570,9 @@ static int pm800_probe(struct i2c_client *client, dev_err(&client->dev, "failed to allocaate memory\n"); return -ENOMEM; } + + pdata->irq_clr_on_wr = of_property_read_bool(np, + "marvell,irq-clr-on-write"); } ret = pm80x_init(client); diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h index 97cb283..94b3dcd 100644 --- a/include/linux/mfd/88pm80x.h +++ b/include/linux/mfd/88pm80x.h @@ -77,6 +77,8 @@ enum { #define PM800_WAKEUP2 (0x0E) #define PM800_WAKEUP2_INV_INT (1 << 0) #define PM800_WAKEUP2_INT_CLEAR (1 << 1) +#define PM800_WAKEUP2_INT_READ_CLEAR (0 << 1) +#define PM800_WAKEUP2_INT_WRITE_CLEAR (1 << 1) #define PM800_WAKEUP2_INT_MASK (1 << 2) #define PM800_POWER_UP_LOG (0x10) @@ -300,7 +302,7 @@ struct pm80x_chip { struct regmap_irq_chip_data *irq_data; int type; int irq; - int irq_mode; + int irq_clr_on_wr; /* '1': Clear on write, '0': Clear on read*/ unsigned long wu_flag; spinlock_t lock; }; @@ -315,7 +317,7 @@ struct pm80x_platform_data { */ struct regulator_init_data *regulators[PM800_ID_RG_MAX]; unsigned int num_regulators; - int irq_mode; /* Clear interrupt by read/write(0/1) */ + int irq_clr_on_wr; /* Clear interrupt by read/write(0/1) */ int batt_det; /* enable/disable */ int (*plat_config)(struct pm80x_chip *chip, struct pm80x_platform_data *pdata);