@@ -170,7 +170,6 @@ static void bamboo_init(MachineState *machine)
= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
- qemu_irq *pic;
qemu_irq *irqs;
PCIBus *pcibus;
PowerPCCPU *cpu;
@@ -202,7 +201,7 @@ static void bamboo_init(MachineState *machine)
irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
- pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
+ machine->irqs = ppcuic_init(env, irqs, 0x0C0, 0, 1);
/* SDRAM controller */
memset(ram_bases, 0, sizeof(ram_bases));
@@ -212,14 +211,16 @@ static void bamboo_init(MachineState *machine)
ram_bases, ram_sizes,
ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, 1);
+ ppc4xx_sdram_init(env, machine->irqs[14], PPC440EP_SDRAM_NR_BANKS,
+ ram_memories, ram_bases, ram_sizes, 1);
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
PPC440EP_PCI_CONFIG,
- pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]],
- pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]],
+ machine->irqs[pci_irq_nrs[0]],
+ machine->irqs[pci_irq_nrs[1]],
+ machine->irqs[pci_irq_nrs[2]],
+ machine->irqs[pci_irq_nrs[3]],
NULL);
pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
if (!pcibus) {
@@ -232,12 +233,12 @@ static void bamboo_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa);
if (serial_hds[0] != NULL) {
- serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
+ serial_mm_init(address_space_mem, 0xef600300, 0, machine->irqs[0],
PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
DEVICE_BIG_ENDIAN);
}
if (serial_hds[1] != NULL) {
- serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
+ serial_mm_init(address_space_mem, 0xef600400, 0, machine->irqs[1],
PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
DEVICE_BIG_ENDIAN);
}
@@ -160,6 +160,7 @@ struct MachineState {
char *initrd_filename;
const char *cpu_model;
AccelState *accelerator;
+ qemu_irq *irqs;
};
#endif