| Message ID | 1367235107-31328-1-git-send-email-inderpal.singh@linaro.org |
|---|---|
| State | New |
| Headers | show |
working fine. Tested-by: Chander Kashyap <chander.kashyap@linaro.org <pekon@ti.com>> On 29 April 2013 17:01, Inderpal Singh <inderpal.singh@linaro.org> wrote: > The kernel crashes while resuming from AFTR idle mode. It happens > because L2 cache was not going into retention state. > > This patch configures the USE_RETENTION bit of ARM_L2_OPTION register > so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of > ARM_COMMON_OPTION register for L2RSTDISABLE signal. > > Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> > --- > > Tested on arndale board on arm-soc next/soc branch. > > arch/arm/mach-exynos/include/mach/regs-pmu.h | 1 + > arch/arm/mach-exynos/pmu.c | 5 ++--- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h > b/arch/arm/mach-exynos/include/mach/regs-pmu.h > index 3f30aa1..57344b7 100644 > --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h > +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h > @@ -344,6 +344,7 @@ > #define EXYNOS5_FSYS_ARM_OPTION > S5P_PMUREG(0x2208) > #define EXYNOS5_ISP_ARM_OPTION > S5P_PMUREG(0x2288) > #define EXYNOS5_ARM_COMMON_OPTION > S5P_PMUREG(0x2408) > +#define EXYNOS5_ARM_L2_OPTION > S5P_PMUREG(0x2608) > #define EXYNOS5_TOP_PWR_OPTION > S5P_PMUREG(0x2C48) > #define EXYNOS5_TOP_PWR_SYSMEM_OPTION > S5P_PMUREG(0x2CC8) > #define EXYNOS5_JPEG_MEM_OPTION > S5P_PMUREG(0x2F48) > diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c > index daebc1a..97d6885 100644 > --- a/arch/arm/mach-exynos/pmu.c > +++ b/arch/arm/mach-exynos/pmu.c > @@ -228,6 +228,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] > = { > { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, > { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, > { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, > + { EXYNOS5_ARM_L2_OPTION, { 0x10, 0x10, 0x0 > } }, > { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, > { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, > { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, > @@ -353,11 +354,9 @@ static void exynos5_init_pmu(void) > > /* > * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable > - * MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable > */ > tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION); > - tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL | > - EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN); > + tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; > __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); > > /* > -- > 1.7.9.5 > > -- > To unsubscribe from this list: send the line "unsubscribe > linux-samsung-soc" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >
On 29 April 2013 17:01, Inderpal Singh <inderpal.singh@linaro.org> wrote: > > The kernel crashes while resuming from AFTR idle mode. It happens > because L2 cache was not going into retention state. > > This patch configures the USE_RETENTION bit of ARM_L2_OPTION register > so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of > ARM_COMMON_OPTION register for L2RSTDISABLE signal. > > Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> > --- > > Tested on arndale board on arm-soc next/soc branch. > > arch/arm/mach-exynos/include/mach/regs-pmu.h | 1 + > arch/arm/mach-exynos/pmu.c | 5 ++--- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h > index 3f30aa1..57344b7 100644 > --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h > +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h > @@ -344,6 +344,7 @@ > #define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208) > #define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288) > #define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408) > +#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608) > #define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48) > #define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8) > #define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48) > diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c > index daebc1a..97d6885 100644 > --- a/arch/arm/mach-exynos/pmu.c > +++ b/arch/arm/mach-exynos/pmu.c > @@ -228,6 +228,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = { > { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, > { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, > { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, > + { EXYNOS5_ARM_L2_OPTION, { 0x10, 0x10, 0x0 } }, > { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, > { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, > { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, > @@ -353,11 +354,9 @@ static void exynos5_init_pmu(void) > > /* > * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable > - * MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable > */ > tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION); > - tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL | > - EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN); > + tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; > __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); > > /* > -- > 1.7.9.5 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html working fine. Tested-by: Chander Kashyap <chander.kashyap@linaro.org> -- with warm regards, Chander Kashyap
On Mon, Apr 29, 2013 at 05:01:47PM +0530, Inderpal Singh wrote: > The kernel crashes while resuming from AFTR idle mode. It happens > because L2 cache was not going into retention state. > > This patch configures the USE_RETENTION bit of ARM_L2_OPTION register > so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of > ARM_COMMON_OPTION register for L2RSTDISABLE signal. > > Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> I haven't seen any activity from Kgene on this, but it seems reasonably bad (and the fix is self-contained). Applying to arm-soc fixes branch. -Olof
Olof Johansson wrote: > > On Mon, Apr 29, 2013 at 05:01:47PM +0530, Inderpal Singh wrote: > > The kernel crashes while resuming from AFTR idle mode. It happens > > because L2 cache was not going into retention state. > > > > This patch configures the USE_RETENTION bit of ARM_L2_OPTION register > > so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of > > ARM_COMMON_OPTION register for L2RSTDISABLE signal. > > > > Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> > > I haven't seen any activity from Kgene on this, but it seems reasonably > bad I spent time with my family last week... > (and the fix is self-contained). Applying to arm-soc fixes branch. > Anyway, thanks. - Kukjin
On Thu, May 9, 2013 at 4:32 PM, Kukjin Kim <kgene.kim@samsung.com> wrote: > Olof Johansson wrote: >> >> On Mon, Apr 29, 2013 at 05:01:47PM +0530, Inderpal Singh wrote: >> > The kernel crashes while resuming from AFTR idle mode. It happens >> > because L2 cache was not going into retention state. >> > >> > This patch configures the USE_RETENTION bit of ARM_L2_OPTION register >> > so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of >> > ARM_COMMON_OPTION register for L2RSTDISABLE signal. >> > >> > Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> >> >> I haven't seen any activity from Kgene on this, but it seems reasonably >> bad > > I spent time with my family last week... > >> (and the fix is self-contained). Applying to arm-soc fixes branch. >> > Anyway, thanks. No worries. :) -Olof
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 3f30aa1..57344b7 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -344,6 +344,7 @@ #define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208) #define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288) #define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408) +#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608) #define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48) #define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8) #define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48) diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index daebc1a..97d6885 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -228,6 +228,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = { { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, + { EXYNOS5_ARM_L2_OPTION, { 0x10, 0x10, 0x0 } }, { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, @@ -353,11 +354,9 @@ static void exynos5_init_pmu(void) /* * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable - * MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable */ tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION); - tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL | - EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN); + tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); /*
The kernel crashes while resuming from AFTR idle mode. It happens because L2 cache was not going into retention state. This patch configures the USE_RETENTION bit of ARM_L2_OPTION register so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of ARM_COMMON_OPTION register for L2RSTDISABLE signal. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> --- Tested on arndale board on arm-soc next/soc branch. arch/arm/mach-exynos/include/mach/regs-pmu.h | 1 + arch/arm/mach-exynos/pmu.c | 5 ++--- 2 files changed, 3 insertions(+), 3 deletions(-)