| Message ID | 1431351638-21705-1-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On 11 May 2015 at 14:40, Peter Maydell <peter.maydell@linaro.org> wrote: > This is mostly the GIC TZ changes, with a couple of other > minor bugfixes. > > -- PMM > > The following changes since commit b951cda21d6b232f138ccf008e12bce8ddc95465: > > Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2015-05-11 12:01:09 +0100) > > are available in the git repository at: > > > git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150511 > > for you to fetch changes up to 49855cdaed78f66f501df6e18b8b3b7012cea2eb: > > hw/arm/highbank.c: Wire FIQ between CPU <> GIC (2015-05-11 14:28:54 +0100) Oops: hw/intc/arm_gic_kvm.c: In function ‘kvm_arm_gic_put’: hw/intc/arm_gic_kvm.c:357:12: error: ‘GICState’ has no member named ‘enabled’ hw/intc/arm_gic_kvm.c: In function ‘kvm_arm_gic_get’: hw/intc/arm_gic_kvm.c:458:6: error: ‘GICState’ has no member named ‘enabled’ I could have sworn I'd tested that. Will fix & respin... -- PMM
On 12 May 2015 at 09:10, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote: > On Tue, May 12, 2015 at 1:01 AM, Peter Maydell <peter.maydell@linaro.org> wrote: >> I could have sworn I'd tested that. Will fix & respin... >> > > Feel like grabbing the new Zynq series (v9) with it? :) Maybe. I was going to except for that last minute issue in v8. No real issue with doing two pullreqs, though; in some ways that's better than one large one. -- PMM
This is mostly the GIC TZ changes, with a couple of other minor bugfixes. -- PMM The following changes since commit b951cda21d6b232f138ccf008e12bce8ddc95465: Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2015-05-11 12:01:09 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150511 for you to fetch changes up to 49855cdaed78f66f501df6e18b8b3b7012cea2eb: hw/arm/highbank.c: Wire FIQ between CPU <> GIC (2015-05-11 14:28:54 +0100) ---------------------------------------------------------------- target-arm queue: * Support TZ and grouping in the GIC * hw/sd: sd_reset cleanup * armv7m_nvic: fix bug in systick device ---------------------------------------------------------------- Adrian Huang (1): armv7m_nvic: systick: Reload the RELOAD value and count down only if ENABLE bit is set Fabian Aggeler (12): hw/intc/arm_gic: Create outbound FIQ lines hw/intc/arm_gic: Add Security Extensions property hw/intc/arm_gic: Add Interrupt Group Registers hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked hw/intc/arm_gic: Implement Non-secure view of RPR hw/intc/arm_gic: Restrict priority view hw/intc/arm_gic: Handle grouping for GICC_HPPIR hw/intc/arm_gic: Change behavior of EOIR writes hw/intc/arm_gic: Change behavior of IAR writes hw/arm/vexpress.c: Wire FIQ between CPU <> GIC Greg Bellows (1): hw/arm/virt.c: Wire FIQ between CPU <> GIC Peter Maydell (5): hw/sd: Don't pass BlockBackend to sd_reset() hw/intc/arm_gic: Switch to read/write callbacks with tx attributes hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state hw/intc/arm_gic: Add grouping support to gic_update() hw/arm/highbank.c: Wire FIQ between CPU <> GIC hw/arm/highbank.c | 3 + hw/arm/vexpress.c | 2 + hw/arm/virt.c | 2 + hw/intc/arm_gic.c | 469 ++++++++++++++++++++++++++++++++------- hw/intc/arm_gic_common.c | 22 +- hw/intc/arm_gic_kvm.c | 51 +++-- hw/intc/armv7m_nvic.c | 17 +- hw/intc/gic_internal.h | 29 ++- hw/sd/sd.c | 17 +- include/hw/intc/arm_gic_common.h | 24 +- 10 files changed, 509 insertions(+), 127 deletions(-)