diff mbox

[edk2,5/6] ArmPkg: enable ARE bit before driving GICv3 in native mode

Message ID 1423725731-31430-6-git-send-email-olivier.martin@arm.com
State New
Headers show

Commit Message

Olivier Martin Feb. 12, 2015, 7:22 a.m. UTC 
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

The GICv3 driver must use native mode to drive a GICv3 due to
the fact that v2 compatibility is optional in the v3 spec.
However, if v2 compatibility is implemented, it is the default
and needs to be disabled first by setting the Affinity Routing
Enable (ARE) bit.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
---
 ArmPkg/ArmPkg.dec                         | 3 +++
 ArmPkg/Drivers/ArmGic/ArmGicDxe.inf       | 3 ++-
 ArmPkg/Drivers/ArmGic/ArmGicLib.c         | 6 +++---
 ArmPkg/Drivers/ArmGic/ArmGicLib.inf       | 3 +++
 ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf    | 3 +++
 ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 8 ++++++++
 ArmPkg/Include/Library/ArmGicLib.h        | 3 +++
 7 files changed, 25 insertions(+), 4 deletions(-)

--
1.9.1


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No:  2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No:  2548782


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Comments

Ard Biesheuvel Feb. 12, 2015, 10:25 a.m. UTC | #1 
On 12 February 2015 at 15:22, Olivier Martin <olivier.martin@arm.com> wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> The GICv3 driver must use native mode to drive a GICv3 due to
> the fact that v2 compatibility is optional in the v3 spec.
> However, if v2 compatibility is implemented, it is the default
> and needs to be disabled first by setting the Affinity Routing
> Enable (ARE) bit.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Reviewed-By: Olivier Martin <olivier.martin@arm.com>

You have added quite a lot to this patch, so could you please maybe
replace your reviewed-by with something like

"""
[added PCD that allows forcing the GICv3 driver to drive the GIC in v2 mode]
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
"""



> ---
>  ArmPkg/ArmPkg.dec                         | 3 +++
>  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf       | 3 ++-
>  ArmPkg/Drivers/ArmGic/ArmGicLib.c         | 6 +++---
>  ArmPkg/Drivers/ArmGic/ArmGicLib.inf       | 3 +++
>  ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf    | 3 +++
>  ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 8 ++++++++
>  ArmPkg/Include/Library/ArmGicLib.h        | 3 +++
>  7 files changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
> index 75960ed..ced3929 100644
> --- a/ArmPkg/ArmPkg.dec
> +++ b/ArmPkg/ArmPkg.dec
> @@ -69,6 +69,9 @@
>    # Linux (instead of PSCI)
>    gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
>
> +  # Define if the GICv3 controller should use the GICv2 legacy
> +  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
> +
>  [PcdsFixedAtBuild.common]
>    gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
>
> diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> index 92f3b1d..e554301 100644
> --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> @@ -1,7 +1,7 @@
>  #/** @file
>  #
>  #  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
> -#  Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
> +#  Copyright (c) 2012 - 2015, ARM Ltd. All rights reserved.<BR>
>  #
>  #  This program and the accompanying materials
>  #  are licensed and made available under the terms and conditions of the BSD License
> @@ -54,6 +54,7 @@
>    gArmTokenSpaceGuid.PcdGicDistributorBase
>    gArmTokenSpaceGuid.PcdGicRedistributorsBase
>    gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
> +  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
>
>  [Depex]
>    gEfiCpuArchProtocolGuid
> diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> index 7c53e39..48708e3 100644
> --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> @@ -186,7 +186,7 @@ ArmGicEnableInterrupt (
>    RegShift = Source % 32;
>
>    Revision = ArmGicGetSupportedArchRevision ();
> -  if (Revision == ARM_GIC_ARCH_REVISION_2) {
> +  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
>      // Write set-enable register
>      MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
>    } else {
> @@ -219,7 +219,7 @@ ArmGicDisableInterrupt (
>    RegShift = Source % 32;
>
>    Revision = ArmGicGetSupportedArchRevision ();
> -  if (Revision == ARM_GIC_ARCH_REVISION_2) {
> +  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
>      // Write clear-enable register
>      MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
>    } else {
> @@ -252,7 +252,7 @@ ArmGicIsInterruptEnabled (
>    RegShift = Source % 32;
>
>    Revision = ArmGicGetSupportedArchRevision ();
> -  if (Revision == ARM_GIC_ARCH_REVISION_2) {
> +  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
>      Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
>    } else {
>      GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);
> diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> index 9f46679..2ae3fd3 100644
> --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> @@ -47,3 +47,6 @@
>
>  [Pcd]
>    gArmPlatformTokenSpaceGuid.PcdCoreCount
> +
> +[FeaturePcd]
> +  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
> diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
> index 9097b37..7d4e49e 100644
> --- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
> +++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
> @@ -48,3 +48,6 @@
>
>  [Pcd]
>    gArmPlatformTokenSpaceGuid.PcdCoreCount
> +
> +[FeaturePcd]
> +  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
> diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
> index e94e015..f3bf191 100644
> --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
> +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
> @@ -249,6 +249,14 @@ GicV3DxeInitialize (
>    mGicRedistributorsBase = PcdGet32 (PcdGicRedistributorsBase);
>    mGicNumInterrupts      = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
>
> +  //
> +  // We will be driving this GIC in native v3 mode, i.e., with Affinity
> +  // Routing enabled. So ensure that the ARE bit is set.
> +  //
> +  if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
> +    MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
> +  }
> +
>    for (Index = 0; Index < mGicNumInterrupts; Index++) {
>      GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
>
> diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
> index 2ab9977..e2a4818 100644
> --- a/ArmPkg/Include/Library/ArmGicLib.h
> +++ b/ArmPkg/Include/Library/ArmGicLib.h
> @@ -53,6 +53,9 @@ typedef enum {
>  // GICv3 specific registers
>  #define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers
>
> +// the Affinity Routing Enable (ARE) bit in GICD_CTLR
> +#define ARM_GIC_ICDDCR_ARE      (1 << 4)
> +
>  //
>  // GIC Redistributor
>  //
> --
> 1.9.1
>
>
> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.
>
> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No:  2557590
> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No:  2548782
>

------------------------------------------------------------------------------
Dive into the World of Parallel Programming. The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net/
diff mbox

Patch

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 75960ed..ced3929 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -69,6 +69,9 @@ 
   # Linux (instead of PSCI)
   gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033

+  # Define if the GICv3 controller should use the GICv2 legacy
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
+
 [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
index 92f3b1d..e554301 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
@@ -1,7 +1,7 @@ 
 #/** @file
 #
 #  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#  Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2012 - 2015, ARM Ltd. All rights reserved.<BR>
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -54,6 +54,7 @@ 
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gArmTokenSpaceGuid.PcdGicRedistributorsBase
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy

 [Depex]
   gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 7c53e39..48708e3 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -186,7 +186,7 @@  ArmGicEnableInterrupt (
   RegShift = Source % 32;

   Revision = ArmGicGetSupportedArchRevision ();
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
     // Write set-enable register
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
   } else {
@@ -219,7 +219,7 @@  ArmGicDisableInterrupt (
   RegShift = Source % 32;

   Revision = ArmGicGetSupportedArchRevision ();
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
     // Write clear-enable register
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
   } else {
@@ -252,7 +252,7 @@  ArmGicIsInterruptEnabled (
   RegShift = Source % 32;

   Revision = ArmGicGetSupportedArchRevision ();
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
     Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
   } else {
     GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
index 9f46679..2ae3fd3 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
@@ -47,3 +47,6 @@ 

 [Pcd]
   gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+[FeaturePcd]
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
index 9097b37..7d4e49e 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
@@ -48,3 +48,6 @@ 

 [Pcd]
   gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+[FeaturePcd]
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index e94e015..f3bf191 100644
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -249,6 +249,14 @@  GicV3DxeInitialize (
   mGicRedistributorsBase = PcdGet32 (PcdGicRedistributorsBase);
   mGicNumInterrupts      = ArmGicGetMaxNumInterrupts (mGicDistributorBase);

+  //
+  // We will be driving this GIC in native v3 mode, i.e., with Affinity
+  // Routing enabled. So ensure that the ARE bit is set.
+  //
+  if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
+    MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
+  }
+
   for (Index = 0; Index < mGicNumInterrupts; Index++) {
     GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index 2ab9977..e2a4818 100644
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -53,6 +53,9 @@  typedef enum {
 // GICv3 specific registers
 #define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers

+// the Affinity Routing Enable (ARE) bit in GICD_CTLR
+#define ARM_GIC_ICDDCR_ARE      (1 << 4)
+
 //
 // GIC Redistributor
 //