| Message ID | 1413374624-30066-2-git-send-email-lorenzo.pieralisi@arm.com |
|---|---|
| State | New |
| Headers | show |
On Wed, Oct 15, 2014 at 01:03:41PM +0100, Lorenzo Pieralisi wrote: > ARM relies on the standard implementation of pci_resource_to_user() > which actually is an identity map and exports to user space > PCI memory resources as they are stored in PCI devices resources (ie BARs) > which represent CPU physical addresses (fixed-up using BUS to CPU > address conversions) not PCI bus addresses. This paragraph seems wrong. It first says that PCI memory resources contain the same values that the PCI device has in its BAR. It then goes on to say that they are CPU physical addresses. That is not true. For example, DC21285 systems always have done this as: the PCI bars contain the _bus_ addresses, which tend to be in the range 0 to 0x7fffffff. These correspond with a CPU physical address of 0x80000000 to 0xffffffff. The PCI bus resources for IOMEM resources contains the CPU physical address of the mapping. > On platforms where the mapping between CPU and BUS address is not a 1:1 > mapping this is erroneous, in that an additional shift is applied to > an already fixed-up offset passed from userspace. Yes, I think this is a correct patch inspite of the description. :)
Hi Russell, thanks for having a look. On Wed, Oct 15, 2014 at 11:29:32PM +0100, Russell King - ARM Linux wrote: > On Wed, Oct 15, 2014 at 01:03:41PM +0100, Lorenzo Pieralisi wrote: > > ARM relies on the standard implementation of pci_resource_to_user() > > which actually is an identity map and exports to user space > > PCI memory resources as they are stored in PCI devices resources (ie BARs) > > which represent CPU physical addresses (fixed-up using BUS to CPU > > address conversions) not PCI bus addresses. > > This paragraph seems wrong. > > It first says that PCI memory resources contain the same values that the > PCI device has in its BAR. It then goes on to say that they are CPU > physical addresses. That is not true. > > For example, DC21285 systems always have done this as: the PCI bars > contain the _bus_ addresses, which tend to be in the range 0 to > 0x7fffffff. These correspond with a CPU physical address of > 0x80000000 to 0xffffffff. The PCI bus resources for IOMEM resources > contains the CPU physical address of the mapping. It is a commit log wording problem, I exactly meant what you said, I will reword it (or remove "ie BARs" from it, since it is misleading). I think that the word "BAR" is a bit misused in helpers function like: pci_resource_{start/end/len} too but as long as we all know what that means (and I write proper commit logs :)) it is all fine. > > On platforms where the mapping between CPU and BUS address is not a 1:1 > > mapping this is erroneous, in that an additional shift is applied to > > an already fixed-up offset passed from userspace. > > Yes, I think this is a correct patch inspite of the description. :) Great, I will reword it and wait for comments on patch 1 that changes pci_mmap_fits() (it does not affect ARM, but would like to get both changes in coherently - ie if I am asked to change patch 1 I will probably have to change this patch too). Thanks, Lorenzo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 17a26c1..b56fa2d 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -626,21 +626,15 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine) { - struct pci_sys_data *root = dev->sysdata; - unsigned long phys; - - if (mmap_state == pci_mmap_io) { + if (mmap_state == pci_mmap_io) return -EINVAL; - } else { - phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT); - } /* * Mark this as IO */ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - if (remap_pfn_range(vma, vma->vm_start, phys, + if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, vma->vm_end - vma->vm_start, vma->vm_page_prot)) return -EAGAIN;
The pci_mmap_page_range() API should be written to expect offset values representing PCI memory resource addresses as seen by user space, through the pci_resource_to_user() API. ARM relies on the standard implementation of pci_resource_to_user() which actually is an identity map and exports to user space PCI memory resources as they are stored in PCI devices resources (ie BARs) which represent CPU physical addresses (fixed-up using BUS to CPU address conversions) not PCI bus addresses. On platforms where the mapping between CPU and BUS address is not a 1:1 mapping this is erroneous, in that an additional shift is applied to an already fixed-up offset passed from userspace. Hence, this patch removes the mem_offset from the pgoff calculation since the offset as passed from user space already represents the CPU physical address corresponding to the resource to be mapped, ie no additional offset should be applied. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> --- arch/arm/kernel/bios32.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-)