| Message ID | 20140901114238.GB24594@arm.com |
|---|---|
| State | New |
| Headers | show |
Hi Will, On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon <will.deacon@arm.com> wrote: > Hi Tirumalesh, > > On Wed, Aug 27, 2014 at 07:02:21PM +0100, c.tirumalesh@gmail.com wrote: >> From: Tirumalesh Chalamarla <tchalamarla@cavium.com> >> >> This patch modifes output_mask calculation logic for stage 1 and allow >> max possible value supported by SMMU implementaions for translations, >> where stage 2 is bypassed. >> >> Erlier it is not possible to access full supported PA address with stage 1, >> even if it is supported by SMMU and stage 2 is bypass. > > I'm trying to understand what you're getting at here. Essentially, you want > to use the full stage-1 output range for a stage-1 only MMU, right? > YES, restrict stage 1 out put to VA_BITS only if stage 2 is needed (i.e for NESTED_TRANSLATIONS). > The code is currently structured to truncate that to the stage-2 input size > for nested translation. However, I think that's better solved by faking the > ID registers in the virtual SMMU instead of posing these restrictions on the > host as well. > This sounds good, the only problem is, it is too much bound to virtual SMMU. There is no harm in changing/checking the stage 1 output mask, if stage 2 present, in host also. > Assuming I understand the problem correctly, why not simply remove the > truncation from the existing code (untested patch below)? Does that not > work for you? > This will not restrict stage 1 out put to VA_BITS, even for two level translations. this results in non debuggable problems if we configure incorrectly. there is no harm in checking the condition for nested translations, as i did in my patch. Regards, Tirumalesh. > Will > > --->8 > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index 2b1271658bfa..a02d05793a73 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -1917,21 +1917,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) > /* ID2 */ > id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); > size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); > - > - /* > - * Stage-1 output limited by stage-2 input size due to pgd > - * allocation (PTRS_PER_PGD). > - */ > - if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { > -#ifdef CONFIG_64BIT > - smmu->s1_output_size = min_t(unsigned long, VA_BITS, size); > -#else > - smmu->s1_output_size = min(32UL, size); > -#endif > - } else { > - smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, > - size); > - } > + smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size); > > /* The stage-2 output mask is also applied for bypass */ > size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Sep 01, 2014 at 02:49:58PM +0100, tirumalesh chalamarla wrote: > On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon <will.deacon@arm.com> wrote: > > Assuming I understand the problem correctly, why not simply remove the > > truncation from the existing code (untested patch below)? Does that not > > work for you? > > > > This will not restrict stage 1 out put to VA_BITS, even for two level > translations. this results in non debuggable problems > if we configure incorrectly. there is no harm in checking the > condition for nested translations, as i did in my patch. Right, but restricting stage-1 output to VA_BITS doesn't make sense; remember it's not the same kernel writing the stage-1 and stage-2 tables. Will -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Sep 1, 2014 at 8:12 AM, Will Deacon <will.deacon@arm.com> wrote: > On Mon, Sep 01, 2014 at 02:49:58PM +0100, tirumalesh chalamarla wrote: >> On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon <will.deacon@arm.com> wrote: >> > Assuming I understand the problem correctly, why not simply remove the >> > truncation from the existing code (untested patch below)? Does that not >> > work for you? >> > >> >> This will not restrict stage 1 out put to VA_BITS, even for two level >> translations. this results in non debuggable problems >> if we configure incorrectly. there is no harm in checking the >> condition for nested translations, as i did in my patch. > > Right, but restricting stage-1 output to VA_BITS doesn't make sense; > remember it's not the same kernel writing the stage-1 and stage-2 tables. > Yes, if we restrict driver by limiting either one and removing NESTED altogether, i don't have a problem with this approach. Regards, Tirumalesh. > Will -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 2b1271658bfa..a02d05793a73 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1917,21 +1917,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) /* ID2 */ id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); - - /* - * Stage-1 output limited by stage-2 input size due to pgd - * allocation (PTRS_PER_PGD). - */ - if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { -#ifdef CONFIG_64BIT - smmu->s1_output_size = min_t(unsigned long, VA_BITS, size); -#else - smmu->s1_output_size = min(32UL, size); -#endif - } else { - smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, - size); - } + smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size); /* The stage-2 output mask is also applied for bypass */ size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);