| Message ID | 1404169773-20264-5-git-send-email-greg.bellows@linaro.org |
|---|---|
| State | New |
| Headers | show |
On Mon, Jun 30, 2014 at 06:09:04PM -0500, greg.bellows@linaro.org wrote: > From: Fabian Aggeler <aggelerf@ethz.ch> > > arm_is_secure() function allows to determine CPU security state > if the CPU implements Security Extensions/EL3. > arm_is_secure_below_el3() returns true if CPU is in secure state > below EL3. > > Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> > Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> > Signed-off-by: Greg Bellows <greg.bellows@linaro.org> > --- > target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index ffc51f2..aba077b 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -726,6 +726,44 @@ static inline int arm_feature(CPUARMState *env, int feature) > return (env->features & (1ULL << feature)) != 0; > } > > + > +/* Return true if exception level below EL3 is in secure state */ > +static inline bool arm_is_secure_below_el3(CPUARMState *env) > +{ > +#if !defined(CONFIG_USER_ONLY) > + if (arm_feature(env, ARM_FEATURE_EL3)) { > + return !(env->cp15.scr_el3 & SCR_NS); > + } else if (arm_feature(env, ARM_FEATURE_EL2)) { > + return false; > + } else { > + /* IMPDEF: QEMU defaults to non-secure */ > + return false; > + } > +#else > + return false; > +#endif > +} Should we be #ifdefing the entire arm_is_secure_below_el3() as it is not called from user-only code? > + > +/* Return true if the processor is in secure state */ > +static inline bool arm_is_secure(CPUARMState *env) > +{ > +#if !defined(CONFIG_USER_ONLY) > + if (arm_feature(env, ARM_FEATURE_EL3)) { > + if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) { > + /* CPU currently in Aarch64 state and EL3 */ > + return true; > + } else if (!env->aarch64 && > + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { > + /* CPU currently in Aarch32 state and monitor mode */ > + return true; > + } > + } > + return arm_is_secure_below_el3(env); > +#else > + return false; > +#endif > +} > + > /* Return true if the specified exception level is running in AArch64 state. */ > static inline bool arm_el_is_aa64(CPUARMState *env, int el) > { > -- > 1.8.3.2 >
Yes, this makes sense, I will update for v5. Regards, Greg On 1 July 2014 03:17, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > On Mon, Jun 30, 2014 at 06:09:04PM -0500, greg.bellows@linaro.org wrote: > > From: Fabian Aggeler <aggelerf@ethz.ch> > > > > arm_is_secure() function allows to determine CPU security state > > if the CPU implements Security Extensions/EL3. > > arm_is_secure_below_el3() returns true if CPU is in secure state > > below EL3. > > > > Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> > > Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> > > Signed-off-by: Greg Bellows <greg.bellows@linaro.org> > > --- > > target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 38 insertions(+) > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index ffc51f2..aba077b 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -726,6 +726,44 @@ static inline int arm_feature(CPUARMState *env, int > feature) > > return (env->features & (1ULL << feature)) != 0; > > } > > > > + > > +/* Return true if exception level below EL3 is in secure state */ > > +static inline bool arm_is_secure_below_el3(CPUARMState *env) > > +{ > > +#if !defined(CONFIG_USER_ONLY) > > + if (arm_feature(env, ARM_FEATURE_EL3)) { > > + return !(env->cp15.scr_el3 & SCR_NS); > > + } else if (arm_feature(env, ARM_FEATURE_EL2)) { > > + return false; > > + } else { > > + /* IMPDEF: QEMU defaults to non-secure */ > > + return false; > > + } > > +#else > > + return false; > > +#endif > > +} > > Should we be #ifdefing the entire arm_is_secure_below_el3() as it is > not called from user-only code? > > > > > + > > +/* Return true if the processor is in secure state */ > > +static inline bool arm_is_secure(CPUARMState *env) > > +{ > > +#if !defined(CONFIG_USER_ONLY) > > + if (arm_feature(env, ARM_FEATURE_EL3)) { > > + if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) { > > + /* CPU currently in Aarch64 state and EL3 */ > > + return true; > > + } else if (!env->aarch64 && > > + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { > > + /* CPU currently in Aarch32 state and monitor mode */ > > + return true; > > + } > > + } > > + return arm_is_secure_below_el3(env); > > +#else > > + return false; > > +#endif > > +} > > + > > /* Return true if the specified exception level is running in AArch64 > state. */ > > static inline bool arm_el_is_aa64(CPUARMState *env, int el) > > { > > -- > > 1.8.3.2 > > >
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ffc51f2..aba077b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -726,6 +726,44 @@ static inline int arm_feature(CPUARMState *env, int feature) return (env->features & (1ULL << feature)) != 0; } + +/* Return true if exception level below EL3 is in secure state */ +static inline bool arm_is_secure_below_el3(CPUARMState *env) +{ +#if !defined(CONFIG_USER_ONLY) + if (arm_feature(env, ARM_FEATURE_EL3)) { + return !(env->cp15.scr_el3 & SCR_NS); + } else if (arm_feature(env, ARM_FEATURE_EL2)) { + return false; + } else { + /* IMPDEF: QEMU defaults to non-secure */ + return false; + } +#else + return false; +#endif +} + +/* Return true if the processor is in secure state */ +static inline bool arm_is_secure(CPUARMState *env) +{ +#if !defined(CONFIG_USER_ONLY) + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) { + /* CPU currently in Aarch64 state and EL3 */ + return true; + } else if (!env->aarch64 && + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { + /* CPU currently in Aarch32 state and monitor mode */ + return true; + } + } + return arm_is_secure_below_el3(env); +#else + return false; +#endif +} + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) {